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1. 发明授权

US06653735B1 CVD silicon carbide layer as a BARC and hard mask for gate patterning 有权
标题翻译： CVD碳化硅层作为BARC和用于栅极图案化的硬掩模
公开(公告)号：US06653735B1
公开(公告)日：2003-11-25
申请号：US10209447
申请日：2002-07-30
申请人： Chih Yuh Yang , Douglas Bonser , Pei-Yuan Gao , Lu You
发明人： Chih Yuh Yang , Douglas Bonser , Pei-Yuan Gao , Lu You
IPC分类号： H01L2348
CPC分类号： H01L21/0276 , H01L21/0332 , H01L21/32139
摘要： A BARC comprising materials having a lower pinhole density than that of silicon oxynitride and materials having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of polysilicon than that of amorphous carbon is employed to reduce deformation of a pattern to be formed in a patternable layer. The patternable layer is formed over a substrate. A multi-layered anti-reflective coating is formed over the patternable layer. A photoresist pattern is formed on the coating. The coating may comprise an amorphous carbon layer formed over the patternable layer and a SiC layer having a lower pinhole density than the pinhole density of SiON formed over the amorphous carbon layer. The coating may also be formed over a polysilicon layer and comprise a thermal expansion buffer layer having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of polysilicon than that of amorphous carbon.
摘要翻译：使用包含具有比氮氧化硅更小的针孔密度的材料的BARC和具有比非晶碳更接近于多晶硅热膨胀系数的热膨胀系数的材料来减少将形成的图案的变形可图案层。可图案层形成在衬底上。在可图案层上形成多层抗反射涂层。在涂层上形成光致抗蚀剂图案。涂层可以包括在可图案层上形成的无定形碳层和具有比在无定形碳层上形成的SiON的针孔密度小的针孔密度的SiC层。涂层也可以形成在多晶硅层上，并且包括热膨胀缓冲层，其热膨胀系数比无定形碳的热膨胀系数更接近于多晶硅的热膨胀系数。

2. 发明授权

US06764949B2 Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication 有权
公开(公告)号：US06764949B2
公开(公告)日：2004-07-20
申请号：US10334392
申请日：2002-12-30
申请人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Darin Chan , Philip A. Fisher , Christopher F. Lyons , Mark S. Chang , Pei-Yuan Gao , Marilyn I. Wright , Lu You , Srikanteswara Dakshina-Murthy
发明人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Darin Chan , Philip A. Fisher , Christopher F. Lyons , Mark S. Chang , Pei-Yuan Gao , Marilyn I. Wright , Lu You , Srikanteswara Dakshina-Murthy
IPC分类号： H01L2144
CPC分类号： H01L21/32139 , H01L21/0332
摘要： A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning. The lowest layer of the hardmask stack is preferably amorphous carbon to facilitate easy removal of the hardmask stack from underlying materials by an ashing process.

3. 发明授权

US06750127B1 Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance 有权
标题翻译：使用具有改善的耐蚀性的非晶碳制造半导体器件的方法
公开(公告)号：US06750127B1
公开(公告)日：2004-06-15
申请号：US10367407
申请日：2003-02-14
申请人： Mark S. Chang , Darin Chan , Chih Yuh Yang , Lu You , Scott A. Bell , Srikanteswara Dakshina-Murthy , Douglas J. Bonser
发明人： Mark S. Chang , Darin Chan , Chih Yuh Yang , Lu You , Scott A. Bell , Srikanteswara Dakshina-Murthy , Douglas J. Bonser
IPC分类号： H01L213205
CPC分类号： H01L21/32139 , H01L21/0332 , H01L21/0337
摘要： An amorphous carbon layer is implanted with one or more dopants that enhance the etch resistivity of the amorphous carbon to etchants such as chlorine and HBr that are typically used to etch polysilicon. Such a layer may be pattern to form a handmask for etching polysilicon that provides improved pattern transfer accuracy compared to conventional undoped amorphous carbon.
摘要翻译：注入一个或多个掺杂剂的无定形碳层，其增强无定形碳对通常用于蚀刻多晶硅的蚀刻剂如氯和HBr的蚀刻电阻率。这样的层可以被图案化以形成用于蚀刻多晶硅的手掩模，其与常规未掺杂的无定形碳相比提供改进的图案转印精度。

4. 发明授权

US06764947B1 Method for reducing gate line deformation and reducing gate line widths in semiconductor devices 有权
标题翻译：减少半导体器件栅极线变形和减小栅极线宽度的方法
公开(公告)号：US06764947B1
公开(公告)日：2004-07-20
申请号：US10366801
申请日：2003-02-14
申请人： Darin Chan , Douglas J. Bonser , Marina V. Plat , Marilyn I. Wright , Chih Yuh Yang , Lu You , Scott A. Bell , Philip A. Fisher
发明人： Darin Chan , Douglas J. Bonser , Marina V. Plat , Marilyn I. Wright , Chih Yuh Yang , Lu You , Scott A. Bell , Philip A. Fisher
IPC分类号： H01L214763
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/28123 , H01L21/32139
摘要： A silicon oxide stress relief portion is provided between an amorphous carbon hardmask and a polysilicon layer to be etched to form a gate line. The stress relief portion relieves stress between the hardmask and the polysilicon, thereby reducing the risk of delamination of the hardmask prior to patterning of the polysilicon. The stress relief portion may be trimmed prior to patterning and used as an etch mask for patterning the polysilicon. The amorphous carbon hardmasked may be trimmed prior to patterning the stress relief portion to achieve a further reduction in gate line width.
摘要翻译：在非晶碳硬掩模和待蚀刻的多晶硅层之间设置氧化硅应力释放部分以形成栅极线。应力消除部分减轻硬掩模和多晶硅之间的应力，从而降低在多晶硅图案化之前硬掩模的分层的风险。应力消除部分可以在图案化之前被修整，并且用作图案化多晶硅的蚀刻掩模。在图案化应力释放部分之前，可以修剪硬掩模的无定形碳以实现栅极线宽度的进一步降低。

5. 发明授权

US06864556B1 CVD organic polymer film for advanced gate patterning 失效
标题翻译：用于先进栅极图案化的CVD有机聚合物膜
公开(公告)号：US06864556B1
公开(公告)日：2005-03-08
申请号：US10335445
申请日：2002-12-31
申请人： Lu You , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Richard J. Huang , Christopher F. Lyons , Mark S. Chang , Marilyn I. Wright
发明人： Lu You , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Richard J. Huang , Christopher F. Lyons , Mark S. Chang , Marilyn I. Wright
IPC分类号： G03F7/09 , H01L21/033 , H01L21/28 , H01L21/3213 , H01L21/47 , H01L31/0232
CPC分类号： H01L21/32139 , G03F7/091 , H01L21/0332 , H01L21/28123 , H01L29/785
摘要： A bottom anti-reflective coating comprising an organic polymer layer having substantially no nitrogen and a low compressive stress in relation to a polysilicon layer is employed as the lower layer of a bi-layer antireflective coating/hardmask structure to reduce deformation of a pattern to be formed in a patternable layer. The organic polymer layer is substantially transparent to visible radiation, enabling better detection of alignment marks during a semiconductor device fabrication process and improving overlay accuracy. The organic polymer layer provides excellent step coverage and may be advantageously used in the fabrication of structures such as FinFETs.
摘要翻译：采用底层抗反射涂层，其包含基本上不含氮的有机聚合物层和相对于多晶硅层的低压缩应力作为双层抗反射涂层/硬掩模结构的下层，以减少图案的变形形成在可图案层中。有机聚合物层对可见辐射基本上是透明的，能够在半导体器件制造过程中更好地检测对准标记并提高覆盖精度。有机聚合物层提供优异的台阶覆盖，并且可以有利地用于制造诸如FinFET的结构。

6. 发明授权

US06849530B2 Method for semiconductor gate line dimension reduction 失效
公开(公告)号：US06849530B2
公开(公告)日：2005-02-01
申请号：US10334337
申请日：2002-12-30
申请人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Christopher F. Lyons
发明人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Christopher F. Lyons
IPC分类号： H01L21/28 , H01L21/4763
CPC分类号： H01L21/28123
摘要： To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

7. 发明授权

US6156658A Ultra-thin resist and silicon/oxide hard mask for metal etch 有权
标题翻译：用于金属蚀刻的超薄抗蚀剂和硅/氧化物硬掩模
公开(公告)号：US6156658A
公开(公告)日：2000-12-05
申请号：US203774
申请日：1998-12-02
申请人： Fei Wang , Christopher F. Lyons , Khanh B. Nguyen , Scott A. Bell , Harry J. Levinson , Chih Yuh Yang
发明人： Fei Wang , Christopher F. Lyons , Khanh B. Nguyen , Scott A. Bell , Harry J. Levinson , Chih Yuh Yang
IPC分类号： H01L21/027 , H01L21/3213 , H01L21/44 , H01L21/302 , H01L21/461
CPC分类号： H01L21/32139 , H01L21/0274 , H01L21/32136
摘要： In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a silicon layer over the oxide layer; depositing an ultra-thin photoresist over the silicon layer, the ultra-thin photoresist having a thickness less than about 2,000 .ANG.; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the silicon layer; etching the exposed portion of the silicon layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.
摘要翻译：在一个实施例中，本发明涉及一种形成金属线的方法，包括以下步骤：提供包括金属层的半导体衬底，金属层上的氧化物层和氧化物层上的硅层; 在硅层上沉积超薄光致抗蚀剂，超薄光致抗蚀剂的厚度小于约2,000安培; 用波长约250nm或更小的电磁辐射照射超薄光致抗蚀剂; 开发暴露一部分硅层的超薄光刻胶; 蚀刻暴露出氧化物层的一部分的硅层的暴露部分; 蚀刻暴露出金属层的一部分的氧化物层的暴露部分; 并且蚀刻金属层的暴露部分从而形成金属线。

8. 发明授权

US06440640B1 Thin resist with transition metal hard mask for via etch application 有权
标题翻译：具有过渡金属硬掩模的薄抗蚀剂，用于通孔蚀刻应用
公开(公告)号：US06440640B1
公开(公告)日：2002-08-27
申请号：US09703092
申请日：2000-10-31
申请人： Chih Yuh Yang , Christopher F. Lyons , Harry J. Levinson , Khanh B. Nguyen , Fei Wang , Scott A. Bell
发明人： Chih Yuh Yang , Christopher F. Lyons , Harry J. Levinson , Khanh B. Nguyen , Fei Wang , Scott A. Bell
IPC分类号： G03C500
CPC分类号： H01L21/76816 , H01L21/0276 , H01L21/0332 , H01L21/0338 , H01L21/32139
摘要： A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a transition metal layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the transition metal layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the transition metal layer. The first etch step includes an etch chemistry that is selective to the transition metal layer over the ultra-thin photoresist layer and the dielectric layer. The transition metal layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.
摘要翻译：提供一种形成通孔结构的方法。在该方法中，在覆盖第一金属层的抗反射涂层（ARC）层上形成电介质层; 并且在介电层上形成过渡金属层。在过渡金属层上形成超薄光致抗蚀剂层，并用短波长辐射对超薄光致抗蚀剂层进行构图，以形成通孔图案。在第一蚀刻步骤期间，将图案化超薄光致抗蚀剂层用作掩模，以将通孔图案转印到过渡金属层。第一蚀刻步骤包括对超薄光致抗蚀剂层和电介质层上的过渡金属层有选择性的蚀刻化学品。在第二蚀刻步骤期间，过渡金属层用作硬掩模，以通过蚀刻介电层的部分形成与通孔图案相对应的接触孔。

9. 发明授权

US06200907B1 Ultra-thin resist and barrier metal/oxide hard mask for metal etch 有权
标题翻译：用于金属蚀刻的超薄抗蚀剂和阻挡金属/氧化物硬掩模
公开(公告)号：US06200907B1
公开(公告)日：2001-03-13
申请号：US09204216
申请日：1998-12-02
申请人： Fei Wang , Christopher F. Lyons , Khanh B. Nguyen , Scott A. Bell , Harry J. Levinson , Chih Yuh Yang
发明人： Fei Wang , Christopher F. Lyons , Khanh B. Nguyen , Scott A. Bell , Harry J. Levinson , Chih Yuh Yang
IPC分类号： H01L21302
CPC分类号： H01L21/32139 , H01L21/0275 , H01L21/0332 , H01L21/31111 , H01L21/31116 , H01L21/76838
摘要： In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a barrier metal layer over the oxide layer; depositing an ultra-thin photoresist over the barrier metal layer, the ultra-thin photoresist having a thickness less than about 2,000 Å; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the barrier metal layer; etching the exposed portion of the barrier metal layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.
摘要翻译：在一个实施例中，本发明涉及一种形成金属线的方法，包括以下步骤：提供包括金属层的半导体衬底，金属层上的氧化物层和氧化物层上的阻挡金属层; 在阻挡金属层上沉积超薄光致抗蚀剂，超薄光致抗蚀剂具有小于约的厚度; 用波长约250nm或更小的电磁辐射照射超薄光致抗蚀剂; 显影暴露一部分阻挡金属层的超薄光刻胶; 蚀刻暴露部分氧化物层的阻挡金属层的暴露部分; 蚀刻暴露出金属层的一部分的氧化物层的暴露部分; 并且蚀刻金属层的暴露部分从而形成金属线。

10. 发明授权

US06184128B2 Method using a thin resist mask for dual damascene stop layer etch 有权
标题翻译：使用薄抗蚀剂掩模的双镶嵌停止层蚀刻方法
公开(公告)号：US06184128B2
公开(公告)日：2001-02-06
申请号：US09497222
申请日：2000-01-31
申请人： Fei Wang , Christopher F. Lyons , Khanh B. Nguyen , Scott A. Bell , Harry J. Levinson , Chih Yuh Yang
发明人： Fei Wang , Christopher F. Lyons , Khanh B. Nguyen , Scott A. Bell , Harry J. Levinson , Chih Yuh Yang
IPC分类号： H01L214763
CPC分类号： H01L21/7681 , H01L21/31144
摘要： In one embodiment, the present invention relates to a dual damascene method involving the steps of providing a substrate having a first low k material layer; forming a first hard mask layer over the first low k material layer; patterning a first opening having a first width in the first hard mask layer using a first photoresist thereby exposing a portion of the first low k material layer; removing the first photoresist; depositing a second low k material layer over the patterned first hard mask layer and the exposed portion of the first low k material layer; forming a second hard mask layer over the second low k material layer; patterning a second opening having a width larger than the first width in the second hard mask layer using a second photoresist thereby exposing a portion of the second low k material layer; anisotropically etching the exposed portions of the first and second low k material layers; and removing the second photoresist, wherein and at least one of the first photoresist and the second photoresist have a thickness of about 1,500 Å or less.
摘要翻译：在一个实施例中，本发明涉及一种双镶嵌方法，包括以下步骤：提供具有第一低k材料层的基底; 在所述第一低k材料层上形成第一硬掩模层; 使用第一光致抗蚀剂构图在第一硬掩模层中具有第一宽度的第一开口，从而暴露第一低k材料层的一部分; 去除第一光致抗蚀剂; 在图案化的第一硬掩模层和第一低k材料层的暴露部分上沉积第二低k材料层; 在所述第二低k材料层上形成第二硬掩模层; 使用第二光致抗蚀剂构图在第二硬掩模层中形成具有大于第一宽度的宽度的第二开口，从而暴露第二低k材料层的一部分; 各向异性地蚀刻第一和第二低k材料层的暴露部分; 并且去除所述第二光致抗蚀剂，其中所述第一光致抗蚀剂和所述第二光致抗蚀剂中的至少一个具有大约等于或小于1500埃的厚度。

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