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1. 发明授权

US07205241B2 Method for manufacturing semiconductor device with contact body extended in direction of bit line 失效
标题翻译：具有沿位线方向延伸的接触体的半导体器件的制造方法
公开(公告)号：US07205241B2
公开(公告)日：2007-04-17
申请号：US10731931
申请日：2003-12-10
申请人： Chang-min Park , Jung-hyeon Lee , Han-ku Cho , Joon-soo Park
发明人： Chang-min Park , Jung-hyeon Lee , Han-ku Cho , Joon-soo Park
IPC分类号： H01L21/302
CPC分类号： H01L21/76897 , H01L21/76895 , H01L27/10855 , H01L27/10894 , H01L28/91 , Y10S438/942
摘要： Methods for manufacturing semiconductor devices with contact bodies extended in a direction of a bit line to increase the contact area between a contact body and a storage electrode is provided. In one aspect a method includes forming gate lines on a semiconductor substrate, forming a first insulating layer to cover the gate lines, forming first contact pads and second contact pads, which are electrically connected to the semiconductor substrate between the gate lines, by penetrating the first insulating layer. Further, a second insulating layer is formed to cover the first contact pads and the second contact pads, and bit lines are formed across over the gate lines and are electrically connected to the second contact pads by penetrating the second insulating layer. In addition, a third insulating layer is formed to cover the bit lines and is selectively etched to form a band-type opening that crosses the bit lines and exposes the first contact pads.
摘要翻译：提供了制造具有沿位线方向延伸的接触体以增加接触体与存储电极之间的接触面积的半导体器件的方法。在一个方面，一种方法包括在半导体衬底上形成栅极线，形成第一绝缘层以覆盖栅极线，形成第一接触焊盘和第二接触焊盘，这些接触焊盘和第二接触焊盘通过穿透栅极线与半导体衬底电连接第一绝缘层。此外，形成第二绝缘层以覆盖第一接触焊盘和第二接触焊盘，并且位线横跨栅极线形成，并且通过穿透第二绝缘层而电连接到第二接触焊盘。此外，形成第三绝缘层以覆盖位线，并且被选择性地蚀刻以形成穿过位线并暴露第一接触焊盘的带状开口。

2. 发明申请

US20110269294A1 METHOD OF FORMING A HARD MASK AND METHOD OF FORMING A FINE PATTERN OF SEMICONDUCTOR DEVICE USING THE SAME 有权
标题翻译：形成硬掩模的方法和使用其形成半导体器件的精细图案的方法
公开(公告)号：US20110269294A1
公开(公告)日：2011-11-03
申请号：US13181655
申请日：2011-07-13
申请人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
发明人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
IPC分类号： H01L21/762
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/0338 , H01L21/3088 , H01L21/31144 , H01L21/76816
摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.
摘要翻译：形成硬掩模的方法采用双重图案化技术。第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。第一牺牲图案的特征彼此间隔开第一间距。然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

3. 发明申请

US20100197139A1 METHOD OF FORMING A HARD MASK AND METHOD OF FORMING A FINE PATTERN OF SEMICONDUCTOR DEVICE USING THE SAME 有权
标题翻译：形成硬掩模的方法和使用其形成半导体器件的精细图案的方法
公开(公告)号：US20100197139A1
公开(公告)日：2010-08-05
申请号：US12759771
申请日：2010-04-14
申请人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
发明人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
IPC分类号： H01L21/311
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/0338 , H01L21/3088 , H01L21/31144 , H01L21/76816
摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.
摘要翻译：形成硬掩模的方法采用双重图案化技术。第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。第一牺牲图案的特征彼此间隔开第一间距。然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

4. 发明授权

US07732341B2 Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same 有权
标题翻译：形成硬掩模的方法和使用其形成半导体器件的精细图案的方法
公开(公告)号：US07732341B2
公开(公告)日：2010-06-08
申请号：US11727124
申请日：2007-03-23
申请人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
发明人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/0338 , H01L21/3088 , H01L21/31144 , H01L21/76816
摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.
摘要翻译：形成硬掩模的方法采用双重图案化技术。第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。第一牺牲图案的特征彼此间隔开第一间距。然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

5. 发明授权

US08278221B2 Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same 有权
标题翻译：形成硬掩模的方法和使用其形成半导体器件的精细图案的方法
公开(公告)号：US08278221B2
公开(公告)日：2012-10-02
申请号：US13181655
申请日：2011-07-13
申请人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
发明人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
IPC分类号： H01L21/331
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/0338 , H01L21/3088 , H01L21/31144 , H01L21/76816
摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.
摘要翻译：形成硬掩模的方法采用双重图案化技术。第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。第一牺牲图案的特征彼此间隔开第一间距。然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

6. 发明授权

US08003543B2 Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same 有权
标题翻译：形成硬掩模的方法和使用其形成半导体器件的精细图案的方法
公开(公告)号：US08003543B2
公开(公告)日：2011-08-23
申请号：US12759771
申请日：2010-04-14
申请人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
发明人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/0338 , H01L21/3088 , H01L21/31144 , H01L21/76816
摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.
摘要翻译：形成硬掩模的方法采用双重图案化技术。第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。第一牺牲图案的特征彼此间隔开第一间距。然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

7. 发明申请

US20080090419A1 Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same 有权
标题翻译：形成硬掩模的方法和使用其形成半导体器件的精细图案的方法
公开(公告)号：US20080090419A1
公开(公告)日：2008-04-17
申请号：US11727124
申请日：2007-03-23
申请人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
发明人： Cha-won Koh , Han-ku Cho , Jeong-lim Nam , Gi-sung Yeo , Joon-soo Park , Ji-young Lee
IPC分类号： H01L21/311
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/0338 , H01L21/3088 , H01L21/31144 , H01L21/76816
摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.
摘要翻译：形成硬掩模的方法采用双重图案化技术。第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。第一牺牲图案的特征彼此间隔开第一间距。然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

8. 发明申请

US20070284623A1 Semiconductor device having vertical channel transistor 审中-公开
标题翻译：具有垂直沟道晶体管的半导体器件
公开(公告)号：US20070284623A1
公开(公告)日：2007-12-13
申请号：US11802647
申请日：2007-05-24
申请人： Sang-Jin Kim , Gi-sung Yeo , Joon-soo Park , Han-ku Cho , Sang-gyun Woo , Min-jong Hong
发明人： Sang-Jin Kim , Gi-sung Yeo , Joon-soo Park , Han-ku Cho , Sang-gyun Woo , Min-jong Hong
IPC分类号： H01L29/76 , H01L29/745
CPC分类号： H01L27/0207 , H01L27/10823 , H01L27/10876 , H01L29/4236 , H01L29/66666 , H01L29/7827
摘要： A semiconductor device includes a substrate, and a plurality of active pillars arranged in a pattern of alternating even and odd rows and alternating even and odd columns, each active pillar extending from the substrate and including a channel portion, wherein the odd columns include active pillars spaced at a first pitch, the first pitch being determined in the column direction, the even columns include active pillars spaced at the first pitch, the even rows include active pillars spaced at a third pitch, the third pitch being determined in the row direction the odd rows include active pillars spaced at the third pitch, and active pillars in the even columns are offset by a second pitch from active pillars in the odd columns, the second pitch being determined in the column direction.
摘要翻译：半导体器件包括衬底和布置成交替的偶数行和奇数行以及交替的偶数和奇数列的多个有源柱，每个有源柱从衬底延伸并且包括沟道部分，其中奇数列包括有源柱以第一间距间隔开，第一间距是在列方向上确定的，偶数列包括以第一节距间隔开的活动柱，偶数行包括以第三节距间隔开的有效柱，第三间距在行方向上确定奇数行包括在第三间距处间隔开的活动柱，并且偶数列中的活动柱由奇数列中的活动柱偏移第二间距，第二间距在列方向上确定。

9. 发明申请

US20060019184A1 Multi-exposure lithography method and system providing increased overlay accuracy 有权
公开(公告)号：US20060019184A1
公开(公告)日：2006-01-26
申请号：US11207367
申请日：2005-08-19
申请人： Joon-soo Park , Chang-min Park
发明人： Joon-soo Park , Chang-min Park
IPC分类号： G03F9/00
CPC分类号： G03F7/70633 , G03F7/70433 , G03F7/70466
摘要： Multi-exposure lithography methods and systems that provide improved overlay accuracy. In one aspect of the invention, a method for multi-exposure lithography comprises determining overlay parameters corresponding to each of a plurality of sub-layouts, inputting the overlay parameters into an exposure system, exposing each sub-layout to photoresist on a wafer by using the exposure system, wherein prior to the exposure process for a given sub-layout, a correction process is performed for the sub-layout using a corresponding overlay parameter to correct an overlay of the sub-layout, and developing the exposed photoresist after exposing all of the sub-layouts.

10. 发明授权

US06960414B2 Multi-exposure lithography method and system providing increased overlay accuracy 有权
标题翻译：多曝光光刻方法和系统提供更高的覆盖精度
公开(公告)号：US06960414B2
公开(公告)日：2005-11-01
申请号：US10305681
申请日：2002-11-27
申请人： Joon-soo Park , Chang-min Park
发明人： Joon-soo Park , Chang-min Park
IPC分类号： G03F9/00 , G03F7/20 , H01L21/027 , G06F9/00
CPC分类号： G03F7/70633 , G03F7/70433 , G03F7/70466
摘要： Multi-exposure lithography methods and systems that provide improved overlay accuracy. In one aspect of the invention, a method for multi-exposure lithography comprises determining overlay parameters corresponding to each of a plurality of sub-layouts, inputting the overlay parameters into an exposure system, exposing each sub-layout to photoresist on a wafer by using the exposure system, wherein prior to the exposure process for a given sub-layout, a correction process is performed for the sub-layout using a corresponding overlay parameter to correct an overlay of the sub-layout, and developing the exposed photoresist after exposing all of the sub-layouts.
摘要翻译：提供改进的重叠精度的多曝光光刻方法和系统。在本发明的一个方面，一种用于多曝光光刻的方法包括确定与多个子布局中的每一个对应的覆盖参数，将覆盖参数输入到曝光系统中，通过使用将曝光每个子布局曝光在晶片上的光致抗蚀剂曝光系统，其中在给定子布局的曝光处理之前，使用对应的重叠参数对子布局执行校正处理，以校正子布局的叠加，以及在曝光全部之后显影曝光的光致抗蚀剂的子布局。

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