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1. 发明申请

US20060138559A1 Flash memories having at least one resistance pattern on gate pattern and methods of fabricating the same 审中-公开
标题翻译：在栅极图案上具有至少一个电阻图案的闪存及其制造方法
公开(公告)号：US20060138559A1
公开(公告)日：2006-06-29
申请号：US11317595
申请日：2005-12-23
申请人： Dong-Jun Lee , Keon-Soo Kim , Hyun-Chul Back , Seong-Soon Cho
发明人： Dong-Jun Lee , Keon-Soo Kim , Hyun-Chul Back , Seong-Soon Cho
IPC分类号： H01L29/00 , H01L21/8234
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11543
摘要： Flash memories and methods of manufacturing the same provide at least one resistance pattern on a gate pattern, and are capable of increasing a process margin in the semiconductor fabrication process. Gate patterns and bit line patterns are sequentially formed in a cell array region and a peripheral circuit region of a semiconductor substrate. A bit line interlayer insulating layer is disposed to cover the bit line patterns. At least one resistance pattern is disposed on the bit line interlayer insulating layer in the cell array region of the semiconductor substrate. A planarized interlayer insulating layer is formed on the bit line interlayer insulating layer to cover the resistance pattern. Interconnection lines such as metal interconnection lines are formed on the planarized interlayer insulating layer in the cell array region and the peripheral circuit region of the semiconductor substrate.
摘要翻译：闪存及其制造方法在栅极图案上提供至少一个电阻图案，并且能够增加半导体制造工艺中的工艺裕度。栅极图案和位线图案依次形成在半导体衬底的单元阵列区域和外围电路区域中。布置位线层间绝缘层以覆盖位线图形。在半导体衬底的单元阵列区域中的位线层间绝缘层上设置至少一个电阻图案。平面化层间绝缘层形成在位线层间绝缘层上以覆盖电阻图形。互连线如金属互连线形成在电池阵列区域和半导体衬底的外围电路区域的平坦化层间绝缘层上。

2. 发明申请

US20120045901A1 METHOD OF FORMING A PATTERN STRUCTURE FOR A SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件的图案结构的方法
公开(公告)号：US20120045901A1
公开(公告)日：2012-02-23
申请号：US13212349
申请日：2011-08-18
申请人： JONG-HYUK KIM , Keon-Soo Kim , Kwang-Shik Shin , Hyun-Chul Back , Seong-Soon Cho , Young-Bae Yoon , Jung-Hwan Park
发明人： JONG-HYUK KIM , Keon-Soo Kim , Kwang-Shik Shin , Hyun-Chul Back , Seong-Soon Cho , Young-Bae Yoon , Jung-Hwan Park
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/76816
摘要： In a method of forming a pattern structure, a cut-off portion of the node-separated line of a semiconductor device is formed by a double patterning process by using a connection portion of the sacrificial mask pattern and the mask pattern to thereby improve alignment margin. The alignment margin between the mask pattern and the sacrificial mask pattern is increased to an amount of the length of the connection portion of the sacrificial mask pattern. The lines adjacent to the node-separated line include a protrusion portion protruding toward the cut-off portion of the separated line.
摘要翻译：在形成图案结构的方法中，通过使用牺牲掩模图案和掩模图案的连接部分的双重图案化工艺来形成半导体器件的节点分离线的截止部分，从而改善对准边缘。掩模图案和牺牲掩模图案之间的对准边缘增加到牺牲掩模图案的连接部分的长度的量。与节点分离线相邻的线包括向分离线的截止部分突出的突出部分。

3. 发明授权

US08759224B2 Method of forming a pattern structure for a semiconductor device 有权
标题翻译：形成半导体器件的图案结构的方法
公开(公告)号：US08759224B2
公开(公告)日：2014-06-24
申请号：US13212349
申请日：2011-08-18
申请人： Jong-Hyuk Kim , Keon-Soo Kim , Kwang-Shik Shin , Hyun-Chul Back , Seong-Soon Cho , Young-Bae Yoon , Jung-Hwan Park
发明人： Jong-Hyuk Kim , Keon-Soo Kim , Kwang-Shik Shin , Hyun-Chul Back , Seong-Soon Cho , Young-Bae Yoon , Jung-Hwan Park
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/76816
摘要： In a method of forming a pattern structure, a cut-off portion of the node-separated line of a semiconductor device is formed by a double patterning process by using a connection portion of the sacrificial mask pattern and the mask pattern to thereby improve alignment margin. The alignment margin between the mask pattern and the sacrificial mask pattern is increased to an amount of the length of the connection portion of the sacrificial mask pattern. The lines adjacent to the node-separated line include a protrusion portion protruding toward the cut-off portion of the separated line.
摘要翻译：在形成图案结构的方法中，通过使用牺牲掩模图案和掩模图案的连接部分的双重图案化工艺来形成半导体器件的节点分离线的截止部分，从而提高对准边缘。掩模图案和牺牲掩模图案之间的对准边缘增加到牺牲掩模图案的连接部分的长度的量。与节点分离线相邻的线包括向分离线的截止部分突出的突出部分。

4. 发明授权

US07671400B2 Semiconductor memory device including double spacers on sidewall of flating gate, electronic device including the same 有权
标题翻译：半导体存储器件包括在隔离栅侧壁上的双重间隔物，包括该隔离栅的电子器件
公开(公告)号：US07671400B2
公开(公告)日：2010-03-02
申请号：US12133587
申请日：2008-06-05
申请人： Joon-Sung Lim , Jong-Ho Park , Hyun-Chul Back , Sung-Hun Lee
发明人： Joon-Sung Lim , Jong-Ho Park , Hyun-Chul Back , Sung-Hun Lee
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A semiconductor memory device includes a device isolation layer formed in a semiconductor substrate to define a plurality of active regions. Floating gates are disposed on the active regions. A control gate line overlaps top surfaces of the floating gates and crosses over the active regions. The control gate line has an extending portion disposed in a gap between adjacent floating gates and overlapping sidewalls of the adjacent floating gates. First spacers are disposed on the sidewalls of the adjacent floating gates. Each of the first spacers extends along a sidewall of the active region and along a sidewall of the device isolation layer. Second spacers are disposed between outer sidewalls of the first spacers and the extending portion and are disposed above the device isolation layer. An electronic device including a semiconductor memory device and a method of fabricating a semiconductor memory device are also disclosed.
摘要翻译：半导体存储器件包括形成在半导体衬底中以限定多个有源区的器件隔离层。浮动门设置在活动区域上。控制栅极线与浮动栅极的顶表面重叠，并在有源区域上交叉。控制栅极线具有设置在相邻浮动栅极之间的间隙中的延伸部分和相邻浮动栅极的重叠侧壁之间。第一间隔件设置在相邻浮动门的侧壁上。每个第一间隔件沿着有源区的侧壁并且沿着器件隔离层的侧壁延伸。第二间隔件设置在第一间隔件的外侧壁和延伸部分之间，并且设置在装置隔离层的上方。还公开了一种包括半导体存储器件和制造半导体存储器件的方法的电子器件。

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