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1. 发明授权

US07671400B2 Semiconductor memory device including double spacers on sidewall of flating gate, electronic device including the same 有权
标题翻译：半导体存储器件包括在隔离栅侧壁上的双重间隔物，包括该隔离栅的电子器件
公开(公告)号：US07671400B2
公开(公告)日：2010-03-02
申请号：US12133587
申请日：2008-06-05
申请人： Joon-Sung Lim , Jong-Ho Park , Hyun-Chul Back , Sung-Hun Lee
发明人： Joon-Sung Lim , Jong-Ho Park , Hyun-Chul Back , Sung-Hun Lee
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A semiconductor memory device includes a device isolation layer formed in a semiconductor substrate to define a plurality of active regions. Floating gates are disposed on the active regions. A control gate line overlaps top surfaces of the floating gates and crosses over the active regions. The control gate line has an extending portion disposed in a gap between adjacent floating gates and overlapping sidewalls of the adjacent floating gates. First spacers are disposed on the sidewalls of the adjacent floating gates. Each of the first spacers extends along a sidewall of the active region and along a sidewall of the device isolation layer. Second spacers are disposed between outer sidewalls of the first spacers and the extending portion and are disposed above the device isolation layer. An electronic device including a semiconductor memory device and a method of fabricating a semiconductor memory device are also disclosed.
摘要翻译：半导体存储器件包括形成在半导体衬底中以限定多个有源区的器件隔离层。浮动门设置在活动区域上。控制栅极线与浮动栅极的顶表面重叠，并在有源区域上交叉。控制栅极线具有设置在相邻浮动栅极之间的间隙中的延伸部分和相邻浮动栅极的重叠侧壁之间。第一间隔件设置在相邻浮动门的侧壁上。每个第一间隔件沿着有源区的侧壁并且沿着器件隔离层的侧壁延伸。第二间隔件设置在第一间隔件的外侧壁和延伸部分之间，并且设置在装置隔离层的上方。还公开了一种包括半导体存储器件和制造半导体存储器件的方法的电子器件。

2. 发明授权

US09087734B2 Non-volatile memory devices with non-uniform floating gate coupling 有权
标题翻译：具有非均匀浮栅耦合的非易失性存储器件
公开(公告)号：US09087734B2
公开(公告)日：2015-07-21
申请号：US13158990
申请日：2011-06-13
申请人： Joon-Sung Lim , Jong-Ho Park , Ok-Cheon Hong , Ji-Hwan Jeon
发明人： Joon-Sung Lim , Jong-Ho Park , Ok-Cheon Hong , Ji-Hwan Jeon
IPC分类号： H01L29/788 , H01L29/66 , G11C11/34 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/11519
摘要： A memory device includes a substrate having an active region defined therein that extends linearly along a first direction. The device also includes a select line on the substrate and extending along a second direction to perpendicularly cross the active region, first and second floating gate patterns on the active region and spaced apart along the first direction, and first and second dielectric patterns on respective ones of the first and second floating gate patterns. The device further includes first and second word lines on respective ones of the first and second dielectric patterns and extending in parallel with the select line along the first direction. A first area of overlap of the first word line with the first floating gate pattern and the first dielectric pattern is less than a second area of overlap of the second word line with the second floating gate pattern and the second dielectric pattern. The first word line may be disposed between the select line and the second word line.
摘要翻译：存储器件包括其中限定在其中的有源区域沿着第一方向线性延伸的衬底。该器件还包括在衬底上的选择线，并沿着第二方向延伸以垂直地穿过有源区，有源区上的第一和第二浮动栅极图案并沿着第一方向间隔开，并且在相应的一个上分开的第一和第二电介质图案的第一和第二浮栅图案。该装置还包括在第一和第二电介质图案的相应的第一和第二字线上并沿着第一方向与选择线平行延伸的第一和第二字线。第一字线与第一浮栅图案和第一介电图案的重叠的第一区域小于第二字线与第二浮栅图案和第二介质图案的第二重叠区域。第一字线可以设置在选择线和第二字线之间。

3. 发明申请

US20110303962A1 NON-VOLATILE MEMORY DEVICES WITH NON-UNIFORM FLOATING GATE COUPLING 有权
标题翻译：具有非均匀浮动门耦合的非易失性存储器件
公开(公告)号：US20110303962A1
公开(公告)日：2011-12-15
申请号：US13158990
申请日：2011-06-13
申请人： Joon-Sung Lim , Jong-Ho Park , Ok-Cheon Hong , Ji-Hwan Jeon
发明人： Joon-Sung Lim , Jong-Ho Park , Ok-Cheon Hong , Ji-Hwan Jeon
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/11519
摘要： A memory device includes a substrate having an active region defined therein that extends linearly along a first direction. The device also includes a select line on the substrate and extending along a second direction to perpendicularly cross the active region, first and second floating gate patterns on the active region and spaced apart along the first direction, and first and second dielectric patterns on respective ones of the first and second floating gate patterns. The device further includes first and second word lines on respective ones of the first and second dielectric patterns and extending in parallel with the select line along the first direction. A first area of overlap of the first word line with the first floating gate pattern and the first dielectric pattern is less than a second area of overlap of the second word line with the second floating gate pattern and the second dielectric pattern. The first word line may be disposed between the select line and the second word line.
摘要翻译：存储器件包括其中限定在其中的有源区域沿着第一方向线性延伸的衬底。该器件还包括在衬底上的选择线，并沿着第二方向延伸以垂直地穿过有源区，有源区上的第一和第二浮动栅极图案并沿着第一方向间隔开，并且在相应的一个上分开的第一和第二电介质图案的第一和第二浮栅图案。该装置还包括在第一和第二电介质图案的相应的第一和第二字线上并沿着第一方向与选择线平行延伸的第一和第二字线。第一字线与第一浮栅图案和第一介电图案的重叠的第一区域小于第二字线与第二浮栅图案和第二介质图案的第二重叠区域。第一字线可以设置在选择线和第二字线之间。

4. 发明申请

US20180337193A1 SEMICONDUCTOR DEVICES 审中-公开
公开(公告)号：US20180337193A1
公开(公告)日：2018-11-22
申请号：US16047712
申请日：2018-07-27
申请人： Joon-Sung Lim , Jang-Gn Yun , Jaesun Yun
发明人： Joon-Sung Lim , Jang-Gn Yun , Jaesun Yun
IPC分类号： H01L27/11582 , H01L27/11573 , H01L23/528 , H01L23/522
CPC分类号： H01L27/11582 , H01L23/5226 , H01L23/528 , H01L27/11573 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern. Cell bit line contact plugs are disposed on the cell vertical structures. A bit line is disposed on the cell bit line contact plugs. A peripheral bit line contact structure is disposed between the bit line and the first peripheral interconnection structure. The peripheral bit line contact structure crosses the opening of the semiconductor

5. 发明授权

US09887199B2 Semiconductor devices including a peripheral circuit region and first and second memory regions, and related programming methods 有权
公开(公告)号：US09887199B2
公开(公告)日：2018-02-06
申请号：US14670667
申请日：2015-03-27
申请人： Joon-Sung Lim , Jang-Gn Yun , Hoosung Cho
发明人： Joon-Sung Lim , Jang-Gn Yun , Hoosung Cho
IPC分类号： H01L27/088 , H01L27/105 , H01L27/06 , H01L27/11524 , H01L27/11582 , G11C5/02 , G11C11/56 , G11C16/04 , G11C16/10
CPC分类号： H01L27/105 , G11C5/025 , G11C11/56 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C2211/5641 , H01L27/0688 , H01L27/11524 , H01L27/11582
摘要： Semiconductor devices are provided. A semiconductor device includes a peripheral circuit region and a first memory region that are side by side on a substrate. Moreover, the semiconductor device includes a second memory region that is on the peripheral circuit region and the first memory region. Related methods of programming semiconductor devices are also provided.

6. 发明申请

US20160163635A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20160163635A1
公开(公告)日：2016-06-09
申请号：US14957113
申请日：2015-12-02
申请人： Jang-Gn Yun , Jaesun Yun , Joon-Sung Lim
发明人： Jang-Gn Yun , Jaesun Yun , Joon-Sung Lim
IPC分类号： H01L23/528 , H01L23/00 , H01L23/552 , H01L27/115
CPC分类号： H01L23/528 , H01L23/3192 , H01L23/552 , H01L27/0688 , H01L27/11573 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure. A conductive shielding pattern is disposed between the cell semiconductor pattern and the semiconductor substrate and above the first circuit and the first interconnection structure.
摘要翻译：半导体器件包括设置在半导体衬底上的单元半导体图案。在半导体衬底上设置半导体虚设图案。半导体虚拟图案与单元半导体图案共面。第一电路设置在半导体衬底和单元半导体图案之间。第一互连结构设置在半导体衬底和单元半导体图案之间。第一虚拟结构设置在半导体衬底和单元半导体图案之间。第一虚拟结构的一部分与第一互连结构的一部分共面。与半导体图案不重叠的第二虚拟结构设置在半导体衬底上。第二虚拟结构的一部分与第一互连结构的一部分共面。在电池半导体图案和半导体衬底之间以及第一电路和第一互连结构之上设置导电屏蔽图案。

7. 发明申请

US20130009213A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130009213A1
公开(公告)日：2013-01-10
申请号：US13617044
申请日：2012-09-14
申请人： Joon-Sung Lim , Jongho Park , Okcheon Hong , Jung-Hwan Park
发明人： Joon-Sung Lim , Jongho Park , Okcheon Hong , Jung-Hwan Park
IPC分类号： H01L27/10
CPC分类号： H01L27/11529 , H01L27/11526 , H01L27/11573 , H01L28/20
摘要： Semiconductor devices and a methods of fabricating the semiconductor devices are provided. The semiconductor devices may include a pattern on a substrate. The semiconductor devices may also include a capping dielectric layer on the pattern. The semiconductor devices may further include a first nitride layer on the capping dielectric layer. Moreover, the semiconductor devices may include a second nitride layer on the first nitride layer. A concentration of nitrogen in the first nitride layer may be greater than that in the second nitride layer.
摘要翻译：提供半导体器件和制造半导体器件的方法。半导体器件可以在衬底上包括图案。半导体器件还可以在图案上包括覆盖电介质层。半导体器件还可以包括在覆盖电介质层上的第一氮化物层。此外，半导体器件可以包括在第一氮化物层上的第二氮化物层。第一氮化物层中的氮浓度可以大于第二氮化物层中的浓度。

8. 发明授权

US09761603B2 Methods for fabricating a semiconductor device and semiconductor devices fabricated by the same 有权
公开(公告)号：US09761603B2
公开(公告)日：2017-09-12
申请号：US14964624
申请日：2015-12-10
申请人： Min-Sung Song , Jae-Hwang Sim , Joon-Sung Lim
发明人： Min-Sung Song , Jae-Hwang Sim , Joon-Sung Lim
IPC分类号： H01L21/4763 , H01L27/11573 , H01L21/311 , H01L27/11526 , H01L21/033 , H01L21/768
CPC分类号： H01L27/11573 , H01L21/0337 , H01L21/31144 , H01L21/76816 , H01L27/11526
摘要： The inventive concepts provide methods for fabricating a semiconductor device and semiconductor devices fabricated by the same. According to the method, conductive lines having a fine pitch smaller than the minimum pitch realized by an exposure process may be formed using two or three photolithography processes and two spacer formation processes. In addition, node separation regions of the conductive lines may be easily formed without a misalignment problem.

9. 发明授权

US09741733B2 Three-dimensional semiconductor memory devices 有权
公开(公告)号：US09741733B2
公开(公告)日：2017-08-22
申请号：US14962263
申请日：2015-12-08
申请人： Joon-Sung Lim , Jang-Gn Yun , Jaesun Yun
发明人： Joon-Sung Lim , Jang-Gn Yun , Jaesun Yun
IPC分类号： H01L27/115 , H01L27/11582 , H01L23/522 , H01L23/528 , H01L27/11573
CPC分类号： H01L27/11582 , H01L23/5226 , H01L23/528 , H01L27/11573 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The semiconductor devices may include a semiconductor pattern including an opening on a semiconductor substrate. A peripheral transistor and a peripheral interconnection structure may be disposed between the semiconductor substrate and the semiconductor pattern. The peripheral interconnection structure may be electrically connected to the peripheral transistor. Cell gate conductive patterns may be disposed on the semiconductor pattern. The cell vertical structures may extend through the cell gate conductive patterns and may be connected to the semiconductor pattern. Cell bit line contact plugs may be disposed on the cell vertical structures. A bit line may be disposed on the cell bit line contact plugs. A peripheral bit line contact structure may be disposed between the bit line and the peripheral interconnection structure. The peripheral bit line contact structure may extend through the opening of the semiconductor.

10. 发明授权

US08288228B2 Semiconductor devices and methods of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08288228B2
公开(公告)日：2012-10-16
申请号：US13032286
申请日：2011-02-22
申请人： Joon-Sung Lim , Jongho Park , Okcheon Hong , Jung-Hwan Park
发明人： Joon-Sung Lim , Jongho Park , Okcheon Hong , Jung-Hwan Park
IPC分类号： H01L21/8247
CPC分类号： H01L27/11529 , H01L27/11526 , H01L27/11573 , H01L28/20
摘要： Semiconductor devices and a methods of fabricating the semiconductor devices are provided. The methods may include forming a pattern on a substrate, forming a capping dielectric layer on the pattern, and thermally processing the substrate. After thermally processing the substrate, the methods may further include forming a diffusion barrier layer by a nitride process that may include supplying nitrogen to the capping dielectric layer. The methods may also include forming an etching stop layer on the diffusion barrier layer, forming an inter-layer dielectric layer on the etching stop layer, and planarizing the inter-layer dielectric layer.
摘要翻译：提供半导体器件和制造半导体器件的方法。所述方法可以包括在衬底上形成图案，在图案上形成覆盖电介质层，并热处理衬底。在热处理衬底之后，所述方法还可以包括通过氮化工艺形成扩散阻挡层，所述氮化工艺可以包括向覆盖电介质层供应氮。所述方法还可以包括在扩散阻挡层上形成蚀刻停止层，在蚀刻停止层上形成层间电介质层，并平坦化层间电介质层。

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