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1. 发明授权

US06545875B1 Multiple channel modules and bus systems using same 失效
公开(公告)号：US06545875B1
公开(公告)日：2003-04-08
申请号：US09568424
申请日：2000-05-10
申请人： Donald V. Perino , Belgacem Haba , Sayeh Khalili
发明人： Donald V. Perino , Belgacem Haba , Sayeh Khalili
IPC分类号： H05K702
CPC分类号： G11C5/04 , G06F13/409 , G11C5/00 , H05K1/023 , H05K1/117 , H05K1/141 , H05K1/147 , H05K1/148 , H05K7/1459 , H05K2201/10189
摘要： Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.

2. 发明授权

US06376904B1 Redistributed bond pads in stacked integrated circuit die package 有权
标题翻译：堆叠式集成电路芯片封装中的再分配焊盘
公开(公告)号：US06376904B1
公开(公告)日：2002-04-23
申请号：US09685941
申请日：2000-10-10
申请人： Belgacem Haba , Donald V. Perino , Sayeh Khalili
发明人： Belgacem Haba , Donald V. Perino , Sayeh Khalili
IPC分类号： H01L2334
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/5385 , H01L24/48 , H01L24/49 , H01L24/50 , H01L24/73 , H01L25/0652 , H01L2224/05553 , H01L2224/05599 , H01L2224/32145 , H01L2224/32225 , H01L2224/4809 , H01L2224/48091 , H01L2224/48095 , H01L2224/48145 , H01L2224/48227 , H01L2224/484 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L2224/85447 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06558 , H01L2225/06562 , H01L2225/06575 , H01L2225/06579 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01083 , H01L2924/014 , H01L2924/10161 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19104 , H01L2924/30107 , H01L2924/3011 , H01L2924/00012 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor module having a first integrated circuit die having a planar surface. The first integrated circuit die has a first conductive pad disposed substantially on the planar surface and a redistributed conductive pad electrically connected to the first conductive pad. The redistributed conductive pad is disposed near a periphery of the planar surface. The semiconductor module has a second integrated circuit die stacked adjacent to the planar surface and offset from the periphery, such that a second conductive pad on the second integrated circuit die can be electrically connected to the redistributed conductive pad.
摘要翻译：一种半导体模块，具有具有平坦表面的第一集成电路管芯。第一集成电路管芯具有基本上设置在平面表面上的第一导电焊盘和电连接到第一导电焊盘的再分布导电焊盘。再分布的导电焊盘设置在平面的周边附近。半导体模块具有与平面相邻并且与周边偏移堆叠的第二集成电路管芯，使得第二集成电路管芯上的第二导电焊盘可以电连接到再分布的导电焊盘。

3. 发明授权

US06657871B2 Multiple channel modules and bus systems using same 失效
标题翻译：多通道模块和使用相同的总线系统
公开(公告)号：US06657871B2
公开(公告)日：2003-12-02
申请号：US10177747
申请日：2002-06-20
申请人： Donald V. Perino , Belgacem Haba , Sayeh Khalili
发明人： Donald V. Perino , Belgacem Haba , Sayeh Khalili
IPC分类号： H05K710
CPC分类号： G11C5/04 , G06F13/409 , G11C5/00 , H05K1/023 , H05K1/117 , H05K1/141 , H05K1/147 , H05K1/148 , H05K7/1459 , H05K2201/10189
摘要： Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
摘要翻译：公开了可用于实现具有1至N个信道的模块的各种模块结构。总线系统可以通过这种模块的互连形成。

4. 发明授权

US06514794B2 Redistributed bond pads in stacked integrated circuit die package 有权
公开(公告)号：US06514794B2
公开(公告)日：2003-02-04
申请号：US10072412
申请日：2002-02-05
申请人： Belgacem Haba , Donald V. Perino , Sayeh Khalili
发明人： Belgacem Haba , Donald V. Perino , Sayeh Khalili
IPC分类号： H01L2144
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/5385 , H01L24/48 , H01L24/49 , H01L24/50 , H01L24/73 , H01L25/0652 , H01L2224/05553 , H01L2224/05599 , H01L2224/32145 , H01L2224/32225 , H01L2224/4809 , H01L2224/48091 , H01L2224/48095 , H01L2224/48145 , H01L2224/48227 , H01L2224/484 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L2224/85447 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06558 , H01L2225/06562 , H01L2225/06575 , H01L2225/06579 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01083 , H01L2924/014 , H01L2924/10161 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19104 , H01L2924/30107 , H01L2924/3011 , H01L2924/00012 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor module having a first integrated circuit die having a planar surface. The first integrated circuit die has a first conductive pad disposed substantially on the planar surface and a redistributed conductive pad electrically connected to the first conductive pad. The redistributed conductive pad is disposed near a periphery of the planar surface. The semiconductor module has a second integrated circuit die stacked adjacent to the planar surface and offset from the periphery, such that a second conductive pad on the second integrated circuit die can be electrically connected to the redistributed conductive pad.

5. 发明授权

US06621155B1 Integrated circuit device having stacked dies and impedance balanced transmission lines 有权
标题翻译：具有堆叠管芯和阻抗平衡传输线的集成电路器件
公开(公告)号：US06621155B1
公开(公告)日：2003-09-16
申请号：US09471304
申请日：1999-12-23
申请人： Donald V. Perino , Sayeh Khalili
发明人： Donald V. Perino , Sayeh Khalili
IPC分类号： H01L2334
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/5385 , H01L24/48 , H01L24/49 , H01L24/50 , H01L25/0652 , H01L2224/0401 , H01L2224/05599 , H01L2224/32145 , H01L2224/4809 , H01L2224/48091 , H01L2224/48095 , H01L2224/48145 , H01L2224/48227 , H01L2224/484 , H01L2224/49175 , H01L2224/73265 , H01L2224/85399 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01083 , H01L2924/014 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19104 , H01L2924/30107 , H01L2924/3011 , H01L2224/45099 , H01L2924/00012
摘要： A multi-chip device which includes a plurality of integrated circuit die disposed one over another. Each integrated circuit die includes one or a plurality of bond pads. One or a plurality of conductors are disposed to electrically couple the bond pads of vertically adjacent integrated circuit die. Each conductor is designed, calculated, specified and/or predetermined to have a length so as to behave as a segment in a multi-drop transmission line. The multi-drop transmission line may be terminated at one end or utilized in a flow-through approach. In one embodiment, an integrated circuit die may be horizontally offset with respect to a vertically adjacent integrated circuit die to expose the periphery region. In another embodiment, each integrated circuit die may be stacked and aligned in a vertical column. In this embodiment, a spacer such as a thermally conductive spacer is disposed between each integrated circuit die in the stack. In yet another embodiment, two or more stacks of integrated circuit die are disposed in the multi-chip device and the one or more multi-drop transmission lines may be implemented in the flow-through approach. The plurality of integrated circuit die may comprise a plurality of memory devices, or a plurality of memory devices and a controller, or a plurality of controllers and a plurality of memory devices.
摘要翻译：一种多芯片器件，包括多个集成电路管芯，所述多个集成电路管芯设置在另一个上。每个集成电路管芯包括一个或多个接合焊盘。设置一个或多个导体以电耦合垂直相邻的集成电路管芯的接合焊盘。每个导体被设计，计算，指定和/或预定为具有一个长度以便在多点传输线路中作为一个段。多滴传输线可以在一端终止或以流通方式使用。在一个实施例中，集成电路管芯可以相对于垂直相邻的集成电路管芯水平地偏移以暴露外围区域。在另一个实施例中，每个集成电路管芯可以堆叠并在垂直列中对准。在该实施例中，诸如导热间隔件之类的间隔件设置在堆叠中的每个集成电路管芯之间。在另一个实施例中，集成电路管芯的两个或多个堆叠设置在多芯片器件中，并且可以以流通方式实现一个或多个多点传输线。多个集成电路管芯可以包括多个存储器件，或多个存储器件和控制器，或多个控制器和多个存储器件。

6. 再颁专利

USRE43720E1 Integrated circuit device having stacked dies and impedance balanced transmission lines 有权
标题翻译：具有堆叠管芯和阻抗平衡传输线的集成电路器件
公开(公告)号：USRE43720E1
公开(公告)日：2012-10-09
申请号：US11229445
申请日：2005-09-15
申请人： Donald V. Perino , Sayeh Khalili
发明人： Donald V. Perino , Sayeh Khalili
IPC分类号： H01L23/34 , H01L23/48 , H01L23/02 , H05K7/00
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/5385 , H01L24/48 , H01L24/49 , H01L24/50 , H01L25/0652 , H01L2224/0401 , H01L2224/05599 , H01L2224/32145 , H01L2224/4809 , H01L2224/48091 , H01L2224/48095 , H01L2224/48145 , H01L2224/48227 , H01L2224/484 , H01L2224/49175 , H01L2224/73265 , H01L2224/85399 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01083 , H01L2924/014 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19104 , H01L2924/30107 , H01L2924/3011 , H01L2224/45099 , H01L2924/00012
摘要： A multi-chip device which includes a plurality of integrated circuit die disposed one over another. Each integrated circuit die includes one or a plurality of bond pads. One or a plurality of conductors are disposed to electrically couple the bond pads of vertically adjacent integrated circuit die. Each conductor is designed, calculated, specified and/or predetermined to have a length so as to behave as a segment in a multi-drop transmission line. The multi-drop transmission line may be terminated at one end or utilized in a flow-through approach. In one embodiment, an integrated circuit die may be horizontally offset with respect to a vertically adjacent integrated circuit die to expose the periphery region. In another embodiment, each integrated circuit die may be stacked and aligned in a vertical column. In this embodiment, a spacer such as a thermally conductive spacer is disposed between each integrated circuit die in the stack. In yet another embodiment, two or more stacks of integrated circuit die are disposed in the multi-chip device and the one or more multi-drop transmission lines may be implemented in the flow-through approach. The plurality of integrated circuit die may comprise a plurality of memory devices, or a plurality of memory devices and a controller, or a plurality of controllers and a plurality of memory devices.
摘要翻译：一种多芯片器件，包括多个集成电路管芯，所述多个集成电路管芯设置在另一个上。每个集成电路管芯包括一个或多个接合焊盘。设置一个或多个导体以电耦合垂直相邻的集成电路管芯的接合焊盘。每个导体被设计，计算，指定和/或预定为具有一个长度以便在多点传输线路中作为一个段。多滴传输线可以在一端终止或以流通方式使用。在一个实施例中，集成电路管芯可以相对于垂直相邻的集成电路管芯水平地偏移以暴露外围区域。在另一个实施例中，每个集成电路管芯可以堆叠并在垂直列中对准。在该实施例中，诸如导热间隔件之类的间隔件设置在堆叠中的每个集成电路管芯之间。在另一个实施例中，集成电路管芯的两个或多个堆叠设置在多芯片器件中，并且可以以流通方式实现一个或多个多点传输线。多个集成电路管芯可以包括多个存储器件，或多个存储器件和控制器，或多个控制器和多个存储器件。

7. 发明授权

US07130944B2 Chip-to-chip communication system using an ac-coupled bus and devices employed in same 失效
公开(公告)号：US07130944B2
公开(公告)日：2006-10-31
申请号：US11021207
申请日：2004-12-23
申请人： Donald V. Perino , Haw-Jyh Liaw , Alfredo Moncayo , Kevin Donnelly , Richard M. Barth , Bruno W. Garlepp
发明人： Donald V. Perino , Haw-Jyh Liaw , Alfredo Moncayo , Kevin Donnelly , Richard M. Barth , Bruno W. Garlepp
IPC分类号： G06F13/00
CPC分类号： H01L23/48 , G06F13/423 , H01L2224/48091 , H01L2224/48247 , H01L2924/12032 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： A chip-to-chip communication system and interface technique. A master and at least two devices are interconnected with a signal line of a high speed bus. A capacitive coupling element, for example a diode, is employed to capacitively couple the interface of the device to the signal line. By employing the capacitive coupling element, along with a suitable signaling technique which supports capacitive information transfer, high speed rates of information transfer between the master and device over the signal line are achieved.

8. 发明授权

US06687780B1 Expandable slave device system 失效
标题翻译：可扩展的从设备系统
公开(公告)号：US06687780B1
公开(公告)日：2004-02-03
申请号：US09706238
申请日：2000-11-02
申请人： Bruno W. Garlepp , Richard M. Barth , Kevin S. Donnelly , Ely K. Tsern , Craig E. Hampel , Jeffrey D. Mitchell , James A. Gasbarro , Billy W. Garrett, Jr. , Fredrick A. Ware , Donald V. Perino
发明人： Bruno W. Garlepp , Richard M. Barth , Kevin S. Donnelly , Ely K. Tsern , Craig E. Hampel , Jeffrey D. Mitchell , James A. Gasbarro , Billy W. Garrett, Jr. , Fredrick A. Ware , Donald V. Perino
IPC分类号： G06F1340
CPC分类号： G06F13/4072 , G06F13/4086 , G06F13/4243
摘要： A bus system for use with addressable memory has a global bus of uni-directional signal lines. The global bus has a first end and a second end. A master device transmits data to and receives data from the global bus. First and second global bus terminators are coupled to the first and second ends of the global bus, respectively. One or more subsystems are connected in parallel to each other and to the master device via the global bus. Each subsystem includes a local bus, one or more slave devices coupled to the local bus, a write buffer that receives incoming signals from the master device via the global bus and transmits the incoming signals to the one or more slave devices via the local bus, and a read buffer that receives outgoing signals from the one or more slave devices via the local bus and transmits the outgoing signals to the master device via the global bus.
摘要翻译：与可寻址存储器一起使用的总线系统具有单向信号线的全局总线。全球总线有一个第一端和一端。主设备向全局总线发送数据并从全局总线接收数据。第一和第二全局总线终端分别耦合到全局总线的第一和第二端。一个或多个子系统通过全局总线彼此并联连接到主设备。每个子系统包括本地总线，耦合到本地总线的一个或多个从设备，经由全局总线接收来自主设备的输入信号的写入缓冲器，并且经由本地总线将输入信号发送到一个或多个从设备，以及读取缓冲器，其经由本地总线从一个或多个从设备接收输出信号，并经由全局总线将输出信号发送到主设备。

9. 发明授权

US06530062B1 Active impedance compensation 失效
标题翻译：有源阻抗补偿
公开(公告)号：US06530062B1
公开(公告)日：2003-03-04
申请号：US09523520
申请日：2000-03-10
申请人： Haw-Jyh Liaw , Donald V. Perino , Pak Shing Chau , Kevin S. Donnelly
发明人： Haw-Jyh Liaw , Donald V. Perino , Pak Shing Chau , Kevin S. Donnelly
IPC分类号： G06F1750
CPC分类号： G06F13/4086
摘要： Active impedance compensation is accomplished in a bus system by means of a variable capacitor element associated with a connection circuit between system slave devices and an impedance balanced channel. The variable capacitor elements may be programmed using a control value determined by actively exercising the channel with a telemetry signal and evaluating the resulting signal reflections which are indicative of the impedance discontinuities on the channel.
摘要翻译：有源阻抗补偿通过与系统从设备之间的连接电路和阻抗平衡通道相关联的可变电容器元件在总线系统中完成。可变电容器元件可以使用通过用遥测信号主动地运行通道所确定的控制值进行编程，并且评估指示通道上的阻抗不连续性的结果信号反射。

10. 发明授权

US06359931B1 Apparatus and method for multilevel signaling 失效
标题翻译：多电平信号的装置和方法
公开(公告)号：US06359931B1
公开(公告)日：2002-03-19
申请号：US09418790
申请日：1999-10-15
申请人： Donald V. Perino , John B. Dillon
发明人： Donald V. Perino , John B. Dillon
IPC分类号： H04B300
CPC分类号： H04L25/0272 , H04L5/20 , H04L25/028 , H04L25/0292
摘要： A system for transmitting information from a source to a destination using multilevel signaling. Multiple conductors are coupled between the transmission source and the transmission destination. Multiple drivers are coupled to the conductors at the transmission source. Each driver is coupled to a pair of conductors. Multiple comparators are coupled to the conductors at the transmission destination. Each comparator is coupled to a pair of conductors. The information is encoded into a sequence of symbols in which each symbol represents a unique permutation of signal levels on the conductors. Each signal level is used at least once for each symbol. All signal levels associated with a particular symbol are transmitted over the conductors simultaneously.
摘要翻译：用于使用多电平信令从源向目的地发送信息的系统。多个导体耦合在传输源和传输目的地之间。多个驱动器耦合到传输源上的导体。每个驱动器耦合到一对导体。多个比较器耦合到传输目的地的导体。每个比较器耦合到一对导体。信息被编码成符号序列，其中每个符号表示导体上的信号电平的唯一置换。对于每个符号，每个信号电平至少使用一次。与特定符号相关联的所有信号电平同时在导体上传输。

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