专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06589059B2 Chip socket assembly and chip file assembly for semiconductor chips 失效
公开(公告)号：US06589059B2
公开(公告)日：2003-07-08
申请号：US09957822
申请日：2001-09-20
申请人： Donald V. Perino , Wayne S. Richardson , John B. Dillon
发明人： Donald V. Perino , Wayne S. Richardson , John B. Dillon
IPC分类号： H01R1200
CPC分类号： H05K7/1431 , H01R12/7005 , H05K3/325
摘要： A chip socket assembly provides for the mechanical and electrical coupling of edge-mountable chips to a bus of a circuit board with relative ease. An edge-mountable chip may be placed in a slot defined by a base. A clip may be attached to the base to retain the chip in the base. Alternatively, the base and the package of the chip may be configured such that the chip mates with the base in retaining the chip in the base. With the chip socket assembly, users may add, remove, or replace single chips and therefore expand the functionality of a system with the granularity of a single chip in a relatively easy manner. A chip file assembly may also be used to provide for the mechanical and electrical coupling of a plurality of edge-mountable chips to a bus of a circuit board with relative ease. Assemblies for securing horizontal chip packages are also described.

2. 发明授权

US06234820B1 Method and apparatus for joining printed circuit boards 失效
标题翻译：用于连接印刷电路板的方法和装置
公开(公告)号：US06234820B1
公开(公告)日：2001-05-22
申请号：US08898141
申请日：1997-07-21
申请人： Donald V. Perino , John B. Dillon
发明人： Donald V. Perino , John B. Dillon
IPC分类号： H01R1300
CPC分类号： H01R12/725 , H01R12/7005 , H01R13/2414
摘要： A method and apparatus for joining printed circuit boards is provided. A socket is attached to a mother board. A connector is attached to a daughter board. The traces on the daughter board are connected to signal leads, which are wrapped around an elastomer. The socket and the connector are engaged, such that the mother board is coupled to a daughter board, and the traces on the mother board are coupled to the signal leads of the daughter board.
摘要翻译：提供一种用于连接印刷电路板的方法和装置。插座连接到母板上。连接器连接到子板。子板上的迹线连接到信号引线，信号引线缠绕在弹性体上。插座和连接器接合，使得母板耦合到子板，并且母板上的迹线耦合到子板的信号引线。

3. 发明授权

US6007357A Chip socket assembly and chip file assembly for semiconductor chips 失效
公开(公告)号：US6007357A
公开(公告)日：1999-12-28
申请号：US887567
申请日：1997-07-03
申请人： Donald V. Perino , Wayne S. Richardson , John B. Dillon
发明人： Donald V. Perino , Wayne S. Richardson , John B. Dillon
IPC分类号： G11C5/00 , H01L23/32 , H01R12/70 , H01R33/76 , H05K3/32 , H05K7/14 , H01R9/09
CPC分类号： H05K7/1431 , H01R12/7005 , H05K3/325
摘要： A chip socket assembly provides for the mechanical and electrical coupling of edge-mountable chips to a bus of a circuit board with relative ease. An edge-mountable chip may be placed in a slot defined by a base. A clip may be attached to the base to retain the chip in the base. Alternatively, the base and the package of the chip may be configured such that the chip mates with the base in retaining the chip in the base. With the chip socket assembly, users may add, remove, or replace single chips and therefore expand the functionality of a system with the granularity of a single chip in a relatively easy manner. A chip file assembly may also be used to provide for the mechanical and electrical coupling of a plurality of edge-mountable chips to a bus of a circuit board with relative ease. Assemblies for securing horizontal chip packages are also described.

4. 发明授权

US6005895A Apparatus and method for multilevel signaling 失效
公开(公告)号：US6005895A
公开(公告)日：1999-12-21
申请号：US772175
申请日：1996-12-20
申请人： Donald V. Perino , John B. Dillon
发明人： Donald V. Perino , John B. Dillon
IPC分类号： H04L5/20 , H04L25/02 , H04L25/34 , H04L25/49
CPC分类号： H04L25/0272 , H04L25/028 , H04L5/20 , H04L25/0292
摘要： A system for transmitting information from a source to a destination using multilevel signaling. Multiple conductors are coupled between the transmission source and the transmission destination. Multiple drivers are coupled to the conductors at the transmission source. Each driver is coupled to a pair of conductors. Multiple comparators are coupled to the conductors at the transmission destination. Each comparator is coupled to a pair of conductors. The information is encoded into a sequence of symbols in which each symbol represents a unique permutation of signal levels on the conductors. Each signal level is used at least once for each symbol. All signal levels associated with a particular symbol are transmitted over the conductors simultaneously.

5. 发明授权

US5680361A Method and apparatus for writing to memory components 失效
标题翻译：用于写入存储器组件的方法和装置
公开(公告)号：US5680361A
公开(公告)日：1997-10-21
申请号：US389561
申请日：1995-02-14
申请人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy Wayne Garrett, Jr. , John Girdner Atwood, Jr. , Michael P. Farmwald , Richard DeWitt Crisp
发明人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy Wayne Garrett, Jr. , John Girdner Atwood, Jr. , Michael P. Farmwald , Richard DeWitt Crisp
IPC分类号： G11C7/10 , G11C11/401
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/103 , G11C7/1045 , G11C7/1078 , G11C7/1087
摘要： Additional modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access. In order to enhance the functionality of a system, such as a two-dimensional graphics system, in an alternate embodiment, the memory system is provided with two registers and a select control line to select data from one of two registers. In a computer graphics system, this is used to select between foreground and background colors. The embodiment can be utilized in conjunction with the other embodiments described to provide enhanced functionality and performance.
摘要翻译：提供附加模式以增强存储器系统的功能和性能。在一个实施例中，向每个列访问中使用的写入数据提供唯一的位掩码。在替代实施例中，提供位掩码寄存器和字节掩码寄存器以支持位电平和字节电平掩蔽。位掩码和写数据寄存器被实现为单个寄存器，以提供功能，同时最小化组件空间和成本。在另一个实施例中，提供单独的位掩码和字节掩码。字节掩码在一个周期内加载掩码数据，并在下一个“q”列写入访问期间使用。该结构提供无位掩蔽的操作模式，每行访问提供位掩码，并提供每列访问的位掩码。为了增强诸如二维图形系统的系统的功能，在替代实施例中，存储器系统具有两个寄存器和选择控制线，以从两个寄存器之一中选择数据。在计算机图形系统中，用于在前景和背景颜色之间进行选择。该实施例可以与所描述的其他实施例一起使用以提供增强的功能和性能。

6. 发明授权

US5430676A Dynamic random access memory system 失效
公开(公告)号：US5430676A
公开(公告)日：1995-07-04
申请号：US202290
申请日：1994-02-25
申请人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy W. Garrett, Jr. , John G. Atwood, Jr. , Michael P. Farmwald
发明人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy W. Garrett, Jr. , John G. Atwood, Jr. , Michael P. Farmwald
IPC分类号： G06F13/16 , G11C5/06 , G11C11/401 , G06F12/00
CPC分类号： G11C5/066
摘要： As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to the DRAM in order to take advantage of the high performance of the signal lines in the interface. In the DRAM memory system of the present invention, the address and control lines and are combined and the information multiplexed such that the DRAM pins have roughly equal information rate at all times.

7. 发明授权

US5337285A Method and apparatus for power control in devices 失效
标题翻译：设备功率控制的方法和装置
公开(公告)号：US5337285A
公开(公告)日：1994-08-09
申请号：US65804
申请日：1993-05-21
申请人： Frederick A. Ware , James A. Gasbarro , John B. Dillon , Matthew M. Griffin , Richard M. Barth , Mark A. Horowitz
发明人： Frederick A. Ware , James A. Gasbarro , John B. Dillon , Matthew M. Griffin , Richard M. Barth , Mark A. Horowitz
IPC分类号： G06F1/32 , G11C5/14 , H03K19/00 , H03K19/0175 , G11C7/00
CPC分类号： G11C5/14
摘要： A power control circuit to minimize power consumption of CMOS circuits by disabling/enabling the clock input to the CMOS circuit. A phase locked loop (PLL) or delay locked loop (DLL) drives a capacitive load of the component and a dummy load comparable to the component load. A standby latch is provided to control the clock input to the component. In a standby state, the clock signal is not provided to the component but the PLL/DLL continues to operate, driving the dummy load. Thus, when it is desirable to power on the circuit, the standby latch is reset and the clock signal is provided to the component, thereby turning on the component with little latency.
摘要翻译：电源控制电路，通过禁止/使能CMOS电路的时钟输入来最小化CMOS电路的功耗。锁相环（PLL）或延迟锁定环（DLL）驱动组件的容性负载和与组件负载相当的虚拟负载。提供备用锁存器来控制对组件的时钟输入。在待机状态下，时钟信号不提供给组件，但PLL / DLL继续运行，驱动虚拟负载。因此，当期望对电路通电时，备用锁存器被复位，并且时钟信号被提供给部件，从而以很小的延迟打开部件。

8. 发明授权

US4920481A Emulation with display update trapping 失效
标题翻译：仿真显示更新陷阱
公开(公告)号：US4920481A
公开(公告)日：1990-04-24
申请号：US130369
申请日：1987-12-08
申请人： Joseph H. Binkley , Perry A. Caro , John B. Dillon , Charles R. Fay , Jonathan Gibbons , Hilary N. Hooks , Abdo G. Kadifa , Jeffery W. Lee , William C. Lynch , Clayton W. Mock , Everett T. Neely , Michael L. Tallan , Geoffrey O. Thompson , Gaya Vukkadala , John D. Wick , Donald R. Woods
发明人： Joseph H. Binkley , Perry A. Caro , John B. Dillon , Charles R. Fay , Jonathan Gibbons , Hilary N. Hooks , Abdo G. Kadifa , Jeffery W. Lee , William C. Lynch , Clayton W. Mock , Everett T. Neely , Michael L. Tallan , Geoffrey O. Thompson , Gaya Vukkadala , John D. Wick , Donald R. Woods
IPC分类号： G06F13/10
CPC分类号： G06F13/105
摘要： An emulating data processor includes a host system and an emulating processor with outputs to and inputs from the host system. The emulating processor executes sequences of instructions executable by a PC being emulated, but a host processor independently executes sequences of its instructions which are different from PC instructions. Circuitry monitors the emulating processor outputs and provides information to the host system so that it can emulate the environment of the PC CPU, emulating both memory and I/O devices. The memory accesses of the emulating processor are mapped into the host system memory, so that the host processor is protected from defective PC software on the emulating processor. The display updates of the emulating processor are detected and provide information for the host processor in updating a part of its display which provides the information a PC display would provide simultaneously with the display characteristic of the host system. An input/output processor handles I/O operation requests of the emulating processor, using the host system I/O devices to emulate some of the PC I/O devices. The host system emulates the environment of the emulating processor while emulating the user interface of the PC.
摘要翻译：仿真数据处理器包括主机系统和具有到主机系统的输入和输入的仿真处理器。仿真处理器执行可被正在仿真的PC执行的指令序列，但是主机处理器独立地执行与PC指令不同的其指令序列。电路监视仿真处理器输出并向主机系统提供信息，以便它可以模拟PC CPU的环境，同时模拟存储器和I / O设备。仿真处理器的存储器访问被映射到主机系统存储器中，从而保护主机处理器免受仿真处理器上的有缺陷的PC软件的影响。检测仿真处理器的显示更新，并提供主机处理器更新其显示部分的信息，其提供PC显示器将与主机系统的显示特性同时提供的信息。输入/输出处理器处理模拟处理器的I / O操作请求，使用主机系统I / O设备来模拟一些PC I / O设备。主机系统模拟仿真处理器的环境，同时模拟PC的用户界面。

9. 发明授权

US06643752B1 Transceiver with latency alignment circuitry 有权
标题翻译：具有延迟对准电路的收发器
公开(公告)号：US06643752B1
公开(公告)日：2003-11-04
申请号：US09458582
申请日：1999-12-09
申请人： Kevin Donnelly , Mark Johnson , Chanh Tran , John B. Dillon
发明人： Kevin Donnelly , Mark Johnson , Chanh Tran , John B. Dillon
IPC分类号： G06F1200
CPC分类号： G06F13/405 , G06F13/4022 , G06F13/4243
摘要： A transceiver system is described. A secondary memory module is coupled to a primary channel for receiving data and signals from a controller. The secondary memory module comprises a memory and a secondary channel for transmitting the data and control signals to the memory. The secondary memory module further comprises a transceiver coupled to the primary channel and the secondary channel. The transceiver is designed to electrically isolate the secondary channel from the primary channel. The transceiver is a low latency repeater to permit the data and the control signals from the controller to reach the memory, such that a latency of a data request from the controller is independent of a distance of the transceiver from the controller.
摘要翻译：描述收发器系统。次存储器模块耦合到主信道，用于从控制器接收数据和信号。辅助存储器模块包括用于将数据和控制信号发送到存储器的存储器和辅助通道。次存储器模块还包括耦合到主信道和次信道的收发器。收发器被设计为将次级通道与主通道电隔离。收发器是一个低延迟中继器，允许来自控制器的数据和控制信号到达存储器，使得来自控制器的数据请求的等待时间与收发器与控制器的距离无关。

10. 发明授权

US06352435B1 Chip socket assembly and chip file assembly for semiconductor chips 失效
公开(公告)号：US06352435B1
公开(公告)日：2002-03-05
申请号：US09468247
申请日：1999-12-20
申请人： Donald V. Perino , Wayne S. Richardson , John B. Dillon
发明人： Donald V. Perino , Wayne S. Richardson , John B. Dillon
IPC分类号： H01R1362
CPC分类号： H05K7/1431 , H01R12/7005 , H05K3/325
摘要： A chip socket assembly provides for the mechanical and electrical coupling of edge-mountable chips to a bus of a circuit board with relative ease. An edge-mountable chip may be placed in a slot defined by a base. A clip may be attached to the base to retain the chip in the base. Alternatively, the base and the package of the chip may be configured such that the chip mates with the base in retaining the chip in the base. With the chip socket assembly, users may add, remove, or replace single chips and therefore expand the functionality of a system with the granularity of a single chip in a relatively easy manner. A chip file assembly may also be used to provide for the mechanical and electrical coupling of a plurality of edge-mountable chips to a bus of a circuit board with relative ease. Assemblies for securing horizontal chip packages are also described.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式