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1. 发明授权

US06657871B2 Multiple channel modules and bus systems using same 失效
标题翻译：多通道模块和使用相同的总线系统
公开(公告)号：US06657871B2
公开(公告)日：2003-12-02
申请号：US10177747
申请日：2002-06-20
申请人： Donald V. Perino , Belgacem Haba , Sayeh Khalili
发明人： Donald V. Perino , Belgacem Haba , Sayeh Khalili
IPC分类号： H05K710
CPC分类号： G11C5/04 , G06F13/409 , G11C5/00 , H05K1/023 , H05K1/117 , H05K1/141 , H05K1/147 , H05K1/148 , H05K7/1459 , H05K2201/10189
摘要： Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
摘要翻译：公开了可用于实现具有1至N个信道的模块的各种模块结构。总线系统可以通过这种模块的互连形成。

2. 发明授权

US06545875B1 Multiple channel modules and bus systems using same 失效
公开(公告)号：US06545875B1
公开(公告)日：2003-04-08
申请号：US09568424
申请日：2000-05-10
申请人： Donald V. Perino , Belgacem Haba , Sayeh Khalili
发明人： Donald V. Perino , Belgacem Haba , Sayeh Khalili
IPC分类号： H05K702
CPC分类号： G11C5/04 , G06F13/409 , G11C5/00 , H05K1/023 , H05K1/117 , H05K1/141 , H05K1/147 , H05K1/148 , H05K7/1459 , H05K2201/10189
摘要： Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.

3. 发明授权

US06376904B1 Redistributed bond pads in stacked integrated circuit die package 有权
标题翻译：堆叠式集成电路芯片封装中的再分配焊盘
公开(公告)号：US06376904B1
公开(公告)日：2002-04-23
申请号：US09685941
申请日：2000-10-10
申请人： Belgacem Haba , Donald V. Perino , Sayeh Khalili
发明人： Belgacem Haba , Donald V. Perino , Sayeh Khalili
IPC分类号： H01L2334
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/5385 , H01L24/48 , H01L24/49 , H01L24/50 , H01L24/73 , H01L25/0652 , H01L2224/05553 , H01L2224/05599 , H01L2224/32145 , H01L2224/32225 , H01L2224/4809 , H01L2224/48091 , H01L2224/48095 , H01L2224/48145 , H01L2224/48227 , H01L2224/484 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L2224/85447 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06558 , H01L2225/06562 , H01L2225/06575 , H01L2225/06579 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01083 , H01L2924/014 , H01L2924/10161 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19104 , H01L2924/30107 , H01L2924/3011 , H01L2924/00012 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor module having a first integrated circuit die having a planar surface. The first integrated circuit die has a first conductive pad disposed substantially on the planar surface and a redistributed conductive pad electrically connected to the first conductive pad. The redistributed conductive pad is disposed near a periphery of the planar surface. The semiconductor module has a second integrated circuit die stacked adjacent to the planar surface and offset from the periphery, such that a second conductive pad on the second integrated circuit die can be electrically connected to the redistributed conductive pad.
摘要翻译：一种半导体模块，具有具有平坦表面的第一集成电路管芯。第一集成电路管芯具有基本上设置在平面表面上的第一导电焊盘和电连接到第一导电焊盘的再分布导电焊盘。再分布的导电焊盘设置在平面的周边附近。半导体模块具有与平面相邻并且与周边偏移堆叠的第二集成电路管芯，使得第二集成电路管芯上的第二导电焊盘可以电连接到再分布的导电焊盘。

4. 发明授权

US06514794B2 Redistributed bond pads in stacked integrated circuit die package 有权
公开(公告)号：US06514794B2
公开(公告)日：2003-02-04
申请号：US10072412
申请日：2002-02-05
申请人： Belgacem Haba , Donald V. Perino , Sayeh Khalili
发明人： Belgacem Haba , Donald V. Perino , Sayeh Khalili
IPC分类号： H01L2144
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/5385 , H01L24/48 , H01L24/49 , H01L24/50 , H01L24/73 , H01L25/0652 , H01L2224/05553 , H01L2224/05599 , H01L2224/32145 , H01L2224/32225 , H01L2224/4809 , H01L2224/48091 , H01L2224/48095 , H01L2224/48145 , H01L2224/48227 , H01L2224/484 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L2224/85447 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06558 , H01L2225/06562 , H01L2225/06575 , H01L2225/06579 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01083 , H01L2924/014 , H01L2924/10161 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19104 , H01L2924/30107 , H01L2924/3011 , H01L2924/00012 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor module having a first integrated circuit die having a planar surface. The first integrated circuit die has a first conductive pad disposed substantially on the planar surface and a redistributed conductive pad electrically connected to the first conductive pad. The redistributed conductive pad is disposed near a periphery of the planar surface. The semiconductor module has a second integrated circuit die stacked adjacent to the planar surface and offset from the periphery, such that a second conductive pad on the second integrated circuit die can be electrically connected to the redistributed conductive pad.

5. 再颁专利

USRE43720E1 Integrated circuit device having stacked dies and impedance balanced transmission lines 有权
标题翻译：具有堆叠管芯和阻抗平衡传输线的集成电路器件
公开(公告)号：USRE43720E1
公开(公告)日：2012-10-09
申请号：US11229445
申请日：2005-09-15
申请人： Donald V. Perino , Sayeh Khalili
发明人： Donald V. Perino , Sayeh Khalili
IPC分类号： H01L23/34 , H01L23/48 , H01L23/02 , H05K7/00
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/5385 , H01L24/48 , H01L24/49 , H01L24/50 , H01L25/0652 , H01L2224/0401 , H01L2224/05599 , H01L2224/32145 , H01L2224/4809 , H01L2224/48091 , H01L2224/48095 , H01L2224/48145 , H01L2224/48227 , H01L2224/484 , H01L2224/49175 , H01L2224/73265 , H01L2224/85399 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01083 , H01L2924/014 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19104 , H01L2924/30107 , H01L2924/3011 , H01L2224/45099 , H01L2924/00012
摘要： A multi-chip device which includes a plurality of integrated circuit die disposed one over another. Each integrated circuit die includes one or a plurality of bond pads. One or a plurality of conductors are disposed to electrically couple the bond pads of vertically adjacent integrated circuit die. Each conductor is designed, calculated, specified and/or predetermined to have a length so as to behave as a segment in a multi-drop transmission line. The multi-drop transmission line may be terminated at one end or utilized in a flow-through approach. In one embodiment, an integrated circuit die may be horizontally offset with respect to a vertically adjacent integrated circuit die to expose the periphery region. In another embodiment, each integrated circuit die may be stacked and aligned in a vertical column. In this embodiment, a spacer such as a thermally conductive spacer is disposed between each integrated circuit die in the stack. In yet another embodiment, two or more stacks of integrated circuit die are disposed in the multi-chip device and the one or more multi-drop transmission lines may be implemented in the flow-through approach. The plurality of integrated circuit die may comprise a plurality of memory devices, or a plurality of memory devices and a controller, or a plurality of controllers and a plurality of memory devices.
摘要翻译：一种多芯片器件，包括多个集成电路管芯，所述多个集成电路管芯设置在另一个上。每个集成电路管芯包括一个或多个接合焊盘。设置一个或多个导体以电耦合垂直相邻的集成电路管芯的接合焊盘。每个导体被设计，计算，指定和/或预定为具有一个长度以便在多点传输线路中作为一个段。多滴传输线可以在一端终止或以流通方式使用。在一个实施例中，集成电路管芯可以相对于垂直相邻的集成电路管芯水平地偏移以暴露外围区域。在另一个实施例中，每个集成电路管芯可以堆叠并在垂直列中对准。在该实施例中，诸如导热间隔件之类的间隔件设置在堆叠中的每个集成电路管芯之间。在另一个实施例中，集成电路管芯的两个或多个堆叠设置在多芯片器件中，并且可以以流通方式实现一个或多个多点传输线。多个集成电路管芯可以包括多个存储器件，或多个存储器件和控制器，或多个控制器和多个存储器件。

6. 发明授权

US06621155B1 Integrated circuit device having stacked dies and impedance balanced transmission lines 有权
标题翻译：具有堆叠管芯和阻抗平衡传输线的集成电路器件
公开(公告)号：US06621155B1
公开(公告)日：2003-09-16
申请号：US09471304
申请日：1999-12-23
申请人： Donald V. Perino , Sayeh Khalili
发明人： Donald V. Perino , Sayeh Khalili
IPC分类号： H01L2334
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/5385 , H01L24/48 , H01L24/49 , H01L24/50 , H01L25/0652 , H01L2224/0401 , H01L2224/05599 , H01L2224/32145 , H01L2224/4809 , H01L2224/48091 , H01L2224/48095 , H01L2224/48145 , H01L2224/48227 , H01L2224/484 , H01L2224/49175 , H01L2224/73265 , H01L2224/85399 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01083 , H01L2924/014 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19104 , H01L2924/30107 , H01L2924/3011 , H01L2224/45099 , H01L2924/00012
摘要： A multi-chip device which includes a plurality of integrated circuit die disposed one over another. Each integrated circuit die includes one or a plurality of bond pads. One or a plurality of conductors are disposed to electrically couple the bond pads of vertically adjacent integrated circuit die. Each conductor is designed, calculated, specified and/or predetermined to have a length so as to behave as a segment in a multi-drop transmission line. The multi-drop transmission line may be terminated at one end or utilized in a flow-through approach. In one embodiment, an integrated circuit die may be horizontally offset with respect to a vertically adjacent integrated circuit die to expose the periphery region. In another embodiment, each integrated circuit die may be stacked and aligned in a vertical column. In this embodiment, a spacer such as a thermally conductive spacer is disposed between each integrated circuit die in the stack. In yet another embodiment, two or more stacks of integrated circuit die are disposed in the multi-chip device and the one or more multi-drop transmission lines may be implemented in the flow-through approach. The plurality of integrated circuit die may comprise a plurality of memory devices, or a plurality of memory devices and a controller, or a plurality of controllers and a plurality of memory devices.
摘要翻译：一种多芯片器件，包括多个集成电路管芯，所述多个集成电路管芯设置在另一个上。每个集成电路管芯包括一个或多个接合焊盘。设置一个或多个导体以电耦合垂直相邻的集成电路管芯的接合焊盘。每个导体被设计，计算，指定和/或预定为具有一个长度以便在多点传输线路中作为一个段。多滴传输线可以在一端终止或以流通方式使用。在一个实施例中，集成电路管芯可以相对于垂直相邻的集成电路管芯水平地偏移以暴露外围区域。在另一个实施例中，每个集成电路管芯可以堆叠并在垂直列中对准。在该实施例中，诸如导热间隔件之类的间隔件设置在堆叠中的每个集成电路管芯之间。在另一个实施例中，集成电路管芯的两个或多个堆叠设置在多芯片器件中，并且可以以流通方式实现一个或多个多点传输线。多个集成电路管芯可以包括多个存储器件，或多个存储器件和控制器，或多个控制器和多个存储器件。

7. 发明授权

US06853557B1 Multi-channel memory architecture 失效
标题翻译：多通道内存架构
公开(公告)号：US06853557B1
公开(公告)日：2005-02-08
申请号：US09665920
申请日：2000-09-20
申请人： Belgacem Haba , Sayeh Khalili , Donald R. Mullen , Nader Gamini
发明人： Belgacem Haba , Sayeh Khalili , Donald R. Mullen , Nader Gamini
IPC分类号： G11C5/00 , H05K1/14 , H05K7/02
CPC分类号： H05K1/14 , G11C5/00 , H05K2201/10159
摘要： A memory architecture includes a first substrate containing multiple memory devices and a first channel portion extending across the first substrate. The architecture further includes a second substrate containing multiple memory devices and a second channel portion extending across the second substrate. A connector couples the first channel portion to the second channel portion to form a single channel. The connector includes a first slot that receives an edge of the first substrate and a second slot that receives an edge of the second substrate. Another connector has a pair of slots that receive opposite edges of the first and second substrates. The channel portions extend across the substrates in a substantially linear path. Each channel portion includes multiple conductors having lengths that are approximately equal.
摘要翻译：存储器架构包括包含多个存储器件的第一衬底和跨越第一衬底延伸的第一沟道部分。该架构还包括含有多个存储器件的第二衬底和跨越第二衬底延伸的第二沟道部分。连接器将第一通道部分连接到第二通道部分以形成单一通道。连接器包括接收第一基板的边缘的第一槽和接收第二基板的边缘的第二槽。另一连接器具有接收第一和第二基板的相对边缘的一对槽。通道部分在基本上线性的路径上延伸穿过基板。每个通道部分包括具有近似相等长度的多个导体。

8. 再颁专利

USRE44019E1 Stacked semiconductor module 有权
标题翻译：堆叠式半导体模块
公开(公告)号：USRE44019E1
公开(公告)日：2013-02-19
申请号：US12605303
申请日：2009-10-23
申请人： Thomas F. Fox , Sayeh Khalili , Belgacem Haba , David Nguyen , Richard Warmke , Xingchao Yuan
发明人： Thomas F. Fox , Sayeh Khalili , Belgacem Haba , David Nguyen , Richard Warmke , Xingchao Yuan
IPC分类号： H01L21/00
CPC分类号： G11C5/02 , G11C5/04 , G11C29/08 , G11C2029/4402 , H01L23/5382 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable to identify the integrated circuit dice that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dice and the programmable memory device. The integrated circuit dice of the plurality of integrated circuit dice that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dice.
摘要翻译：提供了半导体模块，其包括半导体外壳和位于壳体内的多个集成电路芯片。半导体模块还包括位于壳体内的电可耦合到多个集成电路芯片的可编程存储器件。可编程存储器件可编程以识别满足预定标准（例如工作频率要求或核心定时等级）的集成电路芯片。此外，提供了一种用于访问半导体模块的方法。提供上述壳体以包围多个集成电路芯片和可编程存储器件。然后识别满足预定标准的多个集成电路芯片的集成电路芯片。随后编程可编程存储器件以识别所选择的集成电路芯片。

9. 发明授权

US06720643B1 Stacked semiconductor module 有权
标题翻译：堆叠式半导体模块
公开(公告)号：US06720643B1
公开(公告)日：2004-04-13
申请号：US09792788
申请日：2001-02-22
申请人： Thomas F. Fox , Sayeh Khalili , Belgacem Haba , David Nguyen , Richard Warmke , Xingchao Yuan
发明人： Thomas F. Fox , Sayeh Khalili , Belgacem Haba , David Nguyen , Richard Warmke , Xingchao Yuan
IPC分类号： H01L2302
CPC分类号： G11C5/02 , G11C5/04 , G11C29/08 , G11C2029/4402 , H01L23/5382 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dies positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dies. The programmable memory device is programmable to identify the integrated circuit dies that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dies and the programmable memory device. The integrated circuit dies of the plurality of integrated circuit dies that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dies.
摘要翻译：提供了半导体模块，其包括半导体壳体和位于壳体内的多个集成电路模具。该半导体模块还包括位于壳体内并可电耦合到多个集成电路管芯的可编程存储器件。可编程存储器件可编程以识别满足预定标准（例如工作频率要求或核心定时等级）的集成电路管芯。此外，提供了一种用于访问半导体模块的方法。提供上述壳体以封闭多个集成电路管芯和可编程存储器件。然后识别满足预定标准的多个集成电路管芯的集成电路管芯。随后编程可编程存储器件以识别所选择的集成电路管芯。

10. 发明申请

US20060160271A1 Stacked semiconductor module 有权
公开(公告)号：US20060160271A1
公开(公告)日：2006-07-20
申请号：US11378008
申请日：2006-03-16
申请人： Thomas Fox , Sayeh Khalili , Belgacem Haba , David Nguyen , Richard Warmke , Xingchao Yuan
发明人： Thomas Fox , Sayeh Khalili , Belgacem Haba , David Nguyen , Richard Warmke , Xingchao Yuan
IPC分类号： H01L21/50
CPC分类号： G11C5/02 , G11C5/04 , G11C29/08 , G11C2029/4402 , H01L23/5382 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable to identify the integrated circuit dice that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dice and the programmable memory device. The integrated circuit dice of the plurality of integrated circuit dice that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dice.

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