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1. 发明授权

US06550015B1 Scalable virtual timer architecture for efficiently implementing multiple hardware timers with minimal silicon overhead 有权
标题翻译：可扩展的虚拟计时器架构，用于以最小的硅开销有效地实现多个硬件定时器
公开(公告)号：US06550015B1
公开(公告)日：2003-04-15
申请号：US09247876
申请日：1999-02-10
申请人： Donald G. Craycraft , Richard G. Russell , Gary M. Godfrey , Mark T. Ellis , Lloyd W. Gauthier
发明人： Donald G. Craycraft , Richard G. Russell , Gary M. Godfrey , Mark T. Ellis , Lloyd W. Gauthier
IPC分类号： G06F104
CPC分类号： G06F1/14
摘要： The scalable virtual timer system or subsystem implements multiple hardware timers with minimal silicon overhead. In one embodiment, for each virtual timer of a plurality of virtual timers, a content addressable memory stores a sum of an “initial state” of a free running counter and a desired count duration for the virtual timer. When the stored value matches a current state of the free running counter, the content addressable memory generates a terminal count for the virtual timer. In an alternative embodiment, for each virtual timer, a period register of a set of period registers stores a sum of a desired count duration for a virtual timer and an “initial state” of the free running counter. A comparator of a set of comparators generates a terminal count for a virtual timer when a current state of the free running counter matches the sum stored in a period register associated with the virtual timer. A state of the free running counter may be read through software, such as by an execution unit, or through hardware, such as by an adder.
摘要翻译：可扩展的虚拟计时器系统或子系统以最小的硅开销实现多个硬件定时器。在一个实施例中，对于多个虚拟定时器的每个虚拟定时器，内容可寻址存储器存储自由运行计数器的“初始状态”和虚拟计时器的期望计数持续时间之和。当存储值与自由运行计数器的当前状态匹配时，内容可寻址存储器生成虚拟计时器的终端计数。在替代实施例中，对于每个虚拟定时器，一组周期寄存器的周期寄存器存储虚拟定时器的期望计数持续时间和自由运行计数器的“初始状态”之和。当自由运行计数器的当前状态与存储在与虚拟定时器相关联的周期寄存器中的和相匹配时，一组比较器的比较器产生虚拟定时器的终端计数。自由运行计数器的状态可以通过软件，例如通过执行单元，或者通过诸如加法器的硬件来读取。

2. 发明授权

US06480929B1 Pseudo-concurrency between a volatile memory and a non-volatile memory on a same data bus 失效
标题翻译：在同一数据总线上的易失性存储器和非易失性存储器之间的伪并发性
公开(公告)号：US06480929B1
公开(公告)日：2002-11-12
申请号：US09184270
申请日：1998-10-31
申请人： Lloyd W. Gauthier , Jim Mergard , Gary M. Godfrey , Richard G. Russell
发明人： Lloyd W. Gauthier , Jim Mergard , Gary M. Godfrey , Richard G. Russell
IPC分类号： G06F1200
CPC分类号： G06F13/1694
摘要： A system provides pseudo-concurrency for a volatile memory and a non-volatile memory on a same data bus. In one system embodiment, the volatile memory is coupled to its own address bus, and the non-volatile memory is coupled to its own address bus. In another system embodiment, the volatile memory and non-volatile memory are coupled to a multiplexed address bus. Concurrent with an access cycle to the volatile memory, the non-volatile memory may be precharged. After the access cycle to the volatile memory, a data cycle to a non-volatile memory may be executed. Concurrent with an access cycle to the non-volatile memory, the volatile memory may be precharged. After the access cycle to the non-volatile memory, a data cycle to the volatile memory may be executed.
摘要翻译：系统为易失性存储器和同一数据总线上的非易失性存储器提供伪并发。在一个系统实施例中，易失性存储器耦合到其自己的地址总线，并且非易失性存储器耦合到其自己的地址总线。在另一系统实施例中，易失性存储器和非易失性存储器耦合到多路复用地址总线。与易失性存储器的访问周期同时，非易失性存储器可以被预充电。在到易失性存储器的访问周期之后，可以执行到非易失性存储器的数据周期。与非易失性存储器的访问周期同时，易失性存储器可以被预充电。在到非易失性存储器的访问周期之后，可以执行到易失性存储器的数据周期。

3. 发明授权

US06266797B1 Data transfer network on a computer chip using a re-configurable path multiple ring topology 失效
标题翻译：数据传输网络在计算机芯片上使用可重配置路径多环拓扑
公开(公告)号：US06266797B1
公开(公告)日：2001-07-24
申请号：US08970691
申请日：1997-11-14
申请人： Gary M. Godfrey , Alfred C. Hartmann
发明人： Gary M. Godfrey , Alfred C. Hartmann
IPC分类号： G06F1750
CPC分类号： H04L29/06 , G06F15/78 , G06F15/8015 , H04L12/42 , H04L69/08
摘要： A computer chip including a data transfer network. The data transfer network comprises a plurality of communication ports and a plurality of modules. Each of the communication ports is directly connected to two or more other communication ports, and each of the communication ports is operable to communicate data. Each of the plurality of modules is coupled to at least one of the plurality of communication ports, and the plurality of modules are operable to communicate with each other through the communication ports. Furthermore, the plurality of communication ports are dynamically configurable to form two or more separate communication paths. The plurality of communication ports may be bi-directionally coupled and operable to communicate data with each other. The plurality of communication ports may also be dynamically configurable to form two or more communication rings. A first plurality of communication ports preferably comprise a first communication path, and a second plurality of communication ports comprise a second communication path. A first communication port in the first communication path is connected between two communication ports in the second communication path. The first communication port is then operable to transfer data between the two communication ports in the second communication path. The first plurality of communication ports and the second plurality of communication ports are also dynamically re-configurable to form two or more communication paths. The first plurality of communication ports and the second plurality of communication ports are preferably dynamically re-configurable to form one or more communication rings.
摘要翻译：一种包括数据传输网络的计算机芯片。数据传输网络包括多个通信端口和多个模块。每个通信端口直接连接到两个或更多个其他通信端口，并且每个通信端口可操作以传送数据。多个模块中的每一个耦合到多个通信端口中的至少一个，并且多个模块可操作以通过通信端口相互通信。此外，多个通信端口是可动态配置的，以形成两个或多个单独的通信路径。多个通信端口可以双向耦合并且可操作以彼此通信数据。多个通信端口也可以动态地配置以形成两个或更多个通信环。第一多个通信端口优选地包括第一通信路径，并且第二多个通信端口包括第二通信路径。第一通信路径中的第一通信端口连接在第二通信路径中的两个通信端口之间。第一通信端口然后可操作以在第二通信路径中的两个通信端口之间传送数据。第一多个通信端口和第二多个通信端口也是动态地可重新配置以形成两个或更多个通信路径。优选地，第一多个通信端口和第二多个通信端口被动态地重新配置以形成一个或多个通信环。

4. 发明授权

US6099585A System and method for streamlined execution of instructions 失效
标题翻译：简化执行指令的系统和方法
公开(公告)号：US6099585A
公开(公告)日：2000-08-08
申请号：US75507
申请日：1998-05-08
申请人： Gary M. Godfrey
发明人： Gary M. Godfrey
IPC分类号： G06F9/38 , G06F9/45
CPC分类号： G06F9/3897 , G06F8/443 , G06F9/3885
摘要： A system and method for the streamlined execution of complex or repeating instructions. The method comprises creating a specialized instruction unit for executing a group of operations and then executing the group as they appear in an instruction stream. The system includes a programmable specialized instruction unit for executing the group of instructions as they appear in an instruction stream. The method comprises receiving a plurality of instructions, examining the plurality of instructions, identifying a subset of the plurality of instructions, creating a specialized instruction unit which is operable to execute the subset, and executing the subset in the special instruction unit upon an occurrence of the subset. Examining the plurality of instructions may occur at such times as compiling a computer program, performing an initialization procedure, or fetching or decoding instructions before execution. Identifying the subset includes selecting a series of instructions which require hardware external to the processor. Creating a specialized instruction unit includes programming a programmable logic or device. The method may also include identifying a second subset of the plurality of instructions, preparing a second specialized instruction unit which is operable to execute the second subset, and executing the second subset in the second specialized instruction unit. The specialized instruction unit is preferably embodied in a computer system comprising a decode unit, a plurality of registers coupled to the decode unit, a load/store unit coupled to the decode unit, a branch execute unit coupled to the decode unit, one or more arithmetic/logic units coupled to the decode unit, one or more specialized instruction units coupled to the decide unit, and a writeback unit coupled to the plurality of registers.
摘要翻译：简化执行复杂或重复指令的系统和方法。该方法包括：创建用于执行一组操作的专用指令单元，然后当它们出现在指令流中时执行该组。该系统包括可编程专用指令单元，用于在指令流中出现时执行指令组。所述方法包括：接收多个指令，检查所述多个指令，识别所述多个指令的子集，创建可操作以执行所述子集的专用指令单元，以及在所述特殊指令单元发生时执行所述子集子集。检查多个指令可以在编译计算机程序，执行初始化过程或在执行之前获取或解码指令的时候发生。识别子集包括选择需要处理器外部硬件的一系列指令。创建专门的指令单元包括对可编程逻辑或器件进行编程。该方法还可以包括识别多个指令的第二子集，准备可操作以执行第二子集的第二专用指令单元，以及执行第二专用指令单元中的第二子集。专用指令单元优选地体现在计算机系统中，计算机系统包括解码单元，耦合到解码单元的多个寄存器，耦合到解码单元的加载/存储单元，耦合到解码单元的分支执行单元，一个或多个耦合到解码单元的算术/逻辑单元，耦合到决定单元的一个或多个专用指令单元，以及耦合到多个寄存器的回写单元。

5. 发明授权

US06550031B1 Transparently gathering a chips multiple internal states via scan path and a trigger 有权
标题翻译：通过扫描路径和触发器透明地收集多个内部状态的芯片
公开(公告)号：US06550031B1
公开(公告)日：2003-04-15
申请号：US09413119
申请日：1999-10-06
申请人： Gary M. Godfrey , Floyd Goodrich, III
发明人： Gary M. Godfrey , Floyd Goodrich, III
IPC分类号： G06F1127
CPC分类号： G06F11/27 , G01R31/3177 , G01R31/318533
摘要： A microcontroller has many miscellaneous logics. The miscellaneous logic can include input/outputs of combinational logic or peripheral devices of the microcontroller, storage devices such as latches, or registers. The miscellaneous logic is coupled to multiple stages of scan cells. The multiple stages can be used as a buffer while the last stage of scan cells are scanned out. A predetermined stage of scan cells are coupled together to form a scan path where data from the miscellaneous logic can be outputted to an external memory. In one embodiment, the predetermined stage is the last stage of scan cells. A trigger signal is used to shift the data from the miscellaneous logic to the next stage of scan cells. Once the last stage of scan cells are loaded, a clocking signal can be provided so that the data in the predetermined stage of scan cells is scanned out. The present invention provides among other things, a graceful way to capture data from miscellaneous logic of the microcontroller using scan hardware.
摘要翻译：微控制器具有许多杂项逻辑。该杂项逻辑可以包括微控制器的组合逻辑或外围设备的输入/输出，诸如锁存器或寄存器的存储设备。杂项逻辑耦合到多个扫描单元级。扫描单元的最后一个阶段可以将多个阶段用作缓冲区。扫描单元的预定阶段被耦合在一起以形成扫描路径，其中来自该杂项逻辑的数据可被输出到外部存储器。在一个实施例中，预定阶段是扫描单元的最后阶段。触发信号用于将数据从杂逻辑移位到扫描单元的下一级。一旦扫描单元的最后阶段被加载，就可以提供时钟信号，以便扫描单元的预定级的数据被扫描出来。本发明尤其提供了使用扫描硬件从微控制器的各种逻辑中捕获数据的优雅方式。

6. 发明授权

US6111859A Data transfer network on a computer chip utilizing combined bus and ring topologies 失效
标题翻译：使用组合总线和环形拓扑的计算机芯片上的数据传输网络
公开(公告)号：US6111859A
公开(公告)日：2000-08-29
申请号：US957589
申请日：1997-10-24
申请人： Gary M. Godfrey , J. Andrew Lambrecht , Alfred C. Hartmann
发明人： Gary M. Godfrey , J. Andrew Lambrecht , Alfred C. Hartmann
IPC分类号： H04L12/42 , H04L29/06 , H04L2/28
CPC分类号： H04L12/42 , H04L29/06 , H04L69/08
摘要： A computer chip includes a data transfer network. The data transfer network comprises a backbone bus, a plurality of communication ports and a plurality of devices or modules each coupled to the backbone bus. Each of the devices includes or is coupled to one or more communication ports. Some of communication ports are operable to transmit and receive data on the backbone bus. Furthermore, the communication ports are interconnected in a ring topology forming a circular bus or a semi-circular bus. A subset of the communication ports may transmit and receive data on the circular bus or semi-circular bus. For the semi-circular bus, the communication ports are not coupled to form a complete ring topology. The communication ports may be operable to communicate with each other over the backbone bus and/or the circular bus. Each of the communication ports includes backbone bus interface logic, circular bus interface logic, one or more data transfer buffers and/or control logic. The communication ports are preferably able to transfer communications between the backbone bus, the circular bus and/or the modules.
摘要翻译：计算机芯片包括数据传输网络。数据传输网络包括骨干总线，多个通信端口以及各自耦合到骨干总线的多个设备或模块。每个设备包括或耦合到一个或多个通信端口。一些通信端口可用于在骨干总线上发送和接收数据。此外，通信端口以环形拓扑互连，形成圆形总线或半圆形总线。通信端口的子集可以在圆形总线或半圆形总线上发送和接收数据。对于半圆形总线，通信端口不耦合以形成完整的环形拓扑。通信端口可以可操作以通过骨干总线和/或循环总线彼此通信。每个通信端口包括主干总线接口逻辑，循环总线接口逻辑，一个或多个数据传输缓冲器和/或控制逻辑。通信端口优选地能够在骨干总线，圆形总线和/或模块之间传送通信。

7. 发明授权

US06724772B1 System-on-a-chip with variable bandwidth 失效
标题翻译：具有可变带宽的片上系统
公开(公告)号：US06724772B1
公开(公告)日：2004-04-20
申请号：US09148923
申请日：1998-09-04
申请人： David J. Borland , Gary M. Godfrey
发明人： David J. Borland , Gary M. Godfrey
IPC分类号： H04J316
CPC分类号： H04J3/1682
摘要： A system-on-a-chip with a variable bandwidth bus. The integrated circuit includes at least one bus, a clock, a plurality of modules coupled to the bus and operable to transfer and receive data on the bus, and a bus controller coupled to the bus that controls data transfers on the bus. The modules are operable to generate requests to the bus controller to perform transfers on the bus. Each request comprises an identifier which identifies one or more receiving modules, a transfer size value which specifies the amount of data to be transferred, and a timing value providing a time frame within which the requested data transfer should occur. Thee bus controller receives the requests, analyzes the timing value, and selectively allocates bandwidth on the bus based on the timing value, the bus controller may also examine the transfer size value or a priority value, and further determine a minimum rate of transfer required to provide the bandwidth on the bus to meet the time frame within which the requested transfer should occur. The integrated circuit may further comprises a power control device coupled to or part of the bus controller, which monitors power consumption and provides power conservation information to the bus controller. The bus controller may further adjust usage of the bus in response to the power conservation information provided by the power control device. The bus may be a time division, multiple access (TDMA) bus. The bus controller may enable data transfers on the TDMA bus only during assigned time slots of assigned frequency and assigned length. The bus controller may also further adjust assignment of the TDMA bus in response to the power conservation information.
摘要翻译：具有可变带宽总线的片上系统。集成电路包括至少一个总线，时钟，耦合到总线并可操作以在总线上传送和接收数据的多个模块，以及耦合到总线的总线控制器，总线控制器控制总线上的数据传输。模块可操作以产生对总线控制器的请求，以在总线上执行传输。每个请求包括标识一个或多个接收模块的标识符，指定要传送的数据量的传送大小值以及提供在其中发生所请求的数据传输的时间帧的定时值。您的总线控制器接收请求，分析定时值，并根据定时值选择性地在总线上分配带宽，总线控制器还可以检查传输大小值或优先级值，并进一步确定所需的最小传输速率在总线上提供带宽，以满足所请求的传输发生的时间范围。集成电路还可以包括耦合到总线控制器或其总线控制器的一部分的功率控制装置，其监视功率消耗并向总线控制器提供功率节省信息。总线控制器可以响应于由电力控制装置提供的功率节省信息，进一步调整总线的使用。总线可以是时分多址（TDMA）总线。总线控制器可以仅在分配的频率和分配的长度的分配时隙期间在TDMA总线上实现数据传输。总线控制器还可以响应于功率节省信息进一步调整TDMA总线的分配。

8. 发明授权

US06560240B1 System-on-a-chip with variable clock rate 有权
标题翻译：具有可变时钟速率的片上系统
公开(公告)号：US06560240B1
公开(公告)日：2003-05-06
申请号：US09148101
申请日：1998-09-04
申请人： David J. Borland , Gary M. Godfrey
发明人： David J. Borland , Gary M. Godfrey
IPC分类号： H04B7212
CPC分类号： G06F1/3203 , G06F1/3253 , Y02D10/126 , Y02D10/151
摘要： A system-on-a-chip with a variable clock rate bus. The integrated circuit includes at least one bus, a clock, a plurality of modules coupled to the bus and operable to transfer and receive data on the bus, and a bus controller coupled to the bus that controls data transfers on the bus. The modules are operable to generate requests to the bus controller to perform transfers on the bus. Each request comprises an identifier which identifies one or more receiving modules, a transfer size value which specifies the amount of data to be transferred, and a timing value providing a time frame within which the requested data transfer should occur. Thee bus controller receives the requests, analyzes the timing value, and selectively adjusts the clock rate of the bus based on the timing value. The bus controller may also examine the transfer size value or a priority value, and further determine a minimum rate of transfer required to provide the bandwidth on the bus to meet the time frame within which the requested transfer should occur. The integrated circuit may further comprises a power control device coupled to or part of the bus controller, which monitors power consumption and provides power conservation information to the bus controller. The bus controller may further adjust usage of the bus in response to the power conservation information provided by the power control device. The bus may be a time division, multiple access (TDMA) bus. The bus controller may enable data transfers on the TDMA bus only during assigned time slots of assigned frequency and assigned length. The bus controller may also further adjust assignment of the TDMA bus in response to the power conservation information.
摘要翻译：具有可变时钟速率总线的片上系统。集成电路包括至少一个总线，时钟，耦合到总线并可操作以在总线上传送和接收数据的多个模块，以及耦合到控制总线上的数据传输的总线的总线控制器。模块可操作以产生对总线控制器的请求，以在总线上执行传输。每个请求包括标识一个或多个接收模块的标识符，指定要传送的数据量的传送大小值以及提供在其中发生所请求的数据传输的时间帧的定时值。总线控制器接收请求，分析定时值，并根据定时值有选择地调整总线的时钟速率。总线控制器还可以检查传输大小值或优先级值，并进一步确定在总线上提供带宽所需的最小传输速率以满足请求传输应在其中发生的时间范围。集成电路还可以包括耦合到总线控制器或其总线控制器的一部分的功率控制装置，其监视功率消耗并向总线控制器提供功率节省信息。总线控制器可以响应于由电力控制装置提供的功率节省信息，进一步调整总线的使用。总线可以是时分多址（TDMA）总线。总线控制器可以仅在分配的频率和分配的长度的分配时隙期间在TDMA总线上实现数据传输。总线控制器还可以响应于功率节省信息进一步调整TDMA总线的分配。

9. 发明授权

US06560659B1 Unicode-based drivers, device configuration interface and methodology for configuring similar but potentially incompatible peripheral devices 有权
标题翻译：基于Unicode的驱动程序，设备配置界面和方法，用于配置类似但可能不兼容的外围设备
公开(公告)号：US06560659B1
公开(公告)日：2003-05-06
申请号：US09383480
申请日：1999-08-26
申请人： David F. Tobias , Gary M. Godfrey
发明人： David F. Tobias , Gary M. Godfrey
IPC分类号： G06F300
CPC分类号： G06F13/102
摘要： A computing system employs an unicode driver to access and control peripheral devices by abstracting commands and status data to a level above register sets of similar but potentially incompatible peripheral devices. A unicode may be generated by an operating system or the unicode driver. Unicodes are routed by a device configuration interface that passes the unicodes between the unicode driver and peripheral devices. The peripheral devices include command decoders for performing conversion between unicodes and device-specific instructions. The use of unicode drivers eliminates duplicate driver code and simplifies device configuration for the computing system.
摘要翻译：计算系统采用unicode驱动程序通过将命令和状态数据抽象到类似但可能不兼容的外围设备的寄存器组以上的级别来访问和控制外围设备。 unicode可能由操作系统或unicode驱动程序生成。 Unicode由通过Unicode驱动程序和外围设备之间的unicode的设备配置接口进行路由。外围设备包括用于执行unicode和设备特定指令之间的转换的命令解码器。使用unicode驱动程序消除了重复的驱动程序代码，并简化了计算系统的设备配置。

10. 发明授权

US06289468B1 Technique for controlling system bus timing with on-chip programmable delay lines 有权
标题翻译：利用片上可编程延迟线控制系统总线时序的技术
公开(公告)号：US06289468B1
公开(公告)日：2001-09-11
申请号：US09187383
申请日：1998-11-06
申请人： Gary M. Godfrey
发明人： Gary M. Godfrey
IPC分类号： G06F112
CPC分类号： G11C7/22 , G06F5/06 , G06F13/4243 , G06F2205/104 , G11C8/18 , G11C11/4076
摘要： An on-chip programmable delay line is provided for controlling timing of an embedded system. A delay register is coupled to a processor. The delay register stores a delay or control value responsive to the processor. The on-chip programmable delay line is coupled to the delay register and delays a signal responsive to the delay value. The relationship between dynamic random access memory (DRAM) signals, such as row address strobe (RAS) and column address strobe (CAS), can thus be adjusted. In addition, the on-chip programmable delay line can be utilized with a device that includes an input that is not synchronous to a system clock.
摘要翻译：提供片上可编程延迟线，用于控制嵌入式系统的时序。延迟寄存器耦合到处理器。延迟寄存器响应于处理器存储延迟或控制值。片上可编程延迟线耦合到延迟寄存器并响应延迟值延迟信号。因此可以调整动态随机存取存储器（DRAM）信号（例如行地址选通（RAS）和列地址选通（CAS））之间的关系。此外，片上可编程延迟线可以与包括与系统时钟不同步的输入的器件利用。

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