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1. 发明授权

US06061756A Computer system which performs intelligent byte slicing/data packing on a multi-byte wide bus 失效
标题翻译：在多字节宽总线上执行智能字节分片/数据打包的计算机系统
公开(公告)号：US06061756A
公开(公告)日：2000-05-09
申请号：US89025
申请日：1998-06-02
申请人： Drew J. Dutton , Scott E. Swanstrom , J. Andrew Lambrecht
发明人： Drew J. Dutton , Scott E. Swanstrom , J. Andrew Lambrecht
IPC分类号： G06F13/368 , G06F13/372 , G06F13/40 , H04N21/238 , G06F13/38
CPC分类号： H04N21/238 , G06F13/368 , G06F13/372 , G06F13/4013 , G06F13/4027
摘要： A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and may also include a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes byte slicing and/or data packing logic coupled to one or more of the expansion bus and/or the multimedia bus which operates to allow different data streams to use different byte channels simultaneously. Thus the byte sliced bus allows different peripherals to share the bus simultaneously. The byte slicing logic thus may assign one data stream to a subset of the total byte lanes on the multimedia bus, and fill the unused byte lanes with another data stream. The data packing logic may optimally fill the bus with data having more or fewer bits than the bus. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.
摘要翻译：针对实时应用程序进行了优化的计算机系统，提高了当前计算机体系结构的性能。该系统包括标准本地系统总线或扩展总线，例如PCI总线，并且还可以包括专用实时总线或多媒体总线。各种多媒体设备耦合到一个或多个扩展总线和/或多媒体总线。计算机系统包括耦合到扩展总线和/或多媒体总线中的一个或多个的字节分片和/或数据打包逻辑，其操作以允许不同的数据流同时使用不同的字节通道。因此，字节分片总线允许不同的外设同时共享总线。因此，字节分片逻辑可以将一个数据流分配给多媒体总线上的总字节通道的子集，并且用另一个数据流填充未使用的字节通道。数据打包逻辑可以使用比总线更多或更少位的数据来最佳地填充总线。因此，本发明的计算机系统为实时应用提供比现有系统更大的性能。

2. 发明授权

US5935232A Variable latency and bandwidth communication pathways 失效
标题翻译：可变延迟和带宽通信路径
公开(公告)号：US5935232A
公开(公告)日：1999-08-10
申请号：US969860
申请日：1997-11-14
申请人： J. Andrew Lambrecht , Alfred C. Hartmann
发明人： J. Andrew Lambrecht , Alfred C. Hartmann
IPC分类号： G06F13/12 , G06F13/36 , G06F13/368 , G06F13/372 , G06F13/40 , H04N7/24 , G06F13/00
CPC分类号： G06F13/124 , G06F13/36 , G06F13/368 , G06F13/372 , G06F13/4022 , G06F13/4027 , H04N21/238
摘要： A system and method for choosing communication pathways for data transfers on a computer chip based on desired latency and bandwidth characteristics. On a computer chip including a network of resources, those resources are allocated based upon the needs of the various components of the computer chip. Typical resources on the computer chip include a first bus with a plurality of data lines and control lines and having first bandwidth and latency characteristics, a second bus with a plurality of data lines and control lines having second bandwidth and latency characteristics, and a plurality of devices coupled to the first bus and second bus. Each device includes interface logic for accessing and performing transfers on the first and second buses. Each device is operable to select either the first or second bus depending on desired bandwidth and latency characteristics. Normally the first bandwidth is greater than the second bandwidth. Each device selects the first bus for higher speed transfers or the second bus for lower speed transfers. When the first latency is shorter than the second latency, each of the devices select the first bus for lower latency transfers and the second bus for higher latency transfers. Other characteristics which may be varies by each device according to the transmission needs of the particular device include clock rate, block size, and bus protocol depending upon desired bandwidth and latency characteristics. For highest possible bandwidth transfers, a multiple bus transfer may be requested by any device.
摘要翻译：一种用于基于期望的等待时间和带宽特性在计算机芯片上选择用于数据传输的通信路径的系统和方法。在包括资源网络的计算机芯片上，根据计算机芯片的各个部件的需要分配这些资源。计算机芯片上的典型资源包括具有多个数据线和控制线并具有第一带宽和等待时间特性的第一总线，具有多个数据线的第二总线和具有第二带宽和延迟特性的控制线，以及多个耦合到第一总线和第二总线的设备。每个设备包括用于访问和执行第一和第二总线上的传输的接口逻辑。每个设备可操作以根据期望的带宽和延迟特性选择第一或第二总线。通常，第一个带宽大于第二个带宽。每个设备选择用于更高速度传输的第一个总线或用于较低速度传输的第二个总线。当第一延迟短于第二等待时间时，每个设备选择用于较低等待时间传输的第一总线和用于较高等待时间传输的第二总线。根据特定设备的传输需要，每个设备可能会改变的其他特性包括时钟速率，块大小和总线协议，这取决于期望的带宽和延迟特性。对于最高可能的带宽传输，可以由任何设备请求多总线传输。

3. 发明授权

US06247161B1 Dynamically configured on-chip communications paths based on statistical analysis 有权
标题翻译：基于统计分析的动态配置的片上通信路径
公开(公告)号：US06247161B1
公开(公告)日：2001-06-12
申请号：US09145011
申请日：1998-09-01
申请人： J. Andrew Lambrecht , Alfred C. Hartmann , Gary Michael Godfrey
发明人： J. Andrew Lambrecht , Alfred C. Hartmann , Gary Michael Godfrey
IPC分类号： G06F1750
CPC分类号： G06F17/5054 , G06F17/5077
摘要： A computer chip including a data transfer network which comprises a plurality of communications links for transmitting data, a plurality of communication nodes, and a plurality of modules. Each of the communication nodes is directly connected to two or more other communication nodes through respective ones of the communications links. Each communication node is operable to communicate data over the respective one of the communications links. Each module is coupled to at least one of the communication nodes, and the modules are operable to communicate with each other through the communication nodes. The communication nodes are operable to create dynamic routes for the data transferred between any two or more of the plurality of modules over the respective ones of the communications links. The communication nodes form the dynamic routes based on statistical data on previous transmissions between the modules. Each communication node may include respective configuration logic for dynamically configuring the dynamic routes, and each configuration logic may include a memory for storing the statistical data on previous transmissions that passed through the respective communications node. The data transfer network may also comprise a routing module for controlling the dynamic routes based on statistical data. The routing module couples to each communication node and monitors the configuration logic. When present and functioning, the routing module adapts the dynamic routes based on an analysis of the statistical data. The statistical data includes one or more of the following for each respective transmission: priority, source module, destination module, number of data units, elapsed transfer time or minimum required transfer time, and total number of transmissions which pass through a given communications node.
摘要翻译：一种包括数据传输网络的计算机芯片，包括用于发送数据的多个通信链路，多个通信节点和多个模块。每个通信节点通过相应的通信链路直接连接到两个或更多个其他通信节点。每个通信节点可操作以在相应的一个通信链路上传送数据。每个模块耦合到至少一个通信节点，并且模块可操作以通过通信节点彼此通信。通信节点可操作以为通过各个通信链路的多个模块中的任意两个或多个之间传送的数据创建动态路由。通信节点基于模块之前的传输的统计数据形成动态路由。每个通信节点可以包括用于动态地配置动态路由的相应配置逻辑，并且每个配置逻辑可以包括用于存储通过相应通信节点的先前传输的统计数据的存储器。数据传输网络还可以包括用于基于统计数据来控制动态路由的路由模块。路由模块耦合到每个通信节点并监视配置逻辑。当存在和运行时，路由模块将根据统计数据的分析来调整动态路由。统计数据包括每个相应传输的一个或多个以下内容：优先级，源模块，目的地模块，数据单元数，经过的传送时间或最小所需传输时间，以及通过给定通信节点的传输总数。

4. 发明授权

US06205467B1 Microprocessor having a context save unit for saving context independent from interrupt requests 失效
标题翻译：微处理器具有上下文保存单元，用于独立于中断请求来保存上下文
公开(公告)号：US06205467B1
公开(公告)日：2001-03-20
申请号：US08557312
申请日：1995-11-14
申请人： J. Andrew Lambrecht , Brian C. Barnes
发明人： J. Andrew Lambrecht , Brian C. Barnes
IPC分类号： G06F900
CPC分类号： G06F9/3863 , G06F9/461
摘要： A microprocessor including a context save unit is provided. The context save unit is configured to periodically perform context saves. When the microprocessor receives an interrupt signal, the microprocessor enters the interrupt service routine without performing a context save. After completing execution of the interrupt service routine, the microprocessor restores the most recently saved context and begins executing the task at that saved context. The interrupt service routine is entered rapidly but the interrupt service routine does not include instructions for saving the registers which it utilizes to perform its function. The context save unit is configured to perform a context save at the occurrence of a variety of events. A fixed or variable time interval may be selected, and each interval includes several options.
摘要翻译：提供了包括上下文保存单元的微处理器。上下文保存单元配置为定期执行上下文保存。当微处理器接收到中断信号时，微处理器进入中断服务程序，而不执行上下文保存。完成中断服务程序的执行后，微处理器恢复最近保存的上下文，并开始在保存的上下文中执行任务。快速进入中断服务程序，但中断服务程序不包含用于保存用于执行其功能的寄存器的指令。上下文保存单元被配置为在发生各种事件时执行上下文保存。可以选择固定或可变时间间隔，并且每个间隔包括若干选项。

5. 发明授权

US6115242A Chip chassis including a micro-backplane for receiving and connecting a plurality of computer chips 失效
标题翻译：芯片底盘包括用于接收和连接多个计算机芯片的微型背板
公开(公告)号：US6115242A
公开(公告)日：2000-09-05
申请号：US957283
申请日：1997-10-24
申请人： J. Andrew Lambrecht
发明人： J. Andrew Lambrecht
IPC分类号： G06F1/18 , G06F1/20 , H05K7/20 , G06F1/16 , H05K9/00 , H02B1/02
CPC分类号： G06F1/20 , G06F1/183
摘要： A chip chassis comprises a housing for enclosing a plurality of semiconductor devices having electrical contacts. The housing is configured to include a plurality of slots each adapted for receiving a semiconductor device. The housing further comprises a plurality of connectors in each of the slots. Each connector within a respective slot of the housing is adapted to electrically contact corresponding electrical contacts of the semiconductor device when the semiconductor device is inserted within the respective slot. Each of the plurality of connectors in each of the slots is electrically coupled to provide an electrical backplane within the housing for electrical communications between each of the slots. The housing may be configured to couple thermally with a heat sink and provide access for a flow-through of a forced coolant. The slots may be adapted to receive a particular type of semiconductor device. Moreover, the connectors comprised in a particular slot may be configured for electrically contacting corresponding electrical contacts on the particular type of semiconductor device designed for the corresponding slot when that particular type of semiconductor device is inserted within the slot. The particular types of semiconductor devices which may be housed in the chip chassis include processors, memories, or I/O control modules. Some slots may be configured for the semiconductor devices to access external data storage devices for the storage and retrieval of data. The chip chassis may also include one or more of the semiconductor devices configured to be housed in the slots of the housing.
摘要翻译：芯片底盘包括用于封闭具有电触点的多个半导体器件的壳体。壳体被配置为包括适于接收半导体器件的多个槽。壳体还包括在每个狭槽中的多个连接器。当半导体器件插入在相应的槽内时，壳体的相应槽内的每个连接器适于电接触半导体器件的对应的电触头。每个槽中的多个连接器中的每一个电连接以在壳体内提供电背板，用于每个槽之间的电通信。壳体可以被配置为与散热器热耦合并且为强制冷却剂的流通提供通路。槽可以适于接收特定类型的半导体器件。此外，包含在特定槽中的连接器可以被配置用于在将该特定类型的半导体器件插入槽内时，将针对相应槽设计的特定类型的半导体器件上的对应电触点电接触。可以容纳在芯片机箱中的特定类型的半导体器件包括处理器，存储器或I / O控制模块。可以为半导体器件配置一些插槽以访问外部数据存储设备以存储和检索数据。芯片底盘还可以包括配置成容纳在壳体的槽中的一个或多个半导体器件。

6. 发明授权

US6035364A Independent use of bits on an on-chip bus 失效
标题翻译：独立使用片上总线上的位
公开(公告)号：US6035364A
公开(公告)日：2000-03-07
申请号：US989330
申请日：1997-12-11
申请人： J. Andrew Lambrecht , Scott E. Swanstrom
发明人： J. Andrew Lambrecht , Scott E. Swanstrom
IPC分类号： G06F13/12 , G06F13/36 , G06F13/368 , G06F13/372 , G06F13/40 , H04N21/238 , G06F13/38
CPC分类号： H04N21/238 , G06F13/124 , G06F13/36 , G06F13/368 , G06F13/372 , G06F13/4013 , G06F13/4022 , G06F13/4027
摘要： A computer chip including multiple on-chip modules connected by an on-chip bus which provides increased performance over current computer chip architectures. The on-chip system bus is a bit sliced bus. Various transmitters/and or receivers are coupled the bit sliced bus. The transmitters and/or receivers include bus interface logic and/or bit transfer logic and/or bit receive logic operatively coupled to the on-chip bit sliced bus which operates to allow different data streams to use different bit lines substantially simultaneously. Thus the bit sliced bus allows different devices to share the bus simultaneously. The bus interface logic and/or the bit transfer logic thus may assign one data stream to a subset of the total bit lines on the bit sliced bus, and fill the unused bit lines with another data stream.
摘要翻译：包括通过片上总线连接的多个片上模块的计算机芯片，其提供超过当前计算机芯片架构的性能。片上系统总线是一个有点切片的总线。各种发射机和/或接收机与位分片总线耦合。发射器和/或接收器包括可操作地耦合到片上位分片总线的总线接口逻辑和/或位传输逻辑和/或位接收逻辑，其操作以允许不同的数据流基本上同时使用不同的位线。因此，位分片总线允许不同的设备同时共享总线。因此，总线接口逻辑和/或位传输逻辑可以将一个数据流分配给位分片总线上的总位线的子集，并且用另一数据流填充未使用的位线。

7. 发明授权

US06275975B1 Scalable mesh architecture with reconfigurable paths for an on-chip data transfer network incorporating a network configuration manager 有权
标题翻译：具有可重构路径的可扩展网状结构，用于集成了网络配置管理器的片上数据传输网络
公开(公告)号：US06275975B1
公开(公告)日：2001-08-14
申请号：US09189762
申请日：1998-11-10
申请人： J. Andrew Lambrecht , Alfred C. Hartmann , Gary Michael Godfrey
发明人： J. Andrew Lambrecht , Alfred C. Hartmann , Gary Michael Godfrey
IPC分类号： G06F1750
CPC分类号： G06F15/7825
摘要： A computer chip including a data transfer network which comprises a plurality of communications links for transmitting data, a plurality of communication nodes, and a plurality of modules. Each of the communication nodes is directly connected to two or more other communication nodes through respective ones of the communications links. Each communication node is operable to communicate data over the respective one of the communications links. Each module is coupled to at least one of the communication nodes, and the modules are operable to communicate with each other through the communication nodes. The communication nodes are operable to create dynamic routes for the data transferred between any two or more of the plurality of modules over the respective ones of the communications links. The communication nodes form the dynamic routes controlled by a network configuration manager.
摘要翻译：一种包括数据传输网络的计算机芯片，包括用于发送数据的多个通信链路，多个通信节点和多个模块。每个通信节点通过相应的通信链路直接连接到两个或更多个其他通信节点。每个通信节点可操作以在相应的一个通信链路上传送数据。每个模块耦合到至少一个通信节点，并且模块可操作以通过通信节点彼此通信。通信节点可操作以为通过各个通信链路的多个模块中的任意两个或多个之间传送的数据创建动态路由。通信节点形成由网络配置管理器控制的动态路由。

8. 发明授权

US06259792B1 Waveform playback device for active noise cancellation 失效
标题翻译：用于主动噪声消除的波形播放装置
公开(公告)号：US06259792B1
公开(公告)日：2001-07-10
申请号：US08895802
申请日：1997-07-17
申请人： J. Andrew Lambrecht
发明人： J. Andrew Lambrecht
IPC分类号： H04R302
CPC分类号： H04R5/02
摘要： A noise environment is sampled via microphone. A processor generates a cancellation signal to offset the effects of the noise to a listener. The cancellation signal is converted into a sample signal compatible with a synthesizer. The synthesizer adjusts the pitch, amplitude and timing of a sample of a patch set to create a substantially continuous output cancellation signal. The continuous output cancellation signal is output via a speaker. The output cancellation signal combines with the noise environment to reduce the effects of the noise environment on the listener. Alternatively, in previously characterized noise environments, one or more cancellation signals may be stored in processor. The processor receives a user input selecting the appropriate cancellation signal and adjusting the parameters of the cancellation signal. After the processor has calculated or selected the cancellation signal and transferred the sampled signal to the synthesizer, the processor is no longer involved in the generation of the cancellation signal. Therefore, the noise cancellation function requires relatively little processing power and is accomplished without the need for special purpose hardware.
摘要翻译：通过麦克风对噪声环境进行采样。处理器产生消除信号以抵消噪声对听众的影响。消除信号被转换成与合成器兼容的采样信号。合成器调整贴片组的样本的音调，幅度和时序以产生基本上连续的输出消除信号。连续输出消除信号通过扬声器输出。输出消除信号与噪声环境相结合，以减少噪声环境对听众的影响。或者，在先前描述的噪声环境中，一个或多个消除信号可以存储在处理器中。处理器接收选择合适的消除信号并调整消除信号的参数的用户输入。在处理器计算或选择了消除信号并将采样的信号传送到合成器之后，处理器不再涉及消除信号的产生。因此，噪声消除功能需要相对较小的处理能力，并且在不需要专用硬件的情况下实现。

9. 发明授权

US06181800B2 System and method for interactive approximation of a head transfer function 失效
标题翻译：一种头部相关传递函数的交互式近似的系统和方法
公开(公告)号：US06181800B2
公开(公告)日：2001-01-30
申请号：US08813454
申请日：1997-03-10
申请人： J. Andrew Lambrecht
发明人： J. Andrew Lambrecht
IPC分类号： H04R502
CPC分类号： H04S1/002 , H04S1/005 , H04S2420/01
摘要： A head related transfer function (HRTF) is used to simulate positional three-dimensional sound. The HRTF accounts for the frequency response, delays and reflections of the human body. The HRTF is unique to each individual and is affected by the shape and size of the head, the shape and size of the pinnae, the characteristics of the ear canal and the relationships of the shoulder to the ear. An HRTF for an individual is interactively approximated by first choosing a generalized HRTF. A computer, or other device, outputs audio signals from fixed locations using the generalized HRTF. Although the sound is output from fixed positions, a user may be expected to perceive the sound from a position different than the fixed position from which the sound is output. The user inputs the actual perceived position of the sound to the computer. The computer calculates positional errors between the expected perceived position of the sound and the actual perceived position of the sound. The positional errors are used to either adjust the parameters of the current HRTF or select a new HRTF. The above process is repeated with an adjusted or new HRTF until the positional errors of the HRTF are within an acceptable range of error.
摘要翻译：头相关传递函数（HRTF）用于模拟位置三维声音。 HRTF考虑了人体的频率响应，延误和反思。 HRTF对于每个人都是独一无二的，并且受到头部的形状和尺寸，猿的形状和尺寸，耳道的特征以及肩部与耳朵的关系的影响。通过首先选择一个广义的HRTF来交互地近似一个个体的HRTF。计算机或其他设备使用广义HRTF从固定位置输出音频信号。尽管从固定位置输出声音，但是可以期望用户感知来自与声音被输出的固定位置不同的位置的声音。用户将声音的实际感知位置输入到计算机。计算机计算声音的预期感知位置和声音的实际感知位置之间的位置误差。位置误差用于调整当前HRTF的参数或选择新的HRTF。用调整或新的HRTF重复上述过程，直到HRTF的位置误差在可接受的误差范围内。

10. 发明授权

US6111859A Data transfer network on a computer chip utilizing combined bus and ring topologies 失效
标题翻译：使用组合总线和环形拓扑的计算机芯片上的数据传输网络
公开(公告)号：US6111859A
公开(公告)日：2000-08-29
申请号：US957589
申请日：1997-10-24
申请人： Gary M. Godfrey , J. Andrew Lambrecht , Alfred C. Hartmann
发明人： Gary M. Godfrey , J. Andrew Lambrecht , Alfred C. Hartmann
IPC分类号： H04L12/42 , H04L29/06 , H04L2/28
CPC分类号： H04L12/42 , H04L29/06 , H04L69/08
摘要： A computer chip includes a data transfer network. The data transfer network comprises a backbone bus, a plurality of communication ports and a plurality of devices or modules each coupled to the backbone bus. Each of the devices includes or is coupled to one or more communication ports. Some of communication ports are operable to transmit and receive data on the backbone bus. Furthermore, the communication ports are interconnected in a ring topology forming a circular bus or a semi-circular bus. A subset of the communication ports may transmit and receive data on the circular bus or semi-circular bus. For the semi-circular bus, the communication ports are not coupled to form a complete ring topology. The communication ports may be operable to communicate with each other over the backbone bus and/or the circular bus. Each of the communication ports includes backbone bus interface logic, circular bus interface logic, one or more data transfer buffers and/or control logic. The communication ports are preferably able to transfer communications between the backbone bus, the circular bus and/or the modules.
摘要翻译：计算机芯片包括数据传输网络。数据传输网络包括骨干总线，多个通信端口以及各自耦合到骨干总线的多个设备或模块。每个设备包括或耦合到一个或多个通信端口。一些通信端口可用于在骨干总线上发送和接收数据。此外，通信端口以环形拓扑互连，形成圆形总线或半圆形总线。通信端口的子集可以在圆形总线或半圆形总线上发送和接收数据。对于半圆形总线，通信端口不耦合以形成完整的环形拓扑。通信端口可以可操作以通过骨干总线和/或循环总线彼此通信。每个通信端口包括主干总线接口逻辑，循环总线接口逻辑，一个或多个数据传输缓冲器和/或控制逻辑。通信端口优选地能够在骨干总线，圆形总线和/或模块之间传送通信。

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