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1. 发明授权

US08417814B1 Application quality of service envelope 有权
标题翻译：应用服务质量信息
公开(公告)号：US08417814B1
公开(公告)日：2013-04-09
申请号：US10948811
申请日：2004-09-22
申请人： Alfred C. Hartmann
发明人： Alfred C. Hartmann
IPC分类号： G06F15/173
CPC分类号： G06F9/5011 , G06F2209/504 , G06F2209/508 , Y02D10/22
摘要： A managed node executes one or more applications. The applications utilize the resources of the node. A quality-of-service (QoS) agent on the managed node enforces a QoS policy for the node. The QoS agent characterizes an application's usage of the node's resources and predicts its future usage. The QoS agent analyzes the predicted resource usage in view of the QoS policy and generates a QoS envelope for the application. The QoS envelope specifies a ceiling on the level of resources that can be used by the application. The QoS agent queues and meters usage above the ceiling specified by the QoS envelope. A security module determines variations between predicted and actual resource usage and generates security events if warranted.
摘要翻译：受管节点执行一个或多个应用程序。应用程序利用节点的资源。受管节点上的服务质量（QoS）代理对该节点执行QoS策略。 QoS代理表征应用程序对节点资源的使用情况，并预测其未来的使用情况。 QoS代理根据QoS策略分析预测的资源使用情况，并为应用程序生成QoS包络。 QoS包络指定应用程序可以使用的资源级别的上限。 QoS代理队列和计量使用高于QoS包络指定的上限。安全模块确定预测资源和实际资源使用情况之间的差异，并在需要的情况下生成安全事件。

2. 发明授权

US06266797B1 Data transfer network on a computer chip using a re-configurable path multiple ring topology 失效
标题翻译：数据传输网络在计算机芯片上使用可重配置路径多环拓扑
公开(公告)号：US06266797B1
公开(公告)日：2001-07-24
申请号：US08970691
申请日：1997-11-14
申请人： Gary M. Godfrey , Alfred C. Hartmann
发明人： Gary M. Godfrey , Alfred C. Hartmann
IPC分类号： G06F1750
CPC分类号： H04L29/06 , G06F15/78 , G06F15/8015 , H04L12/42 , H04L69/08
摘要： A computer chip including a data transfer network. The data transfer network comprises a plurality of communication ports and a plurality of modules. Each of the communication ports is directly connected to two or more other communication ports, and each of the communication ports is operable to communicate data. Each of the plurality of modules is coupled to at least one of the plurality of communication ports, and the plurality of modules are operable to communicate with each other through the communication ports. Furthermore, the plurality of communication ports are dynamically configurable to form two or more separate communication paths. The plurality of communication ports may be bi-directionally coupled and operable to communicate data with each other. The plurality of communication ports may also be dynamically configurable to form two or more communication rings. A first plurality of communication ports preferably comprise a first communication path, and a second plurality of communication ports comprise a second communication path. A first communication port in the first communication path is connected between two communication ports in the second communication path. The first communication port is then operable to transfer data between the two communication ports in the second communication path. The first plurality of communication ports and the second plurality of communication ports are also dynamically re-configurable to form two or more communication paths. The first plurality of communication ports and the second plurality of communication ports are preferably dynamically re-configurable to form one or more communication rings.
摘要翻译：一种包括数据传输网络的计算机芯片。数据传输网络包括多个通信端口和多个模块。每个通信端口直接连接到两个或更多个其他通信端口，并且每个通信端口可操作以传送数据。多个模块中的每一个耦合到多个通信端口中的至少一个，并且多个模块可操作以通过通信端口相互通信。此外，多个通信端口是可动态配置的，以形成两个或多个单独的通信路径。多个通信端口可以双向耦合并且可操作以彼此通信数据。多个通信端口也可以动态地配置以形成两个或更多个通信环。第一多个通信端口优选地包括第一通信路径，并且第二多个通信端口包括第二通信路径。第一通信路径中的第一通信端口连接在第二通信路径中的两个通信端口之间。第一通信端口然后可操作以在第二通信路径中的两个通信端口之间传送数据。第一多个通信端口和第二多个通信端口也是动态地可重新配置以形成两个或更多个通信路径。优选地，第一多个通信端口和第二多个通信端口被动态地重新配置以形成一个或多个通信环。

3. 发明授权

US6096091A Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip 失效
标题翻译：通过倒装FIFO互连的动态可重构逻辑网络，用于片上系统中的灵活流水线处理
公开(公告)号：US6096091A
公开(公告)日：2000-08-01
申请号：US28611
申请日：1998-02-24
申请人： Alfred C. Hartmann
发明人： Alfred C. Hartmann
IPC分类号： G06F15/78 , G06F17/50 , H03K19/00
CPC分类号： G06F15/7867
摘要： An integrated circuit comprising a plurality of reconfigurable logic networks, one or more buffers, a configuration control network, and an embedded processor, all comprised as an integral part of the integrated circuit, and a method of operation of the integrated circuit. One or more of the buffers are coupled between two of the plurality of reconfigurable logic networks. The buffers isolate the plurality of reconfigurable logic networks from one another. The integration control network is coupled to each of the plurality of reconfigurable logic networks, and may also be coupled to one or more buffers. The embedded processor is operable to reconfigure one or more of the plurality of reconfigurable logic networks over the configuration control network. The integrated circuit may also comprise a local memory. The local memory is coupled to the embedded processor, and is operable to store data and/or instructions accessible by the embedded processor. A logic configuration library may also be comprised on the integrated circuit. The logic configuration library is coupled to the embedded processor and is further coupled to the configuration control network. The logic configuration library is operable to store one more configurations for the plurality of reconfigurable logic networks. The reconfigurable logic networks preferably include at least a first logic network and a second logic network.
摘要翻译：包括多个可重构逻辑网络，一个或多个缓冲器，配置控制网络和嵌入式处理器的集成电路，全部包括作为集成电路的组成部分，以及集成电路的操作方法。一个或多个缓冲器耦合在多个可重构逻辑网络中的两个之间。缓冲器将多个可重新配置的逻辑网络彼此隔离。集成控制网络耦合到多个可重构逻辑网络中的每一个，并且还可以耦合到一个或多个缓冲器。嵌入式处理器可操作以通过配置控制网络来重新配置多个可重构逻辑网络中的一个或多个。集成电路还可以包括本地存储器。本地存储器耦合到嵌入式处理器，并且可操作以存储由嵌入式处理器可访问的数据和/或指令。逻辑配置库也可以包括在集成电路上。逻辑配置库耦合到嵌入式处理器，并进一步耦合到配置控制网络。逻辑配置库可操作以存储多个可重构逻辑网络的一个配置。可重配置逻辑网络优选地包括至少第一逻辑网络和第二逻辑网络。

4. 发明授权

US6018782A Flexible buffering scheme for inter-module on-chip communications 失效
标题翻译：用于片内模块间通信的灵活缓冲方案
公开(公告)号：US6018782A
公开(公告)日：2000-01-25
申请号：US892415
申请日：1997-07-14
申请人： Alfred C. Hartmann
发明人： Alfred C. Hartmann
IPC分类号： G06F15/78 , G06F15/80 , G06F13/38 , G06F13/00
CPC分类号： G06F15/7842 , G06F15/8007
摘要： A single chip integrated circuit comprises a plurality of modules interconnected in an on-chip network. The modules are processors or memory devices or hybrids. An inter-module link provides an electrical path for data communication among the modules. The modules are connected to the inter-module link by inter-module ports, with at least one inter-module port coupled between an associated module and the inter-module link. The inter-module link electrically couples the inter-module ports and provides a communications pathway between the modules. Each inter-module port provides a common, universal interface to any of the modules, i.e., modules of different types are connectable to any inter-module port. Each inter-module port operates to receive data from the inter-module link, to determine if the data from the inter-module link is addressed to the associated module, to provide the data from the inter-module link to the associated module if the inter-module port determines that the data from the inter-module link is addressed to the associated module, to accept data from the associated module for transmission on the inter-module link, and to transmit the data from the associated module on the inter-module link. The on-chip network may also include an inter-module network switch for joining circuits of the inter-module link and routing data packets from one inter-module links to another or an inter-chip network bridge to join two single chip integrated circuits into a single communications network and route data packets from modules on one computer chip to modules on another computer chip.
摘要翻译：单芯片集成电路包括在片上网络中互连的多个模块。这些模块是处理器或存储器件或混合器。模块间链路为模块之间的数据通信提供电路。模块通过模块间端口连接到模块间链路，其中至少一个模块间端口耦合在相关联的模块和模块间链路之间。模块间链路电连接模块间端口并提供模块之间的通信路径。每个模块间端口为任何模块提供通用的通用接口，即不同类型的模块可连接到任何模块间端口。每个模块间端口操作以从模块间链路接收数据，以确定来自模块间链路的数据是否被寻址到相关联的模块，以将数据从模块间链路提供给相关联的模块，如果模块间端口确定来自模块间链路的数据被发送到相关联的模块，以接收来自相关联的模块的数据以在模块间链路上传输，并且从相关联的模块发送数据，模块链接。片上网络还可以包括用于将模块间链路的电路和从一个模块间链路到另一个或芯片间网桥的路由数据分组的模块间网络交换机，以将两个单芯片集成电路连接到单个通信网络并将数据包从一个计算机芯片上的模块路由到另一个计算机芯片上的模块。

5. 发明授权

US5935232A Variable latency and bandwidth communication pathways 失效
标题翻译：可变延迟和带宽通信路径
公开(公告)号：US5935232A
公开(公告)日：1999-08-10
申请号：US969860
申请日：1997-11-14
申请人： J. Andrew Lambrecht , Alfred C. Hartmann
发明人： J. Andrew Lambrecht , Alfred C. Hartmann
IPC分类号： G06F13/12 , G06F13/36 , G06F13/368 , G06F13/372 , G06F13/40 , H04N7/24 , G06F13/00
CPC分类号： G06F13/124 , G06F13/36 , G06F13/368 , G06F13/372 , G06F13/4022 , G06F13/4027 , H04N21/238
摘要： A system and method for choosing communication pathways for data transfers on a computer chip based on desired latency and bandwidth characteristics. On a computer chip including a network of resources, those resources are allocated based upon the needs of the various components of the computer chip. Typical resources on the computer chip include a first bus with a plurality of data lines and control lines and having first bandwidth and latency characteristics, a second bus with a plurality of data lines and control lines having second bandwidth and latency characteristics, and a plurality of devices coupled to the first bus and second bus. Each device includes interface logic for accessing and performing transfers on the first and second buses. Each device is operable to select either the first or second bus depending on desired bandwidth and latency characteristics. Normally the first bandwidth is greater than the second bandwidth. Each device selects the first bus for higher speed transfers or the second bus for lower speed transfers. When the first latency is shorter than the second latency, each of the devices select the first bus for lower latency transfers and the second bus for higher latency transfers. Other characteristics which may be varies by each device according to the transmission needs of the particular device include clock rate, block size, and bus protocol depending upon desired bandwidth and latency characteristics. For highest possible bandwidth transfers, a multiple bus transfer may be requested by any device.
摘要翻译：一种用于基于期望的等待时间和带宽特性在计算机芯片上选择用于数据传输的通信路径的系统和方法。在包括资源网络的计算机芯片上，根据计算机芯片的各个部件的需要分配这些资源。计算机芯片上的典型资源包括具有多个数据线和控制线并具有第一带宽和等待时间特性的第一总线，具有多个数据线的第二总线和具有第二带宽和延迟特性的控制线，以及多个耦合到第一总线和第二总线的设备。每个设备包括用于访问和执行第一和第二总线上的传输的接口逻辑。每个设备可操作以根据期望的带宽和延迟特性选择第一或第二总线。通常，第一个带宽大于第二个带宽。每个设备选择用于更高速度传输的第一个总线或用于较低速度传输的第二个总线。当第一延迟短于第二等待时间时，每个设备选择用于较低等待时间传输的第一总线和用于较高等待时间传输的第二总线。根据特定设备的传输需要，每个设备可能会改变的其他特性包括时钟速率，块大小和总线协议，这取决于期望的带宽和延迟特性。对于最高可能的带宽传输，可以由任何设备请求多总线传输。

6. 发明授权

US5908468A Data transfer network on a chip utilizing a multiple traffic circle topology 失效
标题翻译：数据传输网络利用多业务圈拓扑的芯片
公开(公告)号：US5908468A
公开(公告)日：1999-06-01
申请号：US957093
申请日：1997-10-24
申请人： Alfred C. Hartmann
发明人： Alfred C. Hartmann
IPC分类号： G06F15/78 , G06F15/80 , G06F13/00
CPC分类号： G06F15/78 , G06F15/8015
摘要： A computer chip includes a plurality of modules interconnected in an on-chip data transfer network configured in a circular topology to form preferably a plurality of traffic circles. The various modules may be processors, memories and/or hybrids and may include, or be coupled through, a communications port coupled to one of the buses such that the communications port is operable to transmit and receive data on one of the buses. Each of the communications ports is operable to route data from a source bus to a destination bus. The traffic circles are formed by groups of communications ports, and buses or groups of transfer paths. The buses may be operable to transfer data in only one direction or in two directions. The transfer of data on the buses by the modules may be controlled by an on-chip bus controller coupled to one or more of the buses. The bus controller may also include arbiter logic for arbitrating access to one or more of the plurality of buses. One or more of the plurality of communications ports may be further operable to transfer data from one of the buses to a bus connection operable to route data to a device external to computer chip. One or more of the plurality of buses includes addressing and control lines.
摘要翻译：计算机芯片包括互连在片上数据传输网络中的多个模块，其被配置成圆形拓扑结构，以优选地形成多个业务圈。各种模块可以是处理器，存储器和/或混合器，并且可以包括耦合到总线之一的通信端口，或者耦合到通信端口，使得通信端口可操作以在总线之一上发送和接收数据。每个通信端口可操作以将数据从源总线路由到目的地总线。交通圈由通信端口组，公交车组或传输路径组成。总线可以用于仅在一个方向或两个方向上传送数据。通过模块传输总线上的数据可以由耦合到一个或多个总线的片上总线控制器来控制。总线控制器还可以包括用于仲裁访问多个总线中的一个或多个的仲裁器逻辑。多个通信端口中的一个或多个可以进一步可操作以将数据从总线之一传送到可操作以将数据路由到计算机芯片外部的设备的总线连接。多个总线中的一个或多个包括寻址和控制线。

7. 发明授权

US5878265A Data transfer network on a chip utilizing polygonal hub topology 失效
标题翻译：使用多边形集线器拓扑的芯片上的数据传输网络
公开(公告)号：US5878265A
公开(公告)日：1999-03-02
申请号：US891817
申请日：1997-07-14
申请人： Alfred C. Hartmann
发明人： Alfred C. Hartmann
IPC分类号： G06F15/173 , G06F15/80
CPC分类号： G06F15/8007 , G06F15/17337
摘要： A computer chip includes a plurality of modules interconnected in an on-chip data transfer network configured in a mesh of rings, ring or rings, or polygonal hub topology. The data transfer network includes links or buses and a switchpoint. The links or buses are configured in a ring topology as a ring of rings or polygonal hub with each group of links or bus including a portion which is shared with a portion of another group of links bus. The bus switchpoint is positioned as a hub at the intersection of the ring of rings. The switchpoint is operable to route data from a source to a destination so that the modules are operable to communicate with each other through the links or buses, and the switchpoint. In various embodiments, the modules are coupled to the links or buses and/or the switchpoint. The various modules may be processors, memories or hybrids and may include, or be coupled through, a communication port coupled to one of the links or buses such that the communication port is operable to transmit and receive data on one or more of the groups of links or buses.
摘要翻译：计算机芯片包括互连在片上数据传输网络中的多个模块，其被配置成环形，环形或环形或多边形集线器拓扑结构。数据传输网络包括链路或总线和切换点。链路或总线被配置为环形环形环或环形多边形集线器，每组链路或总线包括与另一组链路总线的一部分共享的部分。总线切换点定位为环形环交叉点处的集线器。切换点可操作以将数据从源路由到目的地，使得模块可操作以通过链路或总线以及切换点彼此通信。在各种实施例中，模块耦合到链路或总线和/或切换点。各种模块可以是处理器，存储器或混合器，并且可以包括耦合到链路或总线之一的通信端口，或者耦合到通信端口，使得通信端口可操作以在一个或多个连接或公共汽车。

8. 发明授权

US08533818B1 Profiling backup activity 有权
标题翻译：分析备份活动
公开(公告)号：US08533818B1
公开(公告)日：2013-09-10
申请号：US11479921
申请日：2006-06-30
申请人： Thomas R. Ketterhagen , Alfred C. Hartmann
发明人： Thomas R. Ketterhagen , Alfred C. Hartmann
IPC分类号： G06F11/00 , G06F12/14 , G06F12/16 , G06F7/04 , G06F17/30 , G08B23/00
CPC分类号： G06F21/567
摘要： Mitigating a network security threat is disclosed. Information associated with a data protection event is received. The received information is evaluated for an indication of a network security threat. One or more remedial actions are performed if it is determined that a potential threat has been indicated. Optionally, the received information is stored.
摘要翻译：披露了减轻网络安全威胁的措施。接收与数据保护事件相关联的信息。对所接收的信息进行评估，以显示网络安全威胁。如果确定已经指示潜在威胁，则执行一个或多个补救措施。可选地，存储所接收的信息。

9. 发明授权

US06047002A Communication traffic circle system and method for performing packet conversion and routing between different packet formats including an instruction field 有权
公开(公告)号：US06047002A
公开(公告)日：2000-04-04
申请号：US227509
申请日：1999-01-06
申请人： Alfred C. Hartmann , Carl K. Wakeland
发明人： Alfred C. Hartmann , Carl K. Wakeland
IPC分类号： H04L12/42 , H04L29/06 , H04L12/56
CPC分类号： H04L29/06 , H04L12/42 , H04L69/08
摘要： A communication system which includes more efficient packet conversion and routing for improved performance and simplified operation. The communication system includes one or more inputs for receiving packet data and one or more outputs for providing packet data. In one embodiment, the present invention comprises a "traffic circle" architecture for routing packet data and converting between different packet formats. In this embodiment, the system includes a data bus configured in a ring or circle. A plurality of port adapters or protocol processors are coupled to the ring data bus or communication circle. Each of the port adapters are configurable for converting between different types of communication packet formats. In the preferred embodiment, each of the port adapters are operable to convert between one or more communication packet formats to/from a generic packet format. The common generic packet format is then provided on the circular bus for circulation on the communication traffic circle between respective ones of the port adapters. In a second embodiment, the present invention comprises a cross-bar switch communication channel. This system is designed to receive a plurality of communications channels comprising packet data. The communication system comprises a plurality of protocol converters or protocol processors for converting possibly differing communication protocols or differing packet formats to/from a common generic packet format. Each of the protocol converters are coupled to a single-sided cross-bar switch to transmit/receive data to/from other protocol converters. The single-sided cross-bar switch is operable for interconnecting the multiple communications paths between arbitrary pairs of communications ports. The system preferably includes arbitration and control logic for establishing and removing connection paths within the cross-bar switch. In the preferred embodiment, the single-sided cross-bar switch is configurable for different transmission paths for added flexibility.

10. 发明授权

US07690037B1 Filtering training data for machine learning 有权
标题翻译：过滤机器学习的培训数据
公开(公告)号：US07690037B1
公开(公告)日：2010-03-30
申请号：US11181221
申请日：2005-07-13
申请人： Alfred C. Hartmann
发明人： Alfred C. Hartmann
IPC分类号： G06F11/00
CPC分类号： H04L63/1433 , G06F21/552 , H04L63/1416
摘要： Data center activity traces form a corpus used for machine learning. The data in the corpus are putatively normal but may be tainted with latent anomalies. There is a statistical likelihood that the corpus represents predominately legitimate activity, and this likelihood is exploited to allow for a targeted examination of only the data representing possible anomalous activity. The corpus is separated into clusters having members with like features. The clusters having the fewest members are identified, as these clusters represent potential anomalous activities. These clusters are evaluated to determine whether they represent actual anomalous activities. The data from the clusters representing actual anomalous activities are excluded from the corpus. As a result, the machine learning is more effective and the trained system provides better performance, since latent anomalies are not mistaken for normal activity.
摘要翻译：数据中心活动痕迹形成用于机器学习的语料库。语料库中的数据是假设正常的，但可能会被潜在的异常污染。统计学上有可能是语料主要表现为合法的活动，并且这种可能性被利用以允许仅对表示可能的异常活动的数据进行有针对性的检查。语料库被分成具有类似特征的成员的群集。识别具有最少成员的群集，因为这些群组代表潜在的异常活动。对这些集群进行评估，以确定它们是否代表实际的异常活动。来自代表实际异常活动的群集的数据从语料库中排除。因此，机器学习更有效，训练有素的系统提供更好的性能，因为潜在的异常不会被误认为正常的活动。

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