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1. 发明授权

US07551617B2 Multi-threaded packet processing architecture with global packet memory, packet recirculation, and coprocessor 有权
标题翻译：具有全局分组存储器，分组再循环和协处理器的多线程分组处理架构
公开(公告)号：US07551617B2
公开(公告)日：2009-06-23
申请号：US11054076
申请日：2005-02-08
申请人： Will Eatherton , Earl T. Cohen , John Andrew Fingerhut , Donald E. Steiss , John Williams
发明人： Will Eatherton , Earl T. Cohen , John Andrew Fingerhut , Donald E. Steiss , John Williams
IPC分类号： H04L12/56
CPC分类号： H04L47/56 , H04L45/60 , H04L47/50
摘要： A network processor has numerous novel features including a multi-threaded processor array, a multi-pass processing model, and Global Packet Memory (GPM) with hardware managed packet storage. These unique features allow the network processor to perform high-touch packet processing at high data rates. The packet processor can also be coded using a stack-based high-level programming language, such as C or C++. This allows quicker and higher quality porting of software features into the network processor.Processor performance also does not severely drop off when additional processing features are added. For example, packets can be more intelligently processed by assigning processing elements to different bounded duration arrival processing tasks and variable duration main processing tasks. A recirculation path moves packets between the different arrival and main processing tasks. Other novel hardware features include a hardware architecture that efficiently intermixes co-processor operations with multi-threaded processing operations and improved cache affinity.
摘要翻译：网络处理器具有许多新颖的特征，包括多线程处理器阵列，多遍处理模型和具有硬件管理分组存储的全局分组存储器（GPM）。这些独特的功能允许网络处理器以高数据速率执行高触摸数据包处理。分组处理器也可以使用基于堆栈的高级编程语言（例如C或C ++）进行编码。这样可以更快速地将软件功能移植到网络处理器中。当添加额外的处理功能时，处理器性能也不会严重下降。例如，可以通过将处理元素分配给不同的有界持续时间到达处理任务和可变持续时间主处理任务来更智能地处理分组。再循环路径在不同的到达和主要处理任务之间移动分组。其他新颖的硬件功能包括硬件架构，可以将协处理器操作与多线程处理操作高效地混合，并提高缓存关联度。

2. 发明授权

US06065113A Circuits, systems, and methods for uniquely identifying a microprocessor at the instruction set level employing one-time programmable register 失效
标题翻译：用于使用一次性可编程寄存器在指令集级别唯一标识微处理器的电路，系统和方法
公开(公告)号：US06065113A
公开(公告)日：2000-05-16
申请号：US813887
申请日：1997-03-07
申请人： Jonathan H. Shiell , Joel J. Graber , Donald E. Steiss
发明人： Jonathan H. Shiell , Joel J. Graber , Donald E. Steiss
IPC分类号： G06F1/00 , G06F9/30 , G06F11/00 , G06F9/00
CPC分类号： G06F9/3017 , G06F11/006 , G06F9/30003
摘要： In a method embodiment (10), the method operates a microprocessor (110), and the microprocessor has an instruction set. The method first (11) stores an identifier code uniquely identifying the particular microprocessor in a one-time programmable register. The method second (12) issues to the microprocessor an identifier request instruction from the instruction set. The method then, and in response to the identifier request instruction, provides (18) from the microprocessor an identifier code. Other circuits, systems, and methods are also disclosed and claimed.
摘要翻译：在方法实施例（10）中，该方法操作微处理器（110），并且微处理器具有指令集。方法第一（11）将唯一地标识特定微处理器的识别码存储在一次性可编程寄存器中。方法二（12）向微处理器发出来自指令集的标识符请求指令。该方法然后响应于标识符请求指令，从微处理器提供（18）标识符代码。还公开并要求保护其他电路，系统和方法。

3. 发明授权

US5850543A Microprocessor with speculative instruction pipelining storing a speculative register value within branch target buffer for use in speculatively executing instructions after a return 失效
标题翻译：具有推测性指令流水线的微处理器，在分支目标缓冲区中存储推测寄存器值，用于在返回后推测执行指令
公开(公告)号：US5850543A
公开(公告)日：1998-12-15
申请号：US741878
申请日：1996-10-30
申请人： Jonathan H. Shiell , Donald E. Steiss
发明人： Jonathan H. Shiell , Donald E. Steiss
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/3842
摘要： A microprocessor of the superscalar pipelined type, having speculative execution capability, is disclosed. Speculative execution is under the control of a fetch unit having a branch target buffer and a return address stack, each having multiple entries. Each entry includes an address value corresponding to the destination of a branching instruction, and an associated register value, such as a stack pointer. Upon the execution of a subroutine call, the return address and current stack pointer value are stored in the return address stack, to allow for fetching and speculative execution of the sequential instructions following the call in the calling program. Any branching instruction, such as the call, return, or conditional branch, will have an entry included in the branch target buffer; upon fetch of the branch on later passes, speculative execution from the target address can begin using the stack pointer value stored speculatively in the branch target buffer in association with the target address.
摘要翻译：公开了具有推测执行能力的超标量流水线型微处理器。推测执行在具有分支目标缓冲器和返回地址堆栈的获取单元的控制下，每个具有多个条目。每个条目包括与分支指令的目的地相对应的地址值和相关联的寄存器值，诸如堆栈指针。在执行子程序调用时，返回地址和当前堆栈指针值存储在返回地址堆栈中，以允许在调用程序中的调用之后提取和推测执行顺序指令。任何分支指令（如调用，返回或条件分支）将具有包含在分支目标缓冲区中的条目; 在稍后通过分支提取时，从目标地址的推测执行可以开始使用与目标地址相关联的分支目标缓冲器中的推测性地存储的堆栈指针值。

4. 发明授权

US5047973A High speed numerical processor for performing a plurality of numeric functions 失效
标题翻译：用于执行多个数字功能的高速数字处理器
公开(公告)号：US5047973A
公开(公告)日：1991-09-10
申请号：US343465
申请日：1989-04-26
申请人： Donald E. Steiss , Maria B. Hipona , Henry M. Darley
发明人： Donald E. Steiss , Maria B. Hipona , Henry M. Darley
IPC分类号： G06F7/537 , G06F7/52 , G06F7/53 , G06F7/535 , G06F7/552 , G06F7/57
CPC分类号： G06F7/5324 , G06F7/535 , G06F7/5525 , G06F7/57 , G06F2207/382 , G06F2207/5355
摘要： Division and square root calculations are performed using an operand routing circuit (16) for receiving an operand N, and operand D and a seed value S and directing the operands and seed value to a multiplier (38). Single multiplier (38) is configured into two arrays for calculating partial products of N and S and D and S. The results of multiplier (38) are transmitted through switching circuitry (20) or registers (48) (50) either to operand routing circuitry (16) or adder (44) depending on a convergence algorithm. The final result is rounded.

5. 发明申请

US20090106523A1 TRANSLATION LOOK-ASIDE BUFFER WITH VARIABLE PAGE SIZES 有权
标题翻译：翻译看起来像可变页尺寸的缓冲区
公开(公告)号：US20090106523A1
公开(公告)日：2009-04-23
申请号：US11874866
申请日：2007-10-18
申请人： Donald E. Steiss
发明人： Donald E. Steiss
IPC分类号： G06F12/02
CPC分类号： G06F12/1036 , G06F2212/652 , Y02D10/13
摘要： Multiple pipelined Translation Look-aside Buffer (TLB) units are configured to compare a translation address with associated TLB entries. The TLB units operated in serial order comparing the translation address with associated TLB entries until an identified one of the TLB units produces a hit. The TLB units following the TLB unit producing the hit might be disabled.
摘要翻译：多个流水线翻译后备缓冲器（TLB）单元被配置为将翻译地址与相关联的TLB条目进行比较。 TLB单元以串行顺序操作，将翻译地址与相关联的TLB条目进行比较，直到所识别的一个TLB单元产生命中。遵循TLB单元产生命中的TLB单元可能会被禁用。

6. 发明授权

US06895494B1 Sub-pipelined and pipelined execution in a VLIW 有权
标题翻译：在VLIW中进行子流水线和流水线执行
公开(公告)号：US06895494B1
公开(公告)日：2005-05-17
申请号：US09603226
申请日：2000-06-26
申请人： Donald E. Steiss , Laurence Ray Simar, Jr.
发明人： Donald E. Steiss , Laurence Ray Simar, Jr.
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F15/00
CPC分类号： G06F9/30174 , G06F9/30196 , G06F9/3822 , G06F9/3853
摘要： A subpipelined translation embodiment provides binary compatibility between current an future generations of DSPs. When retrieved from memory an entire fetch packet is assigned an operating mode (base instruction set or migrant instruction set) according to the current execution mode. The fetch packets from the instruction memory are parsed into execute packets and sorted by execution unit (dispatched) in a datapath shared by both execution modes (base and migrant). The two execution modes have separate control logic. Instructions from the dispatch datapath are decoded by either base architecture decode logic or the migrant architecture decode logic, depending on the execution mode bound to the parent fetch packet. Code processed by the migrant and base decode pipelines produces machine words that are selected by a multiplexer. The multiplexer is controlled by the operating mode bound to the fetch packet that produced the machine word. The selected machine word controls a global register file, which supplies operands to all hardware execution units and accepts results of all hardware execution units.
摘要翻译：辅助翻译实施例提供了当前未来几代DSP之间的二进制兼容性。当根据当前的执行模式从存储器检索到整个获取数据包的操作模式（基本指令集或迁移指令集）。来自指令存储器的获取数据包被解析为执行数据包，并由执行单元（分派）按照两个执行模式（基础和移植）共享的数据路径进行排序。这两种执行模式具有单独的控制逻辑。根据绑定到父提取数据包的执行模式，调度数据路径的指令由基础架构解码逻辑或移植体架构解码逻辑进行解码。由移动和基本解码管线处理的代码产生由多路复用器选择的机器字。多路复用器由绑定到产生机器字的提取数据包的操作模式控制。所选的机器字控制一个全局寄存器文件，其向所有硬件执行单元提供操作数，并接受所有硬件执行单元的结果。

7. 发明授权

US06781411B2 Flip flop with reduced leakage current 有权
标题翻译：触发器具有减少的漏电流
公开(公告)号：US06781411B2
公开(公告)日：2004-08-24
申请号：US10256302
申请日：2002-09-27
申请人： Donald E. Steiss , Clive Bittlestone , Peter Cumming , Christopher Barr
发明人： Donald E. Steiss , Clive Bittlestone , Peter Cumming , Christopher Barr
IPC分类号： H03K19173
CPC分类号： H03K3/012 , H03K3/35625 , H03K17/693
摘要： A flip flop (30) comprising a master stage (34) comprising a first plurality of transistors (54, 56), wherein each of the first plurality of transistors comprises a selective conductive path between a source and drain. The flip flop also comprises a slave stage (42) comprising a second plurality of transistors (60, 62, 64, 66), wherein each of the second plurality of transistors comprises a selective conductive path between a source and drain. For the flip flop, in a low power mode the flip flop is operable to receive a first voltage (VDD) coupled to the selective conductive path for each of the first plurality of transistors. Also in the low power mode, the flip flop is operable to receive a second voltage (VDDL) coupled to the selective conductive path for each of the second plurality of transistors. Lastly, the second voltage is greater than the first voltage in the low power mode.
摘要翻译：一种触发器（30），包括包括第一多个晶体管（54,56）的主级（34），其中所述第一多个晶体管中的每一个包括在源极和漏极之间的选择性导电路径。触发器还包括由第二多个晶体管（60,62,64,66）组成的从级（42），其中第二多个晶体管中的每一个包括在源极和漏极之间的选择性导电路径。对于触发器，在低功率模式下，触发器可操作以接收耦合到第一多个晶体管中的每一个的选择导电路径的第一电压（VDD）。同样在低功率模式下，触发器可操作以接收耦合到第二多个晶体管中的每一个的选择性导电路径的第二电压（VDDL）。最后，第二电压大于低功率模式下的第一电压。

8. 发明授权

US07441101B1 Thread-aware instruction fetching in a multithreaded embedded processor 有权
标题翻译：线程感知指令在多线程嵌入式处理器中获取
公开(公告)号：US07441101B1
公开(公告)日：2008-10-21
申请号：US10773385
申请日：2004-02-05
申请人： Donald E. Steiss , Earl T Cohen , John J Williams, Jr.
发明人： Donald E. Steiss , Earl T Cohen , John J Williams, Jr.
IPC分类号： G06F9/312 , G06F9/48
CPC分类号： G06F9/3851 , G06F9/3802
摘要： The present invention provides a multithreaded processor, such as a network processor, that fetches instructions in a pipeline stage based on feedback signals from later stages. The multithreaded processor comprises a pipeline with an instruction unit in the early stage and an instruction queue, a thread interleaver, and an execution pipeline in the later stages. Feedback signals from the later stages cause the instruction unit to block fetching, immediately fetch, raise priority, or lower priority for a particular thread. The instruction queue generates a queue signal, on a per thread basis, responsive to a thread queue condition, etc., the thread interleaver generates an interleaver signal responsive to a thread condition, etc., and the execution pipeline generates an execution signal responsive to an execution stall, etc.
摘要翻译：本发明提供了一种多线程处理器，例如网络处理器，其基于来自后期阶段的反馈信号在流水线级中取指令。多线程处理器包括在早期阶段具有指令单元的流水线以及稍后阶段中的指令队列，线程交织器和执行流水线。来自后期的反馈信号导致指令单元阻止特定线程的取出，立即获取，提高优先级或降低优先级。指令队列响应于线程队列条件等而在每个线程的基础上生成队列信号，线程交织器响应于线程状态等产生交织器信号，并且执行流水线生成响应于执行档等

9. 发明授权

US06567906B2 Secure computing device including virtual memory table look-aside buffer with non-relocatable page of memory 有权
标题翻译：安全计算设备包括具有不可重定位页面的内存的虚拟内存表查看缓冲区
公开(公告)号：US06567906B2
公开(公告)日：2003-05-20
申请号：US09827851
申请日：2001-04-06
申请人： Frank L. Laczko, Sr. , Donald E. Steiss
发明人： Frank L. Laczko, Sr. , Donald E. Steiss
IPC分类号： G06F1200
CPC分类号： G06F21/64 , G06F12/145 , G06F21/51 , G06F21/575 , G06F2207/7219 , G06F2211/008 , G06F2211/1097
摘要： A diagnostic program can check the security of a program. The program is stored at predetermined non-relocatable physical address in memory. The diagnostic program is loaded and checks the program at the predetermined physical address against a standard. The diagnostic program then indicates that the program is verified as secure if it meets the standard or non-verified as secure if it does not meet the standard. If the program is not verified as secure, then the diagnostic program may take remedial action such as disabling normal operation of the program, be transmitting a predetermined message via the system modem or downloading another copy of the program via the modem. The program is made non-relocatable using a special table look-aside buffer having a fixed virtual address register and a corresponding fixed physical address register.
摘要翻译：诊断程序可以检查程序的安全性。程序存储在存储器中预定的不可重定位的物理地址。加载诊断程序并按照标准检查预定物理地址的程序。然后，诊断程序指示如果程序符合标准或未验证为安全（如果不符合标准），则该程序被证实为安全的。如果程序未被证实为安全的，则诊断程序可以采取补救措施，例如禁用程序的正常操作，通过系统调制解调器发送预定的消息，或通过调制解调器下载程序的另一个副本。使用具有固定虚拟地址寄存器和对应的固定物理地址寄存器的特殊表格后备缓冲器使该程序不可重定位。

10. 发明授权

US06539467B1 Microprocessor with non-aligned memory access 有权
标题翻译：具有非对齐内存访问的微处理器
公开(公告)号：US06539467B1
公开(公告)日：2003-03-25
申请号：US09703105
申请日：2000-10-31
申请人： Timothy D. Anderson , David Hoyle , Donald E. Steiss , Steven D. Krueger
发明人： Timothy D. Anderson , David Hoyle , Donald E. Steiss , Steven D. Krueger
IPC分类号： G06F1200
CPC分类号： G06F9/3891 , G06F9/30014 , G06F9/30036 , G06F9/30043 , G06F9/30105 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/30145 , G06F9/30167 , G06F9/3552 , G06F9/3555 , G06F9/3816 , G06F9/3824 , G06F9/3828 , G06F9/3853 , G06F9/3885
摘要： A data processing system (1300) is provided with a digital signal processor (DSP) (1301) that has an instruction set architecture (ISA) that is optimized for intensive numeric algorithm processing. The DSP has dual load/store units (.D1, .D2) connected to dual memory ports (T1, T2) in a level one data cache memory controller (1720a). The DSP can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The DSP can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory target ports.
摘要翻译：数据处理系统（1300）具有数字信号处理器（DSP）（1301），该数字信号处理器（1301）具有针对密集数字算法处理而被优化的指令集架构（ISA）。 DSP具有连接到一级数据高速缓冲存储器控制器（1720a）中的双存储器端口（T1，T2）的双重加载/存储单元（.D1，.D2）。 DSP可以通过执行两个加载/存储指令来并行执行两个对齐的数据传输，每个数据传输具有一个字节，两个字节，四个字节或八个字节的长度。 DSP还可以通过执行利用两个存储器目标端口的不对齐加载/存储指令来执行具有四字节或八字节长度的单个非对齐数据传输。

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