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1. 发明授权

US06065113A Circuits, systems, and methods for uniquely identifying a microprocessor at the instruction set level employing one-time programmable register 失效
标题翻译：用于使用一次性可编程寄存器在指令集级别唯一标识微处理器的电路，系统和方法
公开(公告)号：US06065113A
公开(公告)日：2000-05-16
申请号：US813887
申请日：1997-03-07
申请人： Jonathan H. Shiell , Joel J. Graber , Donald E. Steiss
发明人： Jonathan H. Shiell , Joel J. Graber , Donald E. Steiss
IPC分类号： G06F1/00 , G06F9/30 , G06F11/00 , G06F9/00
CPC分类号： G06F9/3017 , G06F11/006 , G06F9/30003
摘要： In a method embodiment (10), the method operates a microprocessor (110), and the microprocessor has an instruction set. The method first (11) stores an identifier code uniquely identifying the particular microprocessor in a one-time programmable register. The method second (12) issues to the microprocessor an identifier request instruction from the instruction set. The method then, and in response to the identifier request instruction, provides (18) from the microprocessor an identifier code. Other circuits, systems, and methods are also disclosed and claimed.
摘要翻译：在方法实施例（10）中，该方法操作微处理器（110），并且微处理器具有指令集。方法第一（11）将唯一地标识特定微处理器的识别码存储在一次性可编程寄存器中。方法二（12）向微处理器发出来自指令集的标识符请求指令。该方法然后响应于标识符请求指令，从微处理器提供（18）标识符代码。还公开并要求保护其他电路，系统和方法。

2. 发明授权

US6061811A Circuits, systems, and methods for external evaluation of microprocessor built-in self-test 失效
标题翻译：微处理器内置自检外部评估的电路，系统和方法
公开(公告)号：US6061811A
公开(公告)日：2000-05-09
申请号：US961788
申请日：1997-10-31
申请人： James O. Bondi , Joel J. Graber , Donald E. Steiss , John M. Johnsen
发明人： James O. Bondi , Joel J. Graber , Donald E. Steiss , John M. Johnsen
IPC分类号： G06F11/267 , G06F11/00
CPC分类号： G06F11/2236
摘要： A microprocessor (10) operating in response to a clock signal (CLK) having a clock period. The microprocessor includes a readable memory (16), and this readable memory stores code (BIST) for performing diagnostic evaluations of the microprocessor. The diagnostic evaluations include a first evaluation to occur under non-failure operation at a first clock period (24) and a last evaluation to occur under non-failure operation at a last clock period (26). The microprocessor further includes circuitry (14) for issuing a series of addresses to the readable memory in order to address the code for performing diagnostic evaluations of the microprocessor. Still further, the microprocessor includes a conductor (D0) externally accessible and for providing a signal from the microprocessor. Lastly, the microprocessor includes circuitry (12) for outputting a diagnostic signal on the externally accessible conductor during performance of the diagnostic evaluations. Given the externally accessible conductor, divergence of the diagnostic signal from a predetermined pattern before the last dock period indicates a failure of the diagnostic evaluations before the last clock period.
摘要翻译：响应于具有时钟周期的时钟信号（CLK）工作的微处理器（10）。微处理器包括可读存储器（16），并且该可读存储器存储用于执行微处理器的诊断评估的代码（BIST）。诊断评估包括在第一时钟周期（24）的非故障操作下进行的第一评估，以及在最后时钟周期（26）的非故障操作下发生的最后评估。微处理器还包括用于向可读存储器发出一系列地址以便寻址用于执行微处理器的诊断评估的代码的电路（14）。此外，微处理器包括外部可访问的导体（D0），用于提供来自微处理器的信号。最后，微处理器包括用于在执行诊断评估期间在外部可访问的导体上输出诊断信号的电路（12）。给定外部可访问的导体，诊断信号在最后一个停靠期之前的预定模式的发散指示在最后时钟周期之前的诊断评估失败。

3. 发明申请

US20120204072A1 LOW POWER SCAN & DELAY TEST METHOD AND APPARATUS 有权
标题翻译：低功耗扫描和延迟测试方法和设备
公开(公告)号：US20120204072A1
公开(公告)日：2012-08-09
申请号：US13453501
申请日：2012-04-23
申请人： Lee D. Whetsel , Joel J. Graber
发明人： Lee D. Whetsel , Joel J. Graber
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318544 , G01R31/31721 , G01R31/3177 , G01R31/318541 , G01R31/318547 , G01R31/318575 , G01R31/31858 , G01R31/318586
摘要： Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.
摘要翻译：扫描和扫描BIST架构通常用于测试集成电路中的数字电路。本公开改进了低功率扫描和扫描BIST方法。该改进允许低功耗扫描和扫描BIST架构实现与传统扫描和Scan-BIST架构中使用的延迟测试功能一样有效的延迟测试功能。

4. 发明授权

US06928011B2 Electrical fuse control of memory slowdown 有权
标题翻译：电熔丝控制内存减速
公开(公告)号：US06928011B2
公开(公告)日：2005-08-09
申请号：US10630963
申请日：2003-07-30
申请人： Manjeri Krishnan , Bryan Sheffield , Joel J. Graber , Duy-Loan Le , Sanjive Agarwala
发明人： Manjeri Krishnan , Bryan Sheffield , Joel J. Graber , Duy-Loan Le , Sanjive Agarwala
IPC分类号： G11C29/50 , G11C29/00
CPC分类号： G11C29/027 , G11C29/028 , G11C29/50 , G11C29/50012
摘要： Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse techniques by not requiring an additional processing step and expensive equipment. Standard electrical fuse (eFuse) hardware chains provide a soft test feature wherein the effect of memory slow-down can be tested prior to actually programming the fuses. Electrical fuses thus provide a very efficient non-volatile method to match the logic-memory interface through memory trimming, drastically cutting costs and cycle times involved.
摘要翻译：电气保险丝（eFuse）被应用于存储器性能调整的任务，以通过不需要额外的处理步骤和昂贵的设备来改进早期保险丝技术。标准电熔丝（eFuse）硬件链提供了软测试功能，其中可以在实际编程保险丝之前测试存储器减速的影响。因此，电熔丝提供非常有效的非易失性方法，以通过存储器修整来匹配逻辑存储器接口，大大降低成本和所涉及的周期时间。

5. 发明授权

US06898749B2 IC with cache bit memory in series with scan segment 有权
标题翻译： IC与缓存位存储器与扫描段串联
公开(公告)号：US06898749B2
公开(公告)日：2005-05-24
申请号：US09955542
申请日：2001-09-18
申请人： Lee D. Whetsel , Joel J. Graber
发明人： Lee D. Whetsel , Joel J. Graber
IPC分类号： G01R31/317 , G01R31/3185 , G01R31/28
CPC分类号： G01R31/318544 , G01R31/31721 , G01R31/3177 , G01R31/318541 , G01R31/318547 , G01R31/318575 , G01R31/31858 , G01R31/318586
摘要： Low power delay test capabilities in Scan and Scan-BIST architectures occur by inserting a first cache bit memory between the scan input lead and the serial input to a first scan path segment. When the first segment is serially loaded, the last test bit remains in the first cache bit memory. When a last scan path segment is serially loaded and when the last bit is loaded into the last scan path segment, the last bit in the first cache bit memory is simultaneously loaded into the first scan path segment. This presents the desired stimulus signals to the logic circuits. The next clock signal to the scan path segments then captures the response from the logic circuits.
摘要翻译：扫描和扫描BIST架构中的低功耗延迟测试功能是通过将扫描输入引线和串行输入之间的第一个高速缓存位存储器插入到第一个扫描路径段来实现的。当第一段被串行加载时，最后一个测试位保留在第一个高速缓存位存储器中。当最后一个扫描路径段被串行加载，并且当最后一个位被加载到最后一个扫描路径段时，第一个高速缓存位存储器中的最后一位被同时加载到第一个扫描路径段中。这向逻辑电路呈现所需的刺激信号。到扫描路径段的下一个时钟信号然后捕获来自逻辑电路的响应。

6. 发明授权

US07795918B2 Adjusting output buffer timing based on drive strength 有权
标题翻译：根据驱动强度调整输出缓冲时序
公开(公告)号：US07795918B2
公开(公告)日：2010-09-14
申请号：US11839872
申请日：2007-08-16
申请人： Joel J. Graber
发明人： Joel J. Graber
IPC分类号： H03K19/094
CPC分类号： H03K19/00384 , H03K19/00376
摘要： This invention operates to select a drive code for an adjustable drive strength transistor in a drive buffer. The drive code is determined employing a scaled-down drive transistor employing varying drive codes compared with a standard. The thus determined drive code is combined with an offset to generate the drive code for the adjustable strength transistor.
摘要翻译：本发明操作以选择用于驱动缓冲器中的可调驱动强度晶体管的驱动代码。使用与标准相比采用变化的驱动代码的按比例缩小的驱动晶体管来确定驱动代码。将如此确定的驱动代码与偏移相组合以产生可调强度晶体管的驱动代码。

7. 发明申请

US20080320351A1 LOW POWER SCAN & DELAY TEST METHOD AND APPARATUS 有权
标题翻译：低功耗扫描和延迟测试方法和设备
公开(公告)号：US20080320351A1
公开(公告)日：2008-12-25
申请号：US12204267
申请日：2008-09-04
申请人： Lee D. Whetsel , Joel J. Graber
发明人： Lee D. Whetsel , Joel J. Graber
IPC分类号： G01R31/3177 , G06F11/00
CPC分类号： G01R31/318544 , G01R31/31721 , G01R31/3177 , G01R31/318541 , G01R31/318547 , G01R31/318575 , G01R31/31858 , G01R31/318586
摘要： Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.
摘要翻译：扫描和扫描BIST架构通常用于测试集成电路中的数字电路。本公开改进了低功率扫描和扫描BIST方法。该改进允许低功耗扫描和扫描BIST架构实现与传统扫描和Scan-BIST架构中使用的延迟测试功能一样有效的延迟测试功能。

8. 发明授权

US07095671B2 Electrical fuse control of memory slowdown 有权
标题翻译：电熔丝控制内存减速
公开(公告)号：US07095671B2
公开(公告)日：2006-08-22
申请号：US11121387
申请日：2005-05-03
申请人： Manjeri Krishnan , Bryan Sheffield , Joel J. Graber , Duy-Loan Le , Sanjive Agarwala
发明人： Manjeri Krishnan , Bryan Sheffield , Joel J. Graber , Duy-Loan Le , Sanjive Agarwala
IPC分类号： G11C7/00
CPC分类号： G11C29/027 , G11C29/028 , G11C29/50 , G11C29/50012
摘要： Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse techniques by not requiring an additional processing step and expensive equipment. Standard electrical fuse (eFuse) hardware chains provide a soft test feature wherein the effect of memory slow-down can be tested prior to actually programming the fuses. Electrical fuses thus provide a very efficient non-volatile method to match the logic-memory interface through memory trimming, drastically cutting costs and cycle times involved.
摘要翻译：电气保险丝（eFuse）被应用于存储器性能调整的任务，以通过不需要额外的处理步骤和昂贵的设备来改进早期保险丝技术。标准电熔丝（eFuse）硬件链提供了软测试功能，其中可以在实际编程保险丝之前测试存储器减速的影响。因此，电熔丝提供非常有效的非易失性方法，以通过存储器修整来匹配逻辑存储器接口，大大降低成本和所涉及的周期时间。

9. 发明授权

US08185789B2 Capturing response after simultaneously inputting last stimulus bit in scan path subdivisions 有权
标题翻译：同时在扫描路径细分中输入最后一个激励位时捕获响应
公开(公告)号：US08185789B2
公开(公告)日：2012-05-22
申请号：US13198365
申请日：2011-08-04
申请人： Lee D. Whetsel , Joel J. Graber
发明人： Lee D. Whetsel , Joel J. Graber
IPC分类号： G01R31/28
CPC分类号： G01R31/318544 , G01R31/31721 , G01R31/3177 , G01R31/318541 , G01R31/318547 , G01R31/318575 , G01R31/31858 , G01R31/318586
摘要： Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.
摘要翻译：扫描和扫描BIST架构通常用于测试集成电路中的数字电路。本公开改进了低功率扫描和扫描BIST方法。该改进允许低功耗扫描和扫描BIST架构实现与传统扫描和Scan-BIST架构中使用的延迟测试功能一样有效的延迟测试功能。

10. 发明授权

US08015464B2 Segmented scan paths with cache bit memory inputs 有权
标题翻译：具有缓存位存储器输入的分段扫描路径
公开(公告)号：US08015464B2
公开(公告)日：2011-09-06
申请号：US12204267
申请日：2008-09-04
申请人： Lee D. Whetsel , Joel J. Graber
发明人： Lee D. Whetsel , Joel J. Graber
IPC分类号： G01R31/28
CPC分类号： G01R31/318544 , G01R31/31721 , G01R31/3177 , G01R31/318541 , G01R31/318547 , G01R31/318575 , G01R31/31858 , G01R31/318586
摘要： Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.
摘要翻译：扫描和扫描BIST架构通常用于测试集成电路中的数字电路。本公开改进了低功率扫描和扫描BIST方法。该改进允许低功耗扫描和扫描BIST架构实现与传统扫描和Scan-BIST架构中使用的延迟测试功能一样有效的延迟测试功能。

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