专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06401212B1 Microprocessor circuits, systems, and methods for conditioning information prefetching based on resource burden 有权
标题翻译：基于资源负担来调节信息预取的微处理器电路，系统和方法
公开(公告)号：US06401212B1
公开(公告)日：2002-06-04
申请号：US09708299
申请日：2000-11-08
申请人： James O. Bondi , Jonathan H. Shiell
发明人： James O. Bondi , Jonathan H. Shiell
IPC分类号： G06F132
CPC分类号： G06F12/0862 , G06F9/3824
摘要： In a computer system (10) embodiment, there is included a memory (18) and circuitry (16a) for prefetching information from the memory in response to a prefetch request. The system further includes a system resource (14), wherein the system resource is burdened in response to a prefetch operation by the circuitry for prefetching information. The system resource is also further burdened in response to other circuitry (16b, 16n, 17) using the system resource. The system further includes circuitry (20, 22, 24) for determining a measure of the burden on the system resource. Lastly, the system includes circuitry (26) for prohibiting prefetching of the information by the circuitry for prefetching information responsive to a comparison of the measure of the burden with a threshold. Other circuits, systems, and methods are also disclosed and claimed.
摘要翻译：在计算机系统（10）实施例中，包括用于响应于预取请求从存储器预取信息的存储器（18）和电路（16a）。系统还包括系统资源（14），其中系统资源响应于用于预取信息的电路的预取操作而负担。响应于使用系统资源的其它电路（16b，16n，17），系统资源也进一步负担。该系统还包括用于确定系统资源负担的度量的电路（20,22,24）。最后，该系统包括电路（26），用于响应于负担测量与阈值的比较，禁止通过电路预取信息以预取信息。还公开并要求保护其他电路，系统和方法。

2. 发明授权

US06338137B1 Data processor having memory access unit with predetermined number of instruction cycles between activation and initial data transfer 有权
标题翻译：数据处理器具有在激活和初始数据传送之间具有预定数目的指令周期的存储器存取单元
公开(公告)号：US06338137B1
公开(公告)日：2002-01-08
申请号：US09314763
申请日：1999-05-19
申请人： Jonathan H. Shiell , Patrick W. Bosshart
发明人： Jonathan H. Shiell , Patrick W. Bosshart
IPC分类号： G06F9312
CPC分类号： G06F9/325 , G06F9/30043 , G06F9/30072 , G06F9/3873
摘要： A multiple cycle memory access unit issues a memory access load or store, delaying a predetermined number of instruction cycles between it activation and its initial data transfer. The multiple cycle memory access unit controls a predetermined plural number of accesses and operates independently and in parallel with the instruction flow of the data processor. The multiple cycle memory access unit delays a predetermined number of instruction cycles between sequential data transfers of the predetermined number of data transfers. This predetermined period may be the same as the initial delay or it may be determined independent of the initial delay. The operation of the multiple cycle memory access unit is subject to predication on an instruction specified data registers. The multiple cycle memory access unit preferably provides predetermined register number cycling among the plural data registers. The multiple cycle memory access unit preferably aborts operation, stops and saves its internal state on a predetermined event.
摘要翻译：多周期存储器访问单元发出存储器访问负载或存储，延迟其激活和其初始数据传输之间的预定数量的指令周期。多周期存储器访问单元控制预定的多个访问，并且与数据处理器的指令流独立地并行操作。多周期存储器访问单元在预定数量的数据传输的顺序数据传送之间延迟预定数量的指令周期。该预定周期可以与初始延迟相同，或者可以独立于初始延迟来确定。多周期存储器访问单元的操作可以对指令指定的数据寄存器进行预测。多周期存储器访问单元优选地在多个数据寄存器之间提供预定的寄存器数循环。多周期存储器访问单元优选地中止操作，停止并将其内部状态保存在预定事件上。

3. 发明授权

US6085269A Configurable expansion bus controller in a microprocessor-based system 失效
标题翻译：基于微处理器的系统中可配置的扩展总线控制器
公开(公告)号：US6085269A
公开(公告)日：2000-07-04
申请号：US961789
申请日：1997-10-31
申请人： Tai-Yuen Chan , Steven D. Krueger , Jonathan H. Shiell
发明人： Tai-Yuen Chan , Steven D. Krueger , Jonathan H. Shiell
IPC分类号： G06F13/36 , G06F13/38 , G06F13/40 , G06F1/00
CPC分类号： G06F13/385 , G06F13/4018
摘要： A host module (2) including a host CPU (10) and a configurable expansion bus controller (28, 28', 128) is disclosed. The expansion bus controller (28, 28', 128) is configurable by way of configuration signals (BCFG) to be operable in various bus configurations for communicating signals between a module bus (IBUS) and external buses (XPCI1, XPCI0). These modes include combining the external buses (XPCI1, XPCI0) into a single bus of the 64-bit PCI type, operating the external buses (XPCI1, XPCI0) as separate 32-bit PCI buses, as separate CardBus buses, as separate AGP buses (either at one or multiple data transfers per cycle), or as combinations thereof. Certain of the configuration signals (BCFG) are used to select the clock frequencies at which the external buses (XPCI1, XPCI0) operate, in either of the 64-bit or 32-bit PCI protocols, or in the AGP bus protocol when present. The external buses (XPCI1, XPCI0) may be operable at different speeds, and at different protocols, depending upon the state of the configuration signals (BCFG).
摘要翻译：公开了一种包括主机CPU（10）和可配置扩展总线控制器（28,28'，128）的主机模块（2）。扩展总线控制器（28,28'，128）可通过配置信号（BCFG）进行配置，以在各种总线配置中可操作，用于在模块总线（IBUS）和外部总线（XPCI1，XPCI0）之间传送信号。这些模式包括将外部总线（XPCI1，XPCI0）组合为64位PCI类型的单总线，将外部总线（XPCI1，XPCI0）作为单独的32位PCI总线作为单独的CardBus总线，作为单独的AGP总线（每个循环一次或多次数据传输），或作为其组合。某些配置信号（BCFG）用于选择外部总线（XPCI1，XPCI0）在64位或32位PCI协议中的任何时钟或AGP总线协议中存在的时钟频率。根据配置信号（BCFG）的状态，外部总线（XPCI1，XPCI0）可以以不同的速度和不同的协议操作。

4. 发明授权

US6064254A High speed integrated circuit interconnection having proximally located active converter 失效
标题翻译：具有近端定位的有源转换器的高速集成电路互连
公开(公告)号：US6064254A
公开(公告)日：2000-05-16
申请号：US691
申请日：1997-12-30
申请人： Wilbur C. Vogley , Jonathan H. Shiell
发明人： Wilbur C. Vogley , Jonathan H. Shiell
IPC分类号： H05K7/10 , H01L25/00
CPC分类号： H05K7/1092
摘要： An active integrated circuit socket includes plural pin sockets receiving corresponding pins of an integrated circuit and plural socket pins making electrical contact with a printed circuit board. At least one active electronic component requiring electrical power for operation connects a pin sockets to a corresponding socket pin. The active electronic component may be a single ended input to differential output driver, a differential input to single ended output driver, a single ended to differential input/output transceiver or a voltage level shifter. These active components may include passive termination resistors. The single ended to differential transceiver may further include an enable input determining the direction of data transmission. This invention may be employed as an electronic system upgrade product including at least two active integrated circuit sockets connected via a flexible sheet including a plurality of electrical conductors connecting differential signal lines. The flexible sheet may dispose a grounded conductor between each pair of differential signal conductors. The differential signals on the printed circuit board or the flexible sheet enabled by this invention are better able to support high speed data transfer than the single ended signals at the pins of the integrated circuits.
摘要翻译：有源集成电路插座包括接收集成电路的相应引脚的多个引脚插座和与印刷电路板电接触的多个插座引脚。至少一个需要用于操作电力的有源电子部件将销插座连接到相应的插座销。有源电子部件可以是单端输入到差分输出驱动器，差分输入到单端输出驱动器，单端到差分输入/输出收发器或电压电平转换器。这些有源部件可以包括无源终端电阻器。单端到差分收发器还可以包括确定数据传输方向的使能输入。本发明可以用作电子系统升级产品，其包括通过柔性片连接的至少两个有源集成电路插座，所述柔性片包括连接差分信号线的多个电导体。柔性片材可以在每对差分信号导体之间设置接地导体。通过本发明实现的印刷电路板或柔性片上的差分信号比集成电路引脚上的单端信号更能够支持高速数据传输。

5. 发明授权

US06032225A Microprocessor system with burstable, non-cacheable memory access support 失效
标题翻译：微处理器系统具有可突发，不可缓存的内存访问支持
公开(公告)号：US06032225A
公开(公告)日：2000-02-29
申请号：US769194
申请日：1996-12-18
申请人： Jonathan H. Shiell , Ashwini K. Nanda , Ian Chen , Steven D. Krueger
发明人： Jonathan H. Shiell , Ashwini K. Nanda , Ian Chen , Steven D. Krueger
IPC分类号： G06F12/08 , G06F13/28 , G06F12/00
CPC分类号： G06F13/28 , G06F12/0888
摘要： A microprocessor-based system (2) is disclosed, based on an x86-architecture microprocessor (5). The system includes a memory address space (30) and a input/output address space (40), where input/output operations are performed in an I/O mapped manner. According to a first embodiment of the invention, burstable access is performed to areas of the main memory (32) which are blocked from cache access, by the microprocessor (5) asserting the cache request signal (CACHE#) in combination with the control signal (M/IO#) indicating that an I/O operation is requested. The memory controller (10) interprets this combination as a burst request to the non-cacheable memory location (32), indicates the grant of burst access by asserting the cache acknowledge control signal (KEN#), and the burst memory access is then effected. According to a second embodiment of the invention, burst access to non-cacheable memory space (32) is acknowledged by the memory controller (60) by way of a burst acknowledge signal (BEN#) that is separate from the cache acknowledgment signal (KEN#).
摘要翻译：基于x86架构的微处理器（5）公开了一种基于微处理器的系统（2）。该系统包括存储器地址空间（30）和输入/输出地址空间（40），其中以I / O映射方式执行输入/输出操作。根据本发明的第一实施例，微处理器（5）结合控制信号来确定高速缓存请求信号（CACHE＃），对主存储器（32）的被高速缓存访问阻止的区域执行突发存取（M / IO＃），表示请求I / O操作。存储器控制器（10）将该组合解释为对非可缓存存储器位置（32）的突发请求，指示通过断言高速缓存确认控制信号（KEN＃）来准许突发存取，然后实现突发存储器访问。根据本发明的第二实施例，通过与高速缓存确认信号（KEN）分离的突发确认信号（BEN＃），由存储器控制器（60）确认对非可缓存存储器空间（32）的突发访问＃）。

6. 发明授权

US5953512A Microprocessor circuits, systems, and methods implementing a loop and/or stride predicting load target buffer 失效
标题翻译：实现循环和/或步幅预测负载目标缓冲器的微处理器电路，系统和方法
公开(公告)号：US5953512A
公开(公告)日：1999-09-14
申请号：US999087
申请日：1997-12-29
申请人： George Z. N. Cai , Jonathan H. Shiell
发明人： George Z. N. Cai , Jonathan H. Shiell
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3455 , G06F9/383 , G06F9/3848
摘要： A load target circuit (56) with a plurality of entries (56.sub.1). Each the plurality of entries in the load target circuit comprises a value (ADDRESS TAG) for corresponding the line to a data fetching instruction. Additionally, each load target circuit line also includes a plurality of pointers (POINTER A, POINTER B, POINTER C). Each of the plurality of pointers is for storing a target data address corresponding to an incident of the data fetching instruction.
摘要翻译：具有多个入口（561）的负载目标电路（56）。负载目标电路中的多个条目中的每一个包括用于对应于数据获取指令的行的值（ADDRESS TAG）。此外，每个负载目标电路线还包括多个指针（POINTER A，POINTER B，POINTER C）。多个指针中的每一个用于存储与数据取出指令的事件对应的目标数据地址。

7. 发明授权

US5951679A Microprocessor circuits, systems, and methods for issuing successive iterations of a short backward branch loop in a single cycle 失效
标题翻译：微处理器电路，系统和方法，用于在单个周期中发出短的反向分支回路的连续迭代
公开(公告)号：US5951679A
公开(公告)日：1999-09-14
申请号：US962105
申请日：1997-10-31
申请人： Timothy D. Anderson , Jonathan H. Shiell
发明人： Timothy D. Anderson , Jonathan H. Shiell
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/381 , G06F9/325 , G06F9/3842
摘要： In a preferred method embodiment, the method operates a microprocessor (36). The method fetches (14) a short backward branch loop (34) of instructions, wherein the short backward branch loop comprises a branch instruction (SSB) and a target instruction (TR) The method also determines that the short backward branch instruction is a short backward branch instruction after fetching it. Still further, the method stores (30) a short backward branch loop of execution unit instructions. This short backward branch loop comprises a branch execution unit instruction (SSB) and a target execution unit instruction (TR). Additionally, without re-fetching the short backward branch loop after the storing step, the method also executes (22) a plurality of iterations of the short backward branch loop of execution unit instructions over a plurality of clock cycles. More specifically, for certain ones the plurality of clock cycles (clock cycle 10), the execution step executes both a first set of the execution unit instructions corresponding to a first iteration and a second set of the execution unit instructions corresponding to a second iteration, where the second iteration immediately follows the first iteration.
摘要翻译：在优选的方法实施例中，该方法操作微处理器（36）。该方法获取（14）指令的短反向分支循环（34），其中短反向分支回路包括分支指令（SSB）和目标指令（TR）。该方法还确定短向后分支指令是短的提取后分支指令。此外，该方法存储（30）执行单元指令的短的后向分支循环。该短反向分支回路包括分支执行单元指令（SSB）和目标执行单元指令（TR）。此外，在存储步骤之后不重新获取短的反向分支循环，该方法还在多个时钟周期上执行（22）执行单元指令的短反向分支循环的多个迭代。更具体地，对于某些时钟周期（时钟周期10），执行步骤执行与第一次迭代相对应的执行单元指令的第一组和对应于第二次迭代的执行单元指令的第二组，其中第二次迭代紧随第一次迭代。

8. 发明授权

US5799180A Microprocessor circuits, systems, and methods passing intermediate instructions between a short forward conditional branch instruction and target instruction through pipeline, then suppressing results if branch taken 失效
标题翻译：微处理器电路，系统和方法通过短路前进条件分支指令和目标指令之间的中间指令通过管道传递，然后如果分支采取抑制结果
公开(公告)号：US5799180A
公开(公告)日：1998-08-25
申请号：US741242
申请日：1996-10-30
申请人： Jonathan H. Shiell , James Oliver Bondi
发明人： Jonathan H. Shiell , James Oliver Bondi
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/325 , G06F9/30058 , G06F9/30069 , G06F9/30072
摘要： Circuits, systems, and methods relating to processor which processes a plurality of sequentially arranged instructions. In the method, one method step (10) receives into a processor pipeline an instruction from the plurality of sequentially arranged instructions. Another step (12) determines whether the received instruction comprises a short forward branch instruction. If the received instruction comprises a short forward branch instruction, the method (14) issues a detection signal and (16) issues a condition signal representing whether or not the condition of the short forward branch instruction is satisfied. Continuing, the method (18) receives into the processor pipeline a first group of instructions of the plurality of sequentially arranged instructions, where each is between the short forward branch instruction and the target instruction. Each such instruction passes fully through the processor pipeline and the method (26) suppresses its result in response to the detection signal if the condition signal represents that the condition of the short forward branch is satisfied.
摘要翻译：与处理多个顺序排列的指令的处理器有关的电路，系统和方法。在该方法中，一种方法步骤（10）从处理器流水线接收来自多个顺序排列的指令的指令。另一个步骤（12）确定所接收的指令是否包括短转发分支指令。如果接收到的指令包括短转移分支指令，则方法（14）发出检测信号，并且（16）发出表示是否满足短转移分支指令的条件的条件信号。接下来，方法（18）向处理器流水线中接收多个顺序排列的指令的第一组指令，其中每个指令在短向前转移指令和目标指令之间。每个这样的指令完全通过处理器流水线，并且如果条件信号表示满足短前进分支的条件，则方法（26）响应于检测信号来抑制其结果。

9. 发明授权

US06449692B1 Microprocessor circuits, systems, and methods with combined on-chip pixel and non-pixel cache structure 有权
标题翻译：具有组合片上像素和非像素缓存结构的微处理器电路，系统和方法
公开(公告)号：US06449692B1
公开(公告)日：2002-09-10
申请号：US09212034
申请日：1998-12-15
申请人： Steven D. Krueger , Jonathan H. Shiell , Ian Chen
发明人： Steven D. Krueger , Jonathan H. Shiell , Ian Chen
IPC分类号： G06F1208
CPC分类号： G06F12/0897 , G06F3/14 , G06F12/0848 , G06F12/0875 , G09G2360/121
摘要： A computer system (8) comprising a central processing unit (12) and a memory hierarchy. The memory hierarchy comprises a first cache memory (16) and a second cache memory (26). The first cache memory is operable to store non-pixel-information, wherein the non-pixel information is accessible for processing by the central processing unit. The second cache memory is higher in the memory hierarchy than the first cache memory, and has a number of storage locations operable to store non-pixel information (26b) and pixel data (26a). Lastly, the computer system comprises cache control circuitry (24) for dynamically apportioning the number of storage locations such that a first group of the storage locations are for storing non-pixel information and such that a second group of the storage locations are for storing pixel data.
摘要翻译：一种包括中央处理单元（12）和存储器层级的计算机系统（8）。存储器层级包括第一高速缓存存储器（16）和第二高速缓存存储器（26）。第一高速缓冲存储器可操作以存储非像素信息，其中非像素信息可被中央处理单元处理。第二高速缓冲存储器在存储器层级中高于第一高速缓冲存储器，并且具有可操作用于存储非像素信息（26b）和像素数据（26a）的多个存储位置。最后，计算机系统包括高速缓存控制电路（24），用于动态分配存储位置的数量，使得第一组存储位置用于存储非像素信息，并且第二组存储位置用于存储像素数据。

10. 发明授权

US6065125A SMM power management circuits, systems, and methods 失效
标题翻译： SMM电源管理电路，系统和方法
公开(公告)号：US6065125A
公开(公告)日：2000-05-16
申请号：US741876
申请日：1996-10-30
申请人： Jonathan H. Shiell , Ian Chen
发明人： Jonathan H. Shiell , Ian Chen
IPC分类号： G06F1/32 , G06F13/14
CPC分类号： G06F1/3203
摘要： Circuits, systems, and methods relating to operating a computer system operable in a system manager mode (24). The method includes various steps. The first step (34) occurs during operation of the computer system (10) at a time other than start-up, and receives user power management data from a user of the computer system. The second step (38) stores the user power management data in memory space (30) accessible by the system management mode. The third step (40) accesses the user power management data from the memory space. Finally, the fourth step (42) controls at least one peripheral (14, 16, 18, 20) of the computer system in response to the accessed user power management data.
摘要翻译：与操作以系统管理器模式操作的计算机系统相关的电路，系统和方法（24）。该方法包括各种步骤。第一步骤（34）在计算机系统（10）的操作期间发生在除了启动之外的时间，并且从计算机系统的用户接收用户电力管理数据。第二步骤（38）将用户电源管理数据存储在可由系统管理模式访问的存储器空间（30）中。第三步（40）从存储器空间访问用户电源管理数据。最后，第四步骤（42）响应于所访问的用户电源管理数据来控制计算机系统的至少一个外围设备（14,16,18,20）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式