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1. 发明授权

US07253689B2 Low distortion amplifier 有权
标题翻译：低失真放大器
公开(公告)号：US07253689B2
公开(公告)日：2007-08-07
申请号：US11148683
申请日：2005-06-08
申请人： Don C. Devendorf , Lloyd F. Linder , Cuong D. Tran
发明人： Don C. Devendorf , Lloyd F. Linder , Cuong D. Tran
IPC分类号： H03F3/04
CPC分类号： H03F1/32 , H03F3/26 , H03F3/3435
摘要： A low distortion amplifier. The novel amplifier includes a first transistor Q1 having first and second output terminals and an input terminal adapted to receive an input signal, and a second transistor Q2 having first and second output terminals and an input terminal adapted to receive a signal from the first output terminal of Q1, wherein the second output terminal of Q1 is connected to the second output terminal of Q2 in order to eliminate a nonlinear current component in Q2. In an illustrative embodiment, the amplifier also includes a cascode Darlington pair Q3, Q4 for holding the second output terminals of Q1 and Q2 at a desired voltage to further reduce distortion and to maintain a wide bandwidth.
摘要翻译：低失真放大器。新型放大器包括具有第一和第二输出端的第一晶体管Q 1和适于接收输入信号的输入端，以及具有第一和第二输出端的第二晶体管Q 2和适于从第一和第二输出端接收信号的输入端 Q 1的输出端子，其中Q 1的第二输出端子连接到Q 2的第二输出端子，以消除Q 2中的非线性电流分量。在说明性实施例中，放大器还包括用于将Q1和Q2的第二输出端保持在期望电压的共源共栅达林顿对Q 3，Q 4，以进一步减少失真并维持宽带宽。

2. 发明授权

US06400229B1 Low noise, low distortion RF amplifier topology 有权
标题翻译：低噪声，低失真RF放大器拓扑
公开(公告)号：US06400229B1
公开(公告)日：2002-06-04
申请号：US09790796
申请日：2001-02-22
申请人： Kelvin T. Tran , Clifford Duong , Michael N. Farias , Don C. Devendorf , Lloyd F. Linder
发明人： Kelvin T. Tran , Clifford Duong , Michael N. Farias , Don C. Devendorf , Lloyd F. Linder
IPC分类号： H03F122
CPC分类号： H03F1/34 , H03F1/22 , H03F3/42 , H03F2200/372
摘要： A low noise, low distortion radio frequency amplifier which includes a bootstrap design to minimize intermodulation distortion while simultaneously achieving low noise and wide bandwidth. In the illustrative embodiment, the invention includes a first circuit for receiving an input signal; a second circuit for amplifying the input signal using a transistor Q2; and a third circuit for regulating a rate of change of voltage across the transistor Q2 such that the rate of voltage change is zero. The third circuit includes a transistor Q3 connected to the transistor Q2 in cascode. In the specific illustrative embodiment, the third circuit further includes two diodes D1 and D2 used to modulate the voltage at the input of the transistor Q3 in proportion to the voltage modulation at the input of the transistor Q2. In the illustrative embodiment, the second circuit includes a transistor Q1 connected in cascade to the transistor Q2. In the specific illustrative embodiment, the invention further includes a fourth circuit for regulating a rate of change of voltage across the transistor Q1 such that the rate of voltage change is zero. The fourth circuit includes a transistor Q4 connected to the transistor Q1 in cascode. The two diodes D1 and D2 also connect the transistors Q1 and Q4 such that the voltage at the input of the transistor Q4 is modulated in proportion to the voltage modulation at the input of the transistor Q1.
摘要翻译：低噪声，低失真射频放大器，其包括自举设计，以最小化互调失真，同时实现低噪声和宽带宽。在说明性实施例中，本发明包括用于接收输入信号的第一电路; 用于使用晶体管Q2放大输入信号的第二电路; 以及用于调节晶体管Q2两端的电压变化率的第三电路，使得电压变化率为零。第三电路包括以级联连接到晶体管Q2的晶体管Q3。在具体说明性实施例中，第三电路还包括两个二极管D1和D2，用于与晶体管Q2的输入处的电压调制成比例地调制晶体管Q3的输入端的电压。在说明性实施例中，第二电路包括级联连接到晶体管Q2的晶体管Q1。在具体说明性实施例中，本发明还包括用于调节跨越晶体管Q1的电压变化率的第四电路，使得电压变化率为零。第四电路包括以级联连接到晶体管Q1的晶体管Q4。两个二极管D1和D2还连接晶体管Q1和Q4，使得晶体管Q4的输入处的电压与晶体管Q1的输入处的电压调制成比例地调制。

3. 发明授权

US07088148B2 Sample and hold circuit and bootstrapping circuits therefor 有权
标题翻译：采样保持电路和自举电路
公开(公告)号：US07088148B2
公开(公告)日：2006-08-08
申请号：US10863561
申请日：2004-06-08
申请人： Don C. Devendorf , Lloyd F. Linder , Kelvin T. Tran
发明人： Don C. Devendorf , Lloyd F. Linder , Kelvin T. Tran
IPC分类号： G11C27/02
CPC分类号： G11C27/02
摘要： A sample and hold circuit including a first arrangement for receiving an input signal; a second arrangement for sampling and holding the signal in response to a control signal; and a third arrangement for minimizing the change in an input transistor's base current when the circuit switches from track to hold or hold to track and for keeping the collector emitter voltage constant at the input transistor. An arrangement is disclosed to increase the dynamic current accuracy of a current mirror for a diode connected transistor, by holding the voltage across one transistor in the current mirror constant. Another arrangement is disclosed for holding collector to emitter voltage constant for intermediate transistors resulting in improved gain accuracy and linearity. In one embodiment, a dummy leg is added to isolate the output voltage from switching transients that occur when an intermediate transistor is turned on at the transition from track to hold.
摘要翻译：一种采样和保持电路，包括用于接收输入信号的第一装置; 第二装置，用于响应于控制信号采样和保持信号; 以及当电路从轨道切换到保持或保持跟踪并且用于保持集电极发射极电压恒定在输入晶体管时，最小化输入晶体管的基极电流的变化的第三布置。公开了一种通过将电流镜中的一个晶体管的电压保持恒定来提高二极管连接晶体管的电流镜的动态电流精度的装置。公开了另一种用于将集电极保持到中间晶体管的发射极电压恒定的结构，从而提高增益精度和线性度。在一个实施例中，添加虚拟支路以将输出电压与在从轨道到保持的转变时中间晶体管导通时发生的开关瞬变隔离。

4. 发明授权

US5581213A Variable gain amplifier circuit 失效
标题翻译：可变增益放大电路
公开(公告)号：US5581213A
公开(公告)日：1996-12-03
申请号：US479284
申请日：1995-06-07
申请人： Lloyd F. Linder , Don C. Devendorf , Bruno W. Garlepp
发明人： Lloyd F. Linder , Don C. Devendorf , Bruno W. Garlepp
IPC分类号： H03G1/00 , H03G3/12
CPC分类号： H03G1/0088
摘要： A non-attenuating automatic variable gain amplifier (VGA) circuit includes an operational amplifier (op amp) with a feedback resistor connected between its output and inverting input terminals. A variable gain setting resistance circuit having a variable resistance is the gain setting resistor positioned between the op amp's inverting input and a low voltage supply. By varying the resistance of the variable resistance circuit, the gain of the VGA circuit can be manipulated without requiring attenuation of the input signal. A resistance setting control for the variable resistance circuit can operate open loop, fed back from the amplifier output, or fed forward from the amplifier input.
摘要翻译：非衰减自动可变增益放大器（VGA）电路包括运算放大器（运算放大器），反相电阻连接在其输出和反相输入端子之间。具有可变电阻的可变增益设置电阻电路是位于运算放大器的反相输入和低电压电源之间的增益设置电阻。通过改变可变电阻电路的电阻，可以在不需要衰减输入信号的情况下操纵VGA电路的增益。可变电阻电路的电阻设置控制可以操作开路，从放大器输出反馈或从放大器输入端向前馈。

5. 发明授权

US07154421B2 DNL/INL trim techniques for comparator based analog to digital converters 有权
标题翻译：用于基于比较器的模数转换器的DNL / INL微调技术
公开(公告)号：US07154421B2
公开(公告)日：2006-12-26
申请号：US10890443
申请日：2004-07-12
申请人： Don C. Devendorf , Erick M. Hirata , Lloyd F. Linder
发明人： Don C. Devendorf , Erick M. Hirata , Lloyd F. Linder
IPC分类号： H03M1/06
CPC分类号： H03K5/2418 , H03M1/1057 , H03M1/1061 , H03M1/363
摘要： A trimmable comparator. The novel comparator includes a first circuit for comparing first and second input signals and in accordance therewith generating first and second output signals, and a second circuit for adding an adjustable current to the first output signal such that the comparator is in a transition state when the first and/or second input signals are at desired levels. The comparator may also include a third circuit for adding an adjustable current to the second output signal. In the illustrative embodiments, the second and third circuits are implemented using adjustable current sources with trimmable resistors, or using digital to analog converters. The novel comparators may be used in an analog to digital converter to allow the converter thresholds to be adjusted to desired levels.
摘要翻译：可调整比较器。新颖的比较器包括用于比较第一和第二输入信号并根据其产生第一和第二输出信号的第一电路和用于将可调电流加到第一输出信号的第二电路，使得当比较器处于转换状态时第一和/或第二输入信号处于期望的电平。比较器还可以包括用于将可调电流加到第二输出信号的第三电路。在说明性实施例中，第二和第三电路使用具有可调节电阻器的可调电流源或使用数模转换器来实现。新颖的比较器可以用在模数转换器中以允许将转换器阈值调整到期望的水平。

6. 发明授权

US07098684B2 High speed switch 有权
标题翻译：高速开关
公开(公告)号：US07098684B2
公开(公告)日：2006-08-29
申请号：US10740173
申请日：2003-12-18
申请人： Don C. Devendorf , Seth L. Everton , Lloyd F. Linder , Michael H. Liou
发明人： Don C. Devendorf , Seth L. Everton , Lloyd F. Linder , Michael H. Liou
IPC分类号： H03K19/013
CPC分类号： G11C27/02 , H03K17/04113
摘要： A high speed switch. The novel switch includes an input circuit having a transistor Q1 for receiving an input signal, a first mechanism for providing a path from an output of Q1 to an output terminal, and a second mechanism for receiving a control signal and in accordance therewith reducing the conductivity of the path during a mute mode. The first mechanism includes a first circuit for providing a first path from an output of Q1 to a first node, and a second circuit for providing a second path connecting the first node to the output terminal. The second mechanism is adapted to apply a signal to the first node during the mute mode such that the first and second circuits are off or partially conducting. The switch also includes a circuit for clamping the first node to a first predetermined voltage during the mute mode.
摘要翻译：高速开关新型开关包括具有用于接收输入信号的晶体管Q 1的输入电路，用于提供从Q 1的输出到输出端的路径的第一机构，以及用于接收控制信号的第二机构，并且根据其减少在静音模式下路径的电导率。第一机构包括用于提供从Q1的输出到第一节点的第一路径的第一电路和用于提供将第一节点连接到输出端子的第二路径的第二电路。第二机构适于在静音模式期间将信号施加到第一节点，使得第一和第二电路关闭或部分导通。开关还包括用于在静音模式期间将第一节点钳位到第一预定电压的电路。

7. 发明授权

US06693980B1 Wideband fast-hopping receiver front-end and mixing method 有权
标题翻译：宽带快跳接收机前端和混合方式
公开(公告)号：US06693980B1
公开(公告)日：2004-02-17
申请号：US09664298
申请日：2000-09-18
申请人： Lloyd F. Linder , Don C. Devendorf
发明人： Lloyd F. Linder , Don C. Devendorf
IPC分类号： H04L2722
CPC分类号： H03D7/165
摘要： A wideband fast-hopping receiver front-end uses direct digital synthesis (DDS) to provide quadrature LO signals to the front-end's mixers. A DDS circuit stores multiple digital word sequences which represent desired waveforms, and outputs desired sequence pairs to a pair of DACs in response to a clock signal and a command signal. The DACs convert the sequences to analog signals, which are filtered and squared as necessary to provide quadrature LO signals to the mixers. Frequency hopping is accomplished by changing the command signal, which causes a different pair of sequences to be output and the frequency of the LO signals provided to the mixers to be changed. Active image rejection is combined with DDS LO generation to provide faster frequency hopping. The front-end is combined with an ADC and a communications signal processor to provide a complete system, all of which can be integrated together on a common substrate.
摘要翻译：宽带快速跳频接收机前端使用直接数字合成（DDS）向前端的混频器提供正交LO信号。 DDS电路存储表示所需波形的多个数字字序列，并响应于时钟信号和命令信号将期望的序列对输出到一对DAC。 DAC将序列转换为模拟信号，根据需要进行滤波和平方以向混频器提供正交LO信号。通过改变命令信号来实现跳频，这导致输出不同的序列对，并且提供给混频器的LO信号的频率被改变。主动图像抑制与DDS LO生成相结合，提供更快的跳频。前端与ADC和通信信号处理器相结合，提供一个完整的系统，所有系统都可以集成在一个共同的基板上。

8. 发明授权

US5859558A Low voltage analog front end 失效
标题翻译：低压模拟前端
公开(公告)号：US5859558A
公开(公告)日：1999-01-12
申请号：US827855
申请日：1997-04-11
申请人： Ricky Y. Chen , Lloyd F. Linder , Don C. Devendorf
发明人： Ricky Y. Chen , Lloyd F. Linder , Don C. Devendorf
IPC分类号： H03D7/14 , H03F3/343 , H03F3/45 , G06G7/12
CPC分类号： H03F3/45071 , H03D7/1408 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D7/1491 , H03F3/343 , H03D2200/0033 , H03D2200/0043
摘要： A low voltage analog front end (AFE) includes a differential transistor pair which converts an input voltage, typically A.C.-coupled to the pair's control inputs, to a differential current. Impedance networks connected to each transistor's control input are joined together at a common node, and a current source is connected to the node which causes DC bias currents to be mirrored through the pair's current circuits, so that the AFE's differential output current comprises a differential current produced by the pair in response to an input voltage and superimposed on the DC bias currents. The current source preferably generates mirrored currents which are larger than its reference current to linearize the pair's response and to provide the AFE with a wide dynamic range. An input to the AFE sees a low impedance which is about equal to the sum of the impedance networks, which can be resistive or complex as needed. The AFE has widespread application as a front end circuit, serving as a low voltage input stage for a Gilbert mixer, for example. By generating bias currents via the pair's control inputs, supply voltage headroom requirements are reduced, improving a system's dynamic range and/or enabling the use of lower voltage power supplies. The AFE can be configured as either a differential or single-ended voltage-to-differential current converter.
摘要翻译：低电压模拟前端（AFE）包括差分晶体管对，其将输入电压（通常与耦合到对的控制输入的交流耦合）转换为差分电流。连接到每个晶体管的控制输入的阻抗网络在公共节点处连接在一起，并且电流源连接到节点，其导致DC偏置电流通过该对电流电路被镜像，使得AFE的差分输出电流包括差分电流由输出电压响应输入电压产生并叠加在直流偏置电流上。电流源优选地产生大于其参考电流的镜像电流，以使对的响应线性化并为AFE提供宽的动态范围。 AFE的输入端看到一个低阻抗，大约等于阻抗网络的总和，根据需要可以阻抗或复杂。 AFE作为前端电路广泛应用，例如用作Gilbert混频器的低电压输入级。通过经由该对的控制输入产生偏置电流，降低了电源电压余量要求，提高系统的动态范围和/或使能低电压电源。 AFE可以配置为差分或单端电压 - 差分电流转换器。

9. 发明授权

US06879276B2 Split cell bowtie digital to analog converter and method 失效
标题翻译：分离电池bowtie数字到模拟转换器和方法
公开(公告)号：US06879276B2
公开(公告)日：2005-04-12
申请号：US10739860
申请日：2003-12-18
申请人： Don C. Devendorf , Erick M. Hirata , Lloyd F. Linder , Christopher B. Langit , Roger N. Kosaka
发明人： Don C. Devendorf , Erick M. Hirata , Lloyd F. Linder , Christopher B. Langit , Roger N. Kosaka
IPC分类号： H03M1/06 , H03M1/74 , H03M1/66
CPC分类号： H03M1/0643 , H03M1/745
摘要： A DAC (10) including an operational amplifier (12) having an input terminal; a plurality of current paths coupled to the input terminal; a plurality of current sources (I1/2 -I4/2); and an arrangement (11) for switchably coupling current from at least two of the cells to a respective one of the paths in response to an input signal. In a specific embodiment, the inventive DAC (10) further includes a first resistive element (2R1-2R4) disposed in each of the current paths, a second resistive element (R1-R4) disposed between the current paths, and a feedback resistor (RF) disposed between an output terminal of the amplifier and the input terminal thereof. In the illustrative embodiment, the coupling arrangement includes a plurality of switches (SW1-SW4); each of the switches is adapted to switch half of the current from a first source and half of the current from a second source into a respective one of the paths. The invention is adapted to lower the distortion of digital to analog converters by improving differential nonlinearities and integral nonlinearities, caused primarily by current source gradient errors, without the need for trimming.
摘要翻译：包括具有输入端的运算放大器（12）的DAC（10）耦合到所述输入端的多个电流通路; 多个电流源（I1 / 2 -I4 / 2）; 以及用于响应于输入信号将来自至少两个单元的电流可切换地耦合到相应的一个路径的装置（11）。在具体实施例中，本发明的DAC（10）还包括设置在每个电流路径中的第一电阻元件（2R1-2R4），设置在电流路径之间的第二电阻元件（R1-R4）和反馈电阻器 RF）设置在放大器的输出端和其输入端之间。在说明性实施例中，耦合装置包括多个开关（SW1-SW4）; 每个开关适于将来自第一源的电流的一半和来自第二源的电流的一半切换到相应的一个路径。本发明适用于通过改善主要由电流源梯度误差引起的差分非线性和积分非线性来降低数模转换器的失真，而不需要修整。

10. 发明授权

US06040731A Differential pair gain control stage 失效
标题翻译：差分对增益控制级
公开(公告)号：US06040731A
公开(公告)日：2000-03-21
申请号：US848930
申请日：1997-05-01
申请人： Ricky Y. Chen , Lloyd F. Linder , Don C. Devendorf , Matthew S. Gorder
发明人： Ricky Y. Chen , Lloyd F. Linder , Don C. Devendorf , Matthew S. Gorder
IPC分类号： H03G3/10 , H03D7/14 , H03G1/00 , H03G1/04 , H03G3/02 , G06F7/44 , H03L5/00
CPC分类号： H03G1/0023 , H03D7/1408 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D7/1491 , H03D2200/0025 , H03D2200/0047
摘要： A "gain control differential pair" (GCDP) conducts current in response to a differential drive signal, with the gain of a signal path formed via the current circuit of one of its transistors controlled by the drive signal. The GCDP is preferably driven with a drive circuit that receives a symmetrical input signal and produces an offset differential drive signal which has the effect of keeping one of the GCDP's transistors turned off over a wider portion of a symmetrical input signal's voltage range, thereby reducing GCDP-caused noise. One or more GCDPs are implemented as part of a Gilbert mixer to regulate the amount of RF current that flows between the mixer's output and input stages, which eliminates the need to provide gain control in other circuits fed by the mixer. When driven with an offset drive signal, the Gilbert mixer simultaneously provides gain control, low distortion, low power consumption and excellent LO/RF isolation.
摘要翻译： “增益控制差动对”（GCDP）响应于差分驱动信号传导电流，其中通过其驱动信号控制的晶体管的一个晶体管的电流电路形成的信号通路的增益。 GCDP优选地被驱动电路驱动，该驱动电路接收对称的输入信号并产生偏移差分驱动信号，其具有在对称输入信号的电压范围的较宽部分上保持GCDP晶体管中的一个截止的效果，由此降低GCDP 有噪音一个或多个GCDP被实现为Gilbert混频器的一部分，以调节在混频器的输出和输入级之间流动的RF电流的量，这消除了在由混频器馈送的其它电路中提供增益控制的需要。当利用偏移驱动信号驱动时，Gilbert混频器同时提供增益控制，低失真，低功耗和优异的LO / RF隔离。

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