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1. 发明授权

US06400229B1 Low noise, low distortion RF amplifier topology 有权
标题翻译：低噪声，低失真RF放大器拓扑
公开(公告)号：US06400229B1
公开(公告)日：2002-06-04
申请号：US09790796
申请日：2001-02-22
申请人： Kelvin T. Tran , Clifford Duong , Michael N. Farias , Don C. Devendorf , Lloyd F. Linder
发明人： Kelvin T. Tran , Clifford Duong , Michael N. Farias , Don C. Devendorf , Lloyd F. Linder
IPC分类号： H03F122
CPC分类号： H03F1/34 , H03F1/22 , H03F3/42 , H03F2200/372
摘要： A low noise, low distortion radio frequency amplifier which includes a bootstrap design to minimize intermodulation distortion while simultaneously achieving low noise and wide bandwidth. In the illustrative embodiment, the invention includes a first circuit for receiving an input signal; a second circuit for amplifying the input signal using a transistor Q2; and a third circuit for regulating a rate of change of voltage across the transistor Q2 such that the rate of voltage change is zero. The third circuit includes a transistor Q3 connected to the transistor Q2 in cascode. In the specific illustrative embodiment, the third circuit further includes two diodes D1 and D2 used to modulate the voltage at the input of the transistor Q3 in proportion to the voltage modulation at the input of the transistor Q2. In the illustrative embodiment, the second circuit includes a transistor Q1 connected in cascade to the transistor Q2. In the specific illustrative embodiment, the invention further includes a fourth circuit for regulating a rate of change of voltage across the transistor Q1 such that the rate of voltage change is zero. The fourth circuit includes a transistor Q4 connected to the transistor Q1 in cascode. The two diodes D1 and D2 also connect the transistors Q1 and Q4 such that the voltage at the input of the transistor Q4 is modulated in proportion to the voltage modulation at the input of the transistor Q1.
摘要翻译：低噪声，低失真射频放大器，其包括自举设计，以最小化互调失真，同时实现低噪声和宽带宽。在说明性实施例中，本发明包括用于接收输入信号的第一电路; 用于使用晶体管Q2放大输入信号的第二电路; 以及用于调节晶体管Q2两端的电压变化率的第三电路，使得电压变化率为零。第三电路包括以级联连接到晶体管Q2的晶体管Q3。在具体说明性实施例中，第三电路还包括两个二极管D1和D2，用于与晶体管Q2的输入处的电压调制成比例地调制晶体管Q3的输入端的电压。在说明性实施例中，第二电路包括级联连接到晶体管Q2的晶体管Q1。在具体说明性实施例中，本发明还包括用于调节跨越晶体管Q1的电压变化率的第四电路，使得电压变化率为零。第四电路包括以级联连接到晶体管Q1的晶体管Q4。两个二极管D1和D2还连接晶体管Q1和Q4，使得晶体管Q4的输入处的电压与晶体管Q1的输入处的电压调制成比例地调制。

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