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1. 发明授权

US06400229B1 Low noise, low distortion RF amplifier topology 有权
标题翻译：低噪声，低失真RF放大器拓扑
公开(公告)号：US06400229B1
公开(公告)日：2002-06-04
申请号：US09790796
申请日：2001-02-22
申请人： Kelvin T. Tran , Clifford Duong , Michael N. Farias , Don C. Devendorf , Lloyd F. Linder
发明人： Kelvin T. Tran , Clifford Duong , Michael N. Farias , Don C. Devendorf , Lloyd F. Linder
IPC分类号： H03F122
CPC分类号： H03F1/34 , H03F1/22 , H03F3/42 , H03F2200/372
摘要： A low noise, low distortion radio frequency amplifier which includes a bootstrap design to minimize intermodulation distortion while simultaneously achieving low noise and wide bandwidth. In the illustrative embodiment, the invention includes a first circuit for receiving an input signal; a second circuit for amplifying the input signal using a transistor Q2; and a third circuit for regulating a rate of change of voltage across the transistor Q2 such that the rate of voltage change is zero. The third circuit includes a transistor Q3 connected to the transistor Q2 in cascode. In the specific illustrative embodiment, the third circuit further includes two diodes D1 and D2 used to modulate the voltage at the input of the transistor Q3 in proportion to the voltage modulation at the input of the transistor Q2. In the illustrative embodiment, the second circuit includes a transistor Q1 connected in cascade to the transistor Q2. In the specific illustrative embodiment, the invention further includes a fourth circuit for regulating a rate of change of voltage across the transistor Q1 such that the rate of voltage change is zero. The fourth circuit includes a transistor Q4 connected to the transistor Q1 in cascode. The two diodes D1 and D2 also connect the transistors Q1 and Q4 such that the voltage at the input of the transistor Q4 is modulated in proportion to the voltage modulation at the input of the transistor Q1.
摘要翻译：低噪声，低失真射频放大器，其包括自举设计，以最小化互调失真，同时实现低噪声和宽带宽。在说明性实施例中，本发明包括用于接收输入信号的第一电路; 用于使用晶体管Q2放大输入信号的第二电路; 以及用于调节晶体管Q2两端的电压变化率的第三电路，使得电压变化率为零。第三电路包括以级联连接到晶体管Q2的晶体管Q3。在具体说明性实施例中，第三电路还包括两个二极管D1和D2，用于与晶体管Q2的输入处的电压调制成比例地调制晶体管Q3的输入端的电压。在说明性实施例中，第二电路包括级联连接到晶体管Q2的晶体管Q1。在具体说明性实施例中，本发明还包括用于调节跨越晶体管Q1的电压变化率的第四电路，使得电压变化率为零。第四电路包括以级联连接到晶体管Q1的晶体管Q4。两个二极管D1和D2还连接晶体管Q1和Q4，使得晶体管Q4的输入处的电压与晶体管Q1的输入处的电压调制成比例地调制。

2. 发明授权

US5856760A Overdrive protection clamp scheme for feedback amplifiers 失效
标题翻译：反馈放大器的过驱保护钳位方案
公开(公告)号：US5856760A
公开(公告)日：1999-01-05
申请号：US745070
申请日：1996-11-07
申请人： Khanh Lam , Lloyd F. Linder , Carrie C. Lo , Tim M. Ng , Kelvin T. Tran
发明人： Khanh Lam , Lloyd F. Linder , Carrie C. Lo , Tim M. Ng , Kelvin T. Tran
IPC分类号： H03F1/52 , H03F3/30
CPC分类号： H03F1/52 , H03F3/3076 , H03F2200/372
摘要： A low-noise, low-distortion clamping scheme includes a bootstrapped voltage clamp and an R.sub.gm current clamp that provide superior overdrive protection when used together in a Class-AB feedback amplifier. The bootstrapped voltage clamp includes a transistor that is connected to a circuit node to be clamped. The transistor's base is bootstrapped to the node to maintain a constant V.sub.be when not clamping, to reduce the adverse effects of the junction capacitance C.sub.je which would normally vary with the node voltage and distort the signal at the node. Two such clamps provide positive and negative voltage limiting. The R.sub.gm current clamp is used in the input stage of a Class-AB feedback amplifier to limit the current through the resistor R.sub.gm that interconnects the current inputs of two transconductance amplifiers whenever the voltage drop across R.sub.gm increases to an unacceptable level. The clamp uses a dependent current source whose output current increases with the magnitude of the current flowing through R.sub.gm and prevents that current from exceeding a predetermined limit. When not clamping, the clamp has a very small effect on the amplifier's input stage. Two R.sub.gm current clamps are typically used to limit current flowing in either direction through R.sub.gm.
摘要翻译：低噪声，低失真钳位方案包括一个自举电压钳位电路和一个Rgm电流钳位电路，可在AB类反馈放大器中一起使用时提供卓越的过驱动保护。自举电压钳包括连接到要钳位的电路节点的晶体管。晶体管的基极被引导到节点，以在不夹持时保持恒定的Vbe，以减少结电容Cje的不利影响，其通常随着节点电压而变化并且使节点处的信号失真。两个这样的夹具提供正和负电压限制。 Rgm电流钳位用于AB类反馈放大器的输入级，以限制通过电阻Rgm的电流，每当跨过Rgm的电压降到不可接受的电平时，互连两个跨导放大器的电流输入。钳位使用依赖电流源，其输出电流随流过Rgm的电流的大小而增加，并防止该电流超过预定极限。当不夹紧时，夹具对放大器的输入级具有非常小的影响。通常使用两个Rgm电流钳来限制在任一方向流过Rgm的电流。

3. 发明授权

US07088148B2 Sample and hold circuit and bootstrapping circuits therefor 有权
标题翻译：采样保持电路和自举电路
公开(公告)号：US07088148B2
公开(公告)日：2006-08-08
申请号：US10863561
申请日：2004-06-08
申请人： Don C. Devendorf , Lloyd F. Linder , Kelvin T. Tran
发明人： Don C. Devendorf , Lloyd F. Linder , Kelvin T. Tran
IPC分类号： G11C27/02
CPC分类号： G11C27/02
摘要： A sample and hold circuit including a first arrangement for receiving an input signal; a second arrangement for sampling and holding the signal in response to a control signal; and a third arrangement for minimizing the change in an input transistor's base current when the circuit switches from track to hold or hold to track and for keeping the collector emitter voltage constant at the input transistor. An arrangement is disclosed to increase the dynamic current accuracy of a current mirror for a diode connected transistor, by holding the voltage across one transistor in the current mirror constant. Another arrangement is disclosed for holding collector to emitter voltage constant for intermediate transistors resulting in improved gain accuracy and linearity. In one embodiment, a dummy leg is added to isolate the output voltage from switching transients that occur when an intermediate transistor is turned on at the transition from track to hold.
摘要翻译：一种采样和保持电路，包括用于接收输入信号的第一装置; 第二装置，用于响应于控制信号采样和保持信号; 以及当电路从轨道切换到保持或保持跟踪并且用于保持集电极发射极电压恒定在输入晶体管时，最小化输入晶体管的基极电流的变化的第三布置。公开了一种通过将电流镜中的一个晶体管的电压保持恒定来提高二极管连接晶体管的电流镜的动态电流精度的装置。公开了另一种用于将集电极保持到中间晶体管的发射极电压恒定的结构，从而提高增益精度和线性度。在一个实施例中，添加虚拟支路以将输出电压与在从轨道到保持的转变时中间晶体管导通时发生的开关瞬变隔离。

4. 发明授权

US5859569A Current feedback differential amplifier clamp 失效
标题翻译：电流反馈差分放大器钳位
公开(公告)号：US5859569A
公开(公告)日：1999-01-12
申请号：US843200
申请日：1997-04-14
申请人： Hieu M. Le , Lloyd F. Linder , Erick M. Hirata , Benjamin Felder , Roger N. Kosaka , Donald G. McMullin , Kelvin T. Tran
发明人： Hieu M. Le , Lloyd F. Linder , Erick M. Hirata , Benjamin Felder , Roger N. Kosaka , Donald G. McMullin , Kelvin T. Tran
IPC分类号： H03F1/52 , H03F3/30 , H02H7/20 , H03M1/12
CPC分类号： H03F3/3076 , H03F1/52
摘要： A current steering circuit diverts bias current from a differential current summing amplifier's front end when the differential input exceeds a safe threshold level, thus preventing the amplifier's output stage from being overdriven. Diverting the front end's bias currents also turns off transistors within the amplifier's front end and thus protects the front end from damage which may otherwise result from excessive input signals.
摘要翻译：当差分输入超过安全阈值电平时，电流转向电路将偏置电流从差分电流求和放大器的前端转移，从而防止放大器的输出级过载。转向前端的偏置电流也会关闭放大器前端的晶体管，从而保护前端免受过大输入信号造成的损坏。

5. 发明授权

US5410274A Single-ended and differential amplifiers with high feedback input impedance and low distortion 失效
标题翻译：具有高反馈输入阻抗和低失真的单端和差分放大器
公开(公告)号：US5410274A
公开(公告)日：1995-04-25
申请号：US210269
申请日：1994-03-17
申请人： Dwight D. Birdsall , Phillip L. Elliott , Lloyd F. Linder , Kelvin T. Tran , Donald G. McMullin
发明人： Dwight D. Birdsall , Phillip L. Elliott , Lloyd F. Linder , Kelvin T. Tran , Donald G. McMullin
IPC分类号： H03F3/26 , H03F3/30 , H03F3/45
CPC分类号： H03F3/3081 , H03F3/26 , H03F3/3067
摘要： First and second current feedback transconductance amplifiers (102,104) each have a high impedance voltage input, a low impedance current input and a pair of push-pull current outputs. In a single-ended configuration, an input signal is applied to the voltage input of the first transconductance amplifier (102) and the push-pull outputs of the both transconductance amplifiers are connected through a current mirror (136,138) to a node (134) where the current outputs are summed. The node current is integrated by a capacitor (174) to produce a voltage which is amplified by a transimpedance amplifier (190) to produce an output voltage which is fed back to the voltage input of the second transconductance amplifier (104). The current inputs of the transconductance amplifiers (102,104) are interconnected by a resistor (132). The high impedance voltage inputs produce common-mode cancellation of distortion in the transconductance amplifiers (102,104) and low input shot noise. In a differential configuration, differential input signals are applied to the voltage inputs of transconductance amplifiers (260,262), and a separate transimpedance amplifier (292,316) and current mirror (278,280) (302,304) is provided for each transconductance amplifier (260,262). A common-mode feedback circuit (352) controls the common-mode output voltages of the transimpedance amplifiers (292,316) to ground. Switch means (402,404,406,408,410,412) may be added to selectively ground the voltage inputs of the transconductance amplifiers (260,262) and disable their input stages by disconnecting their power supplies (VCC,VEE).
摘要翻译：第一和第二电流反向跨导放大器（102,104）各自具有高阻抗电压输入，低阻抗电流输入和一对推挽电流输出。在单端配置中，输入信号被施加到第一跨导放大器（102）的电压输入，并且两个跨导放大器的推挽输出通过电流镜（136,138）连接到节点（134）其中当前输出相加。节点电流由电容器（174）积分以产生被跨阻放大器（190）放大的电压，以产生反馈到第二跨导放大器（104）的电压输入端的输出电压。跨导放大器（102,104）的电流输入通过电阻器（132）互连。高阻抗电压输入产生跨导放大器（102,104）中的失真的共模消除和低输入散射噪声。在差分配置中，差分输入信号被施加到跨导放大器（260,262）的电压输入端，并为每个跨导放大器（260,262）提供单独的跨阻抗放大器（292,316）和电流镜（278,308）（302,304）。共模反馈电路（352）控制跨阻放大器（292,316）的共模输出电压接地。可以添加开关装置（402,404,406,408,410,412）以有选择地接地跨导放大器（260,262）的电压输入，并且通过断开它们的电源（VCC，VEE）来禁用它们的输入级。

6. 发明授权

US07071781B2 High speed, high resolution amplifier topology 有权
标题翻译：高速，高分辨率放大器拓扑
公开(公告)号：US07071781B2
公开(公告)日：2006-07-04
申请号：US10740172
申请日：2003-12-18
申请人： Seth L. Everton , Lloyd F. Linder , Michael H. Liou , Tom A. Spargo , Kelvin T. Tran
发明人： Seth L. Everton , Lloyd F. Linder , Michael H. Liou , Tom A. Spargo , Kelvin T. Tran
IPC分类号： H03F3/45
CPC分类号： H03F3/45179 , H03F1/0233 , H03F1/3211 , H03F3/45089 , H03F2203/45674
摘要： An amplifier. The novel amplifier includes a first circuit for receiving and amplifying an input signal and outputting an output signal, and a second circuit for supplying power to the first circuit, wherein the power supplied varies in accordance with variations in the output signal. The second circuit includes a bootstrapping circuit adapted to regulate the voltages across any transistors in the signal path such that the voltages remain constant. In an illustrative embodiment, the second circuit bootstraps the voltages across a PMOS current source that acts as the load to an input stage, as well as a Darlington pair in an output stage of the amplifier.
摘要翻译：放大器新型放大器包括用于接收和放大输入信号并输出输出信号的第一电路和用于向第一电路供电的第二电路，其中所提供的功率根据输出信号的变化而变化。第二电路包括自举电路，其适于调节信号路径中的任何晶体管上的电压，使得电压保持恒定。在说明性实施例中，第二电路将用作负载的PMOS电流源两端的电压引导到放大器的输出级中的达林顿对。

7. 发明授权

US5963094A Monolithic class AB shunt-shunt feedback CMOS low noise amplifier having self bias 失效
标题翻译：单片式AB分路反馈CMOS低噪声放大器具有自偏置
公开(公告)号：US5963094A
公开(公告)日：1999-10-05
申请号：US27241
申请日：1998-02-20
申请人： Lloyd F. Linder , Kelvin T. Tran
发明人： Lloyd F. Linder , Kelvin T. Tran
IPC分类号： H03F3/30 , H03F3/18 , H03F3/26
CPC分类号： H03F3/3001 , H03F2200/372
摘要： A monolithic class AB (push-pull) low noise amplifier having feedback and self bias. The low noise amplifier exhibits low power, high intercept point, low noise figure, well matched terminal impedances over wide range of frequency, and may be monolithically implemented. The amplifier may be produced using CMOS process technologies. The amplifier comprises NMOS and PMOS transistors serially coupled between a voltage rail and ground. The amplifier uses self biasing embodied in a bias resistor coupled between an input shunt capacitor and respective drains of the NMOS and PMOS transistors, which allows for maximum gate-to-source voltage and higher transconductance for a minimum aspect ratio (W/L). This results in a wider bandwidth and reduced power for the amplifier. The use of a shunt--shunt feedback network comprising a shunt resistor and a serially coupled shunt capacitor coupled between respective gates and drains of the NMOS and PMOS transistors, provides better terminal impedance matching over wide bandwidth.
摘要翻译：具有反馈和自偏压的单片AB类（推挽）低噪声放大器。低噪声放大器在宽范围的频率范围内表现出低功率，高截止点，低噪声系数，良好匹配的端子阻抗，并且可以单片地实现。放大器可以使用CMOS工艺技术制造。放大器包括串联耦合在电压轨和地之间的NMOS和PMOS晶体管。放大器使用自耦偏压，该偏置电阻耦合在输入并联电容器和NMOS和PMOS晶体管的相应漏极之间，这允许最大栅极 - 源极电压和更高的跨导达到最小纵横比（W / L）。这导致放大器的宽带宽和功率降低。使用包括分流电阻器和耦合在NMOS和PMOS晶体管的相应栅极和漏极之间的串联耦合电容器的分流反馈网络在宽带宽上提供更好的端子阻抗匹配。

8. 发明授权

US5483150A Transistor current switch array for digital-to-analog converter (DAC) including bias current compensation for individual transistor current gain and thermally induced base-emitter voltage drop variation 失效
标题翻译：用于数模转换器（DAC）的晶体管电流开关阵列，包括用于单个晶体管电流增益和热感应基极 - 发射极电压降变化的偏置电流补偿
公开(公告)号：US5483150A
公开(公告)日：1996-01-09
申请号：US17200
申请日：1993-02-05
申请人： Phillip L. Elliott , Dwight D. Birdsall , Lloyd F. Linder , Kelvin T. Tran
发明人： Phillip L. Elliott , Dwight D. Birdsall , Lloyd F. Linder , Kelvin T. Tran
IPC分类号： G05F3/20 , H03M1/08 , H03M1/74 , G05F3/08
CPC分类号： G05F3/205 , H03M1/089 , H03M1/742
摘要： A bias voltage source (20) produces a variable bias voltage (VBREF) which regulates the bias currents in an array (30) of transistor current switch cells (34,36) in an digital-to-analog converter (DAC). The bias voltage (VBREF) is applied to the bases of the regulating transistors (Q8') in the cells (34,36) to regulate the bias currents in their respective main transistors (Q6',Q7') to values proportional to the main bias current (IBIAS). Each main transistor (Q6,Q6',Q7,Q7') and regulating transistor (Q8,Q8') is provided with a compensating transistor (Q10,Q10')(Q11,-Q11') which sinks the emitter-base current thereof and cancels deviation of the actual current gain from the design current gain. Another compensating transistor (Q9,Q9') is connected to each regulating transistor (Q8,Q8') to cancel the effect of base-emitter voltage variation with temperature.
摘要翻译：偏置电压源（20）产生调节数模转换器（DAC）中的晶体管电流开关单元（34,36）的阵列（30）中的偏置电流的可变偏置电压（VBREF）。偏置电压（VBREF）被施加到单元（34,36）中的调节晶体管（Q8'）的基极，以将它们各自的主晶体管（Q6'，Q7'）中的偏置电流调节到与主偏置电流（IBIAS）。每个主晶体管（Q6，Q6'，Q7，Q7'）和调节晶体管（Q8，Q8'）设置有一个补偿晶体管（Q10，Q10'）（Q11，-Q11'），并取消实际电流增益与设计电流增益的偏差。另一个补偿晶体管（Q9，Q9'）连接到每个调节晶体管（Q8，Q8'）以消除基极 - 发射极电压随温度变化的影响。

9. 发明授权

US5315231A Symmetrical bipolar bias current source with high power supply rejection ratio (PSRR) 失效
标题翻译：具有高电源抑制比（PSRR）的对称双极偏置电流源
公开(公告)号：US5315231A
公开(公告)日：1994-05-24
申请号：US976760
申请日：1992-11-16
申请人： Lloyd F. Linder , Dwight D. Birdsall , Kelvin T. Tran
发明人： Lloyd F. Linder , Dwight D. Birdsall , Kelvin T. Tran
IPC分类号： H03F3/45 , H03F1/30 , H03F3/26 , H03F3/30 , G05F3/26
CPC分类号： H03F1/307 , H03F3/26
摘要： A bandgap reference voltage source (104) has positive and negative terminals (104a,104b) which are connected through high impedance constant current sources (124c,126c) to positive and negative voltage supplies (+VDD,-VEE) respectively. The effect of variations of the voltage supplies (+VDD, -VEE) on the voltage source (104) is low due to the high impedances of the currents sources (124c,126c), providing a high power supply rejection ratio (PSRR). The reference voltage (VREF) generated by the voltage source (104) is converted into a reference current (IREF) which flows through two equal series resistors (108,110), and also through current mirrors (124,126) which produce positive and negative output currents corresponding thereto. The current sources (124c,126c) for the voltage source (104) are also controlled by the current mirrors (124,126). A servo control amplifier (232) senses the voltage at the junction (234) of the resistors (108,110) and adjusts the voltage at either the positive or negative terminal (104a,104b) of the voltage source (104) to maintain the voltages at the terminals (104a,104b) symmetrical with respect to ground, thereby preventing the voltage source (104) from latching to one of the voltage supplies (+VDD,-VEE) during startup.
摘要翻译：带隙参考电压源（104）具有分别通过高阻抗恒流源（124c，126c）连接到正和负电压源（+ VDD，-VEE）的正端子和负端子（104a，104b）。由于电流源（124c，126c）的高阻抗提供高电源抑制比（PSRR），电压源（+ VDD，-VEE）的变化对电压源（104）的影响很小。由电压源（104）产生的参考电压（VREF）被转换成流过两个相等的串联电阻（108,110）的参考电流（IREF），并且还通过电流镜（124,126）产生正和负的输出电流对应到此。用于电压源（104）的电流源（124c，126c）也由电流镜（124,126）控制。伺服控制放大器（232）感测电阻器（108,110）的结（234）处的电压，并且调节电压源（104）的正或负端子（104a，104b）处的电压，以将电压维持在端子（104a，104b）相对于地面对称，从而防止电压源（104）在启动期间锁定到电压源（+ VDD，-VEE）之一。

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