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1. 发明授权

US5657279A Redundant circuit configuration for an integrated semiconductor memory 失效
标题翻译：集成半导体存储器的冗余电路配置
公开(公告)号：US5657279A
公开(公告)日：1997-08-12
申请号：US514602
申请日：1995-08-14
申请人： Dominique Savignac , Diether Sommer , Oliver Kiehl
发明人： Dominique Savignac , Diether Sommer , Oliver Kiehl
IPC分类号： G11C29/00 , G11C29/04 , G11C8/00
CPC分类号： G11C29/806 , G11C29/812
摘要： A redundant circuit configuration for an integrated semiconductor memory has normal and redundant memory cells, in which addresses of arbitrary groups of memory cells of the memory are formed from a first partial address and a second partial address. M fixedly programmable address circuits, where M.gtoreq.1, are each assigned to one of the first partial addresses. Each fixedly programmable address circuit in an activated state has the second partial address of a group of normal memory cells to be replaced and has a first output at which an activation signal is applied in the activated state of the address circuit if the first partial address applied to the circuit configuration matches the first partial address assigned to the address circuit. One address comparator is common to all of the address circuits and has a first output. The comparator compares the second partial address stored in memory in one of the address circuits with the applied second partial address, at the applied activation signal of the one address circuit. The comparator supplies an enable signal at the first output of the address comparator if the two partial addresses match. Redundance decoders are triggered by the enable signal.
摘要翻译：用于集成半导体存储器的冗余电路配置具有正常和冗余的存储单元，其中存储器的任意存储单元组的地址由第一部分地址和第二部分地址形成。 M个固定可编程地址电路，其中M> / = 1，每个分配给第一部分地址之一。处于激活状态的每个固定可编程地址电路具有要被替换的一组正常存储器单元的第二部分地址，并且具有第一输出，在第一输出处，如果应用了第一部分地址，则在激活状态下施加激活信号电路配置匹配分配给地址电路的第一部分地址。一个地址比较器对于所有地址电路是公共的，并且具有第一输出。所述比较器在所述一个地址电路的所施加的激活信号上比较存储在其中一个地址电路中的所述第二部分地址与所施加的第二部分地址。如果两个部分地址匹配，比较器将在地址比较器的第一个输出端提供使能信号。冗余解码器由使能信号触发。

2. 发明申请

US20080313494A1 MEMORY REFRESH SYSTEM AND METHOD 有权
标题翻译：存储器刷新系统和方法
公开(公告)号：US20080313494A1
公开(公告)日：2008-12-18
申请号：US11763593
申请日：2007-06-15
申请人： Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Josef Schnell , Octavian Beldiman , Lee Ward Collins
发明人： Klaus Hummler , Jong Hoon Oh , Wayne Frederick Ellis , Jung Pill Kim , Oliver Kiehl , Josef Schnell , Octavian Beldiman , Lee Ward Collins
IPC分类号： G06F11/16
CPC分类号： G11C29/02 , G11C7/1039 , G11C11/401 , G11C11/406 , G11C29/028 , G11C29/50016 , G11C2211/4062 , G11C2211/4065
摘要： A refresh scheduler is configured to refresh memory cells of a memory device according to a plurality of refresh intervals. The various refresh intervals are determined in response to refresh errors.
摘要翻译：刷新调度器被配置为根据多个刷新间隔刷新存储器设备的存储单元。响应于刷新错误确定各种刷新间隔。

3. 发明申请

US20080189480A1 Memory configured on a common substrate 有权
标题翻译：存储器配置在公共基板上
公开(公告)号：US20080189480A1
公开(公告)日：2008-08-07
申请号：US11701006
申请日：2007-02-01
申请人： Jung Pill Kim , Jong-Hoon Oh , Oliver Kiehl , Josef Schnell , Klaus Hummler , Wayne Ellis , Octavian Beldiman , Lee Collins
发明人： Jung Pill Kim , Jong-Hoon Oh , Oliver Kiehl , Josef Schnell , Klaus Hummler , Wayne Ellis , Octavian Beldiman , Lee Collins
IPC分类号： G06F12/00
CPC分类号： G11C5/04 , G11C5/063 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/15192 , H01L2924/15311 , H05K1/181 , H01L2224/0401
摘要： A memory includes a first macro chip, a spine chip, and a common substrate. The common substrate is configured to pass signals between the first macro chip and the spine chip. The first macro chip, the spine chip, and the common substrate provide a memory.
摘要翻译：存储器包括第一宏芯片，脊芯片和公共基板。公共基板被配置为在第一宏芯片和脊芯片之间传递信号。第一个宏芯片，脊椎芯片和公共基板提供了一个记忆。

4. 发明授权

US07321628B2 Data transmission system with reduced power consumption 有权
标题翻译：数据传输系统功耗降低
公开(公告)号：US07321628B2
公开(公告)日：2008-01-22
申请号：US10674859
申请日：2003-09-30
申请人： Oliver Kiehl
发明人： Oliver Kiehl
IPC分类号： H04L27/00
CPC分类号： H04L25/4915
摘要： System and method for reducing power consumption and noise in a transmission system with an asymmetrically terminated transmission line. A preferred embodiment comprises encoding data words to reduce the number of times a given state appears in a code word. The preferred embodiment comprises counting the number of times a given state appears in a data word. If the count is greater than half of the total number of bits in the data word, then the data word is inverted and a weight bit can be set to the given state. If the count is less than (or equal to) half of the total number of bits, then the data word may be unchanged and the weight bit can be set to the inverse of the given state. The code word can be generated by appending the weight bit to the data word.
摘要翻译：具有不对称端接传输线的传输系统中降低功耗和噪声的系统和方法。优选实施例包括编码数据字以减少给定状态在码字中出现的次数。优选实施例包括对给定状态在数据字中出现的次数进行计数。如果计数大于数据字中总位数的一半，则数据字被反转，并且可以将权重位设置为给定状态。如果计数小于（或等于）总位数的一半，则数据字可以不变，并且权重位可以被设置为给定状态的倒数。可以通过将权重位附加到数据字来生成代码字。

5. 发明授权

US07215595B2 Memory device and method using a sense amplifier as a cache 有权
标题翻译：使用读出放大器作为缓存的存储器件和方法
公开(公告)号：US07215595B2
公开(公告)日：2007-05-08
申请号：US10967899
申请日：2004-10-18
申请人： Oliver Kiehl
发明人： Oliver Kiehl
IPC分类号： G11C8/18
CPC分类号： G11C11/4091 , G11C7/06 , G11C7/12 , G11C11/4094 , G11C2207/005
摘要： A memory device includes a pair of complementary bitlines including a first bitline and a second bitline. A bitline precharge block is coupled between the first bitline and the second bitline. A sense amplifier is coupled to both the first bitline and the second bitline and a sense amplifier precharge block is coupled to the sense amplifier. The sense amplifier precharge block can be activated independently from the bitline precharge block. An isolation block is coupled between the pair of complementary bitlines and the bitline precharge block on one side and the sense amplifier and sense amplifier precharge block on another side.
摘要翻译：存储器件包括一对补充位线，包括第一位线和第二位线。位线预充电块耦合在第一位线和第二位线之间。读出放大器耦合到第一位线和第二位线，读出放大器预充电块耦合到读出放大器。读出放大器预充电块可以独立于位线预充电块来激活。隔离块耦合在一对互补位线和一侧的位线预充电块和另一侧的读出放大器和读出放大器预充电块之间。

6. 发明授权

US06730989B1 Semiconductor package and method 失效
标题翻译：半导体封装及方法
公开(公告)号：US06730989B1
公开(公告)日：2004-05-04
申请号：US09596130
申请日：2000-06-16
申请人： Manfred Reithinger , Mike Killian , Gerd Frankowsky , Oliver Kiehl , Gerhard Mueller , Ernst Stahl , Hartmud Terletzki , Thomas Vogelsang
发明人： Manfred Reithinger , Mike Killian , Gerd Frankowsky , Oliver Kiehl , Gerhard Mueller , Ernst Stahl , Hartmud Terletzki , Thomas Vogelsang
IPC分类号： H01L23544
CPC分类号： H01L23/5382 , H01L23/50 , H01L25/18 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.
摘要翻译：半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。晶片的分数部分具有电连接到芯片的多个电触点。封装还包括其上具有电导体的电介质构件。电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

7. 发明授权

US06294940B1 Symmetric clock receiver for differential input signals 有权
标题翻译：用于差分输入信号的对称时钟接收器
公开(公告)号：US06294940B1
公开(公告)日：2001-09-25
申请号：US09598349
申请日：2000-06-21
申请人： Oliver Kiehl
发明人： Oliver Kiehl
IPC分类号： H03K300
CPC分类号： H03K5/1534 , G06F1/10 , H03K5/00006
摘要： A clock circuit, in accordance with the present invention, includes a first circuit stage for providing a first output signal and a second output signal. The first circuit stage includes inputs for clock signals. A switch is coupled to the first stage for switching an output polarity by selecting one of the first output signal and the second output signal generated by the first circuit stage in accordance with a control signal. A second circuit stage is coupled to the first circuit stage through the switch. The second circuit stage for shaping the first and second output signals input thereto from the switch. The second circuit stage includes an output for outputting clock pulses based on the first and second output signals. The control signal is generated from the clock pulses.
摘要翻译：根据本发明的时钟电路包括用于提供第一输出信号和第二输出信号的第一电路级。第一个电路级包括时钟信号的输入。开关通过根据控制信号选择由第一电路级产生的第一输出信号和第二输出信号之一来耦合到第一级用于切换输出极性。第二电路级通过开关耦合到第一电路级。用于对从开关输入的第一和第二输出信号进行整形的第二电路级。第二电路级包括用于基于第一和第二输出信号输出时钟脉冲的输出。控制信号由时钟脉冲产生。

8. 发明授权

US5444398A Decoded-source sense amplifier with special column select driver voltage 失效
标题翻译：具有特殊列选择驱动电压的解码源读出放大器
公开(公告)号：US5444398A
公开(公告)日：1995-08-22
申请号：US995639
申请日：1992-12-17
申请人： Oliver Kiehl , Fergal Bonner , Michael Killian , Klaus J. Lau
发明人： Oliver Kiehl , Fergal Bonner , Michael Killian , Klaus J. Lau
IPC分类号： G11C11/409 , G11C7/06 , H03K3/45
CPC分类号： G11C7/065
摘要： A decoded source sense amplifier in which the column select signal is shaped so that it turns on bit select transistors at a predetermined time after the source electrodes of the sense amplifier are connected to ground, so as to give the sense amplifier time to latch before it is coupled to external bit lines.
摘要翻译：一种解码源读出放大器，其中列选择信号的形状使其在读出放大器的源电极连接到地之后的预定时间接通位选择晶体管，以便给出读出放大器在其之前锁存的时间耦合到外部位线。

9. 发明申请

US20130082718A1 CIRCUIT TEST INTERFACE AND TEST METHOD THEREOF 有权
标题翻译：电路测试接口及其测试方法
公开(公告)号：US20130082718A1
公开(公告)日：2013-04-04
申请号：US13253061
申请日：2011-10-04
申请人： Bret Dale , Oliver Kiehl
发明人： Bret Dale , Oliver Kiehl
IPC分类号： G01R1/00
CPC分类号： G01R31/3172 , G01R31/318572
摘要： A circuit test interface and a test method are disclosed. The circuit test interface may include a test voltage input pad, a test voltage output pad, and a plurality of input buffers. Each of the plurality of input buffers may have a first input terminal, a second input terminal, and an output terminal. The first input terminal of each respective input buffer may be coupled to one of a plurality of through-silicon vias (TSVs). The circuit test interface may further include a plurality of switch units. Each of the plurality of switch units may have a first terminal and a second terminal. The circuit test interface may further include a scan chain, coupled to both the output terminal of each of the plurality of input buffers and to the test voltage output pad.
摘要翻译：公开了电路测试接口和测试方法。电路测试接口可以包括测试电压输入焊盘，测试电压输出焊盘和多个输入缓冲器。多个输入缓冲器中的每一个可以具有第一输入端子，第二输入端子和输出端子。每个相应输入缓冲器的第一输入端可以耦合到多个穿硅通孔（TSV）中的一个。电路测试接口还可以包括多个开关单元。多个开关单元中的每一个可以具有第一端子和第二端子。电路测试接口还可以包括耦合到多个输入缓冲器中的每一个的输出端和测试电压输出焊盘两者的扫描链。

10. 发明申请

US20090200652A1 METHOD FOR STACKING CHIPS IN A MULTI-CHIP PACKAGE 有权
标题翻译：用于在多芯片封装中堆叠晶片的方法
公开(公告)号：US20090200652A1
公开(公告)日：2009-08-13
申请号：US12028542
申请日：2008-02-08
申请人： Jong Hoon Oh , Klaus Hummler , Oliver Kiehl , Josef Schnell , Wayne Frederick Ellis , Jung Pil Kim , Lee Ward Collins , Octavian Beldiman
发明人： Jong Hoon Oh , Klaus Hummler , Oliver Kiehl , Josef Schnell , Wayne Frederick Ellis , Jung Pil Kim , Lee Ward Collins , Octavian Beldiman
IPC分类号： H01L23/498 , H01L21/58
CPC分类号： H01L25/0657 , H01L25/03 , H01L25/18 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06513 , H01L2924/00014 , H01L2924/01079 , H01L2224/05599
摘要： A multi-chip package is provided that has at least a first, second and third chip, each comprising a top and bottom surface. The multi-chip package also has a package substrate for interfacing with a printed circuit board (PCB). The chips and the package substrate are housed within an encapsulation material. The bottom surface of the first chip is attached to the package substrate. The top surface of the first chip has a first plurality of landing pads, which serve as a mechanical and electrical interface between the first and second chip. The bottom surface of the second chip has a second plurality of landing pads that serve as a mechanical and electrical interface between the second and first chip. Additionally, the top surface of the second chip has a third plurality of landing pads that serve as a mechanical and electrical interface between the second and third chip.
摘要翻译：提供了具有至少第一，第二和第三芯片的多芯片封装，每个芯片包括顶部和底部表面。多芯片封装还具有用于与印刷电路板（PCB）连接的封装基板。芯片和封装衬底容纳在封装材料内。第一芯片的底表面附接到封装衬底。第一芯片的顶表面具有第一多个着陆焊盘，其用作第一和第二芯片之间的机械和电接口。第二芯片的底表面具有用作第二芯片和第一芯片之间的机械和电接口的第二多个着陆焊盘。此外，第二芯片的顶表面具有用作第二和第三芯片之间的机械和电接口的第三多个着陆焊盘。

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