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1. 发明授权

US06730989B1 Semiconductor package and method 失效
标题翻译：半导体封装及方法
公开(公告)号：US06730989B1
公开(公告)日：2004-05-04
申请号：US09596130
申请日：2000-06-16
申请人： Manfred Reithinger , Mike Killian , Gerd Frankowsky , Oliver Kiehl , Gerhard Mueller , Ernst Stahl , Hartmud Terletzki , Thomas Vogelsang
发明人： Manfred Reithinger , Mike Killian , Gerd Frankowsky , Oliver Kiehl , Gerhard Mueller , Ernst Stahl , Hartmud Terletzki , Thomas Vogelsang
IPC分类号： H01L23544
CPC分类号： H01L23/5382 , H01L23/50 , H01L25/18 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.
摘要翻译：半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。晶片的分数部分具有电连接到芯片的多个电触点。封装还包括其上具有电导体的电介质构件。电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

2. 发明授权

US06815803B1 Multiple chip semiconductor arrangement having electrical components in separating regions 有权
标题翻译：在分离区域中具有电气部件的多芯片半导体布置
公开(公告)号：US06815803B1
公开(公告)日：2004-11-09
申请号：US09596129
申请日：2000-06-16
申请人： Manfred Reithinger , Mike Killian , Gerd Frankowsky , Oliver Kiehl , Gerhard Mueller , Ernst Stahl , Hartmud Terletzki , Thomas Vogelsang
发明人： Manfred Reithinger , Mike Killian , Gerd Frankowsky , Oliver Kiehl , Gerhard Mueller , Ernst Stahl , Hartmud Terletzki , Thomas Vogelsang
IPC分类号： H01L23544
CPC分类号： H01L25/18 , H01L23/50 , H01L23/5382 , H01L27/105 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.
摘要翻译：半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。晶片的分数部分具有电连接到芯片的多个电触点。封装还包括其上具有电导体的电介质构件。电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

3. 发明授权

US07060529B2 Multiple chip semiconductor arrangement having electrical components in separating regions 失效
标题翻译：在分离区域中具有电气部件的多芯片半导体布置
公开(公告)号：US07060529B2
公开(公告)日：2006-06-13
申请号：US10841162
申请日：2004-05-07
申请人： Manfred Reithinger , Mike Killian , Gerd Frankowsky , Oliver Kiehl , Gerhard Mueller , Ernst Stahl , Hartmud Terletzki , Thomas Vogelsang
发明人： Manfred Reithinger , Mike Killian , Gerd Frankowsky , Oliver Kiehl , Gerhard Mueller , Ernst Stahl , Hartmud Terletzki , Thomas Vogelsang
IPC分类号： H01L21/50 , H01L21/30
CPC分类号： H01L25/18 , H01L23/50 , H01L23/5382 , H01L27/105 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.
摘要翻译：半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。晶片的分数部分具有电连接到芯片的多个电触点。封装还包括其上具有电导体的电介质构件。电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

4. 发明申请

US20050001298A1 Multiple chip semiconductor arrangement having electrical components in separating regions 失效
标题翻译：在分离区域中具有电气部件的多芯片半导体布置
公开(公告)号：US20050001298A1
公开(公告)日：2005-01-06
申请号：US10841162
申请日：2004-05-07
申请人： Manfred Reithinger , Mike Killian , Gerd Frankowsky , Oliver Kiehl , Gerhard Mueller , Ernst Stahl , Hartmud Terletzki , Thomas Vogelsang
发明人： Manfred Reithinger , Mike Killian , Gerd Frankowsky , Oliver Kiehl , Gerhard Mueller , Ernst Stahl , Hartmud Terletzki , Thomas Vogelsang
IPC分类号： H01L21/8242 , H01L23/50 , H01L23/538 , H01L25/18 , H01L27/105 , H01L23/544
CPC分类号： H01L25/18 , H01L23/50 , H01L23/5382 , H01L27/105 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.
摘要翻译：半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。晶片的分数部分具有电连接到芯片的多个电触点。封装还包括其上具有电导体的电介质构件。电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

5. 发明授权

US07339841B2 Test mode method and apparatus for internal memory timing signals 有权
标题翻译：用于内部存储器定时信号的测试模式方法和装置
公开(公告)号：US07339841B2
公开(公告)日：2008-03-04
申请号：US11227099
申请日：2005-09-16
申请人： Martin Versen , Klaus Nierle , Oliver Kiehl , Ernst Stahl
发明人： Martin Versen , Klaus Nierle , Oliver Kiehl , Ernst Stahl
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C29/12015 , G11C29/14 , G11C29/50012
摘要： A method of testing internal signals of a memory for timing marginalities which may result in unstable operation includes: delaying internal address signals of the memory by an amount great enough so that data cannot be validly written to and read from memory locations which are accessed by address signals having timing marginalities which are delayed but small enough so that data can be validly written to and read from memory locations which are accessed by address signals not having such timing marginalities which are delayed. Data is then written to and read from memory locations which are accessed by delayed address signals, and a determination is made as to whether the data read from any memory location does not correspond with the data written to such memory location.
摘要翻译：测试存储器的内部信号的方法，其可能导致不稳定的操作的定时边界，包括：将存储器的内部地址信号延迟足够大的量，使得数据不能被有效地写入到存储器位置并从其被地址访问的存储器位置读取具有延迟但足够小的定时边缘的信号，使得数据可以被有效地写入到存储单元中并从存储位置读取，地址信号不具有被延迟的这种定时边缘。然后将数据写入到由延迟的地址信号访问的存储器位置并从其读取，并且确定从任何存储器位置读取的数据是否与写入该存储器位置的数据不对应。

6. 发明申请

US20070064505A1 Test mode method and apparatus for internal memory timing signals 有权
标题翻译：用于内部存储器定时信号的测试模式方法和装置
公开(公告)号：US20070064505A1
公开(公告)日：2007-03-22
申请号：US11227099
申请日：2005-09-16
申请人： Martin Versen , Klaus Nierle , Oliver Kiehl , Ernst Stahl
发明人： Martin Versen , Klaus Nierle , Oliver Kiehl , Ernst Stahl
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C29/12015 , G11C29/14 , G11C29/50012
摘要： A method of testing internal signals of a memory for timing marginalities which may result in unstable operation includes: delaying internal address signals of the memory by an amount great enough so that data cannot be validly written to and read from memory locations which are accessed by address signals having timing marginalities which are delayed but small enough so that data can be validly written to and read from memory locations which are accessed by address signals not having such timing marginalities which are delayed. Data is then written to and read from memory locations which are accessed by delayed address signals, and a determination is made as to whether the data read from any memory location does not correspond with the data written to such memory location.
摘要翻译：测试存储器的内部信号的方法，其可能导致不稳定的操作的定时边界，包括：将存储器的内部地址信号延迟足够大的量，使得数据不能被有效地写入到存储器位置并从其被地址访问的存储器位置读取具有延迟但足够小的定时边缘的信号，使得数据可以被有效地写入到存储单元中并从存储位置读取，地址信号不具有被延迟的这种定时边缘。然后将数据写入到由延迟的地址信号访问的存储器位置并从其读取，并且确定从任何存储器位置读取的数据是否与写入该存储器位置的数据不对应。

7. 发明授权

US06760248B2 Voltage regulator with distributed output transistor 有权
标题翻译：具有分布式输出晶体管的稳压器
公开(公告)号：US06760248B2
公开(公告)日：2004-07-06
申请号：US10267262
申请日：2002-10-09
申请人： Ernst Stahl
发明人： Ernst Stahl
IPC分类号： G11C1124
CPC分类号： G11C7/1066 , G11C5/147 , G11C7/12 , G11C11/4074 , G11C11/4094
摘要： A memory device and method of manufacturing thereof having a voltage regulator with distributed output transistor. A novel approach for the bitline high voltage (VBLH) generation is used to save chip area by allowing narrower power bussing. The output transistor is distributed along the array edge. In addition, the transistor is divided into sections with different channel widths to compensate for current drive losses due to voltage drops along the VDD power bus. The IR-drop on the VBLH line is eliminated, and a constant output voltage is provided along the array edge.
摘要翻译：一种存储器件及其制造方法，具有分布式输出晶体管的电压调节器。利用位线高电压（VBLH）生成的新颖方法可以通过允许较窄的功率总线来节省芯片面积。输出晶体管沿阵列边缘分布。此外，晶体管被分成具有不同沟道宽度的部分，以补偿由于沿VDD电源总线的电压降引起的电流驱动损耗。消除VBLH线上的IR降，沿着阵列边缘提供恒定的输出电压。

8. 发明申请

US20070081366A1 Capacitive coupling assisted voltage switching 审中-公开
标题翻译：电容耦合辅助电压开关
公开(公告)号：US20070081366A1
公开(公告)日：2007-04-12
申请号：US11247335
申请日：2005-10-11
申请人： Ernst Stahl
发明人： Ernst Stahl
IPC分类号： H02M3/18
CPC分类号： H02M3/07
摘要： A system includes a charge pump configured to provide a boosted voltage, a voltage source configured to provide a voltage less than the boosted voltage, and a load. The system includes a coupling capacitance coupled to the load, a first switch coupled between the charge pump and the load, and a second switch coupled between the voltage source and the load.
摘要翻译：系统包括被配置为提供升压电压的电荷泵，被配置为提供小于升压电压的电压的电压源和负载。该系统包括耦合到负载的耦合电容，耦合在电荷泵和负载之间的第一开关以及耦合在电压源和负载之间的第二开关。

9. 发明申请

US20090051418A1 DISTRIBUTED VOLTAGE REGULATOR 审中-公开
标题翻译：分布式电压调节器
公开(公告)号：US20090051418A1
公开(公告)日：2009-02-26
申请号：US11842254
申请日：2007-08-21
申请人： DIETMAR GOGL , Ernst Stahl
发明人： DIETMAR GOGL , Ernst Stahl
IPC分类号： G05F1/10
CPC分类号： G11C5/147 , G05F1/56 , G11C5/025
摘要： An integrated circuit device and a method for providing distributed voltage regulation. The device includes a plurality of memory cell arrays and access circuitry dependent on one or more regulated voltages generated on the device and a plurality of pulsed digital distributed output units configured to generate the one or more regulated voltages. The device also includes a voltage regulator control logic configured to generate one or more control signals to control the distributed output units based, at least in part, on a comparison between one or more reference voltages and the one or more regulated voltages.
摘要翻译：一种集成电路装置和提供分布式电压调节的方法。该装置包括多个存储单元阵列和取决于在该装置上产生的一个或多个调节电压的访问电路以及被配置为产生一个或多个调节电压的多个脉冲数字分布式输出单元。该装置还包括电压调节器控制逻辑，其被配置为至少部分地基于一个或多个参考电压与一个或多个调节电压之间的比较来产生一个或多个控制信号以控制分布式输出单元。

10. 发明授权

US07187599B2 Integrated circuit chip having a first delay circuit trimmed via a second delay circuit 有权
标题翻译：具有通过第二延迟电路修整的第一延迟电路的集成电路芯片
公开(公告)号：US07187599B2
公开(公告)日：2007-03-06
申请号：US11137736
申请日：2005-05-25
申请人： Josef Schnell , Ernst Stahl
发明人： Josef Schnell , Ernst Stahl
IPC分类号： G11C7/00
CPC分类号： G11C29/02 , G01R31/3016 , G01R31/31725 , G01R31/31726 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C29/022 , G11C29/023 , G11C29/028
摘要： An integrated circuit chip including a first delay circuit and a second delay circuit. The first delay circuit has a first delay circuit topology configured to delay a signal a first delay. The second delay circuit has a second delay circuit topology configured to provide a second delay in a circuit loop that is configured to be monitored and provide an oscillating signal. The second delay circuit topology is substantially the same as the first delay circuit topology and the first delay circuit is configured to be trimmed to adjust the first delay based on the second delay and the oscillating signal.
摘要翻译：一种包括第一延迟电路和第二延迟电路的集成电路芯片。第一延迟电路具有第一延迟电路拓扑，其被配置为将信号延迟第一延迟。第二延迟电路具有第二延迟电路拓扑，其被配置为在被配置为被监视并提供振荡信号的电路回路中提供第二延迟。第二延迟电路拓扑与第一延迟电路拓扑基本相同，并且第一延迟电路被配置为被修整以基于第二延迟和振荡信号调整第一延迟。

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