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1. 发明授权

US5357469A Method for data transfer for a semiconductor memory using combined control signals to provide high speed transfer, and semiconductor memory for carrying out the method 失效
标题翻译：使用组合控制信号提供高速传输的半导体存储器的数据传输方法和用于执行该方法的半导体存储器
公开(公告)号：US5357469A
公开(公告)日：1994-10-18
申请号：US769172
申请日：1991-09-30
申请人： Diether Sommer , Dominique Savignac
发明人： Diether Sommer , Dominique Savignac
IPC分类号： G11C11/401 , G11C7/10 , G11C7/22 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1033
摘要： In a method for data transfer between a plurality of memory cells and at least one input/output terminal of a semiconductor memory, and a semiconductor memory for carrying out the method, a memory cell address is defined by a control signal for a data transfer. A data transfer operation from or to the memory cells is controlled with an address control signal and an output enable control signal for defining a memory cell address with one of the two signals. A data transfer operation is subsequently initiated at a given logical linkage of the two control signals. An ensuing data transfer is controlled with the other of the two control signals.
摘要翻译：在多个存储器单元与半导体存储器的至少一个输入/输出端子之间的数据传输方法和用于执行该方法的半导体存储器中，存储器单元地址由用于数据传送的控制信号定义。使用地址控制信号和输出使能控制信号来控制来自或到存储器单元的数据传送操作，以用两个信号中的一个来定义存储单元地址。随后在两个控制信号的给定逻辑连接处启动数据传送操作。随后的数据传输由两个控制信号中的另一个控制。

2. 发明授权

US5546036A Circuit array for amplifying and holding data with different supply 失效
标题翻译：用于放大和保存不同电源的数据的电路阵列
公开(公告)号：US5546036A
公开(公告)日：1996-08-13
申请号：US376683
申请日：1995-01-23
申请人： Diether Sommer , Dominique Savignac , Dieter Gleis
发明人： Diether Sommer , Dominique Savignac , Dieter Gleis
IPC分类号： G11C7/06 , G11C7/10 , G11C11/4093 , H03K3/286
CPC分类号： G11C11/4093 , G11C7/065 , G11C7/1051
摘要： A circuit array for amplifying and holding data with different supply voltages includes a first flip-flop being constructed in MOS technology for receiving a low supply voltage and data with a low supply voltage. The first flip-flop has output terminals. A second flip-flop being constructed in MOS technology receives a high supply voltage. The second flip-flop has a load segment and output terminals. At least one additional MOS transistor is connected in series with each of the output terminals of the second flip-flop between the load segment and ground. The at least one additional MOS transistor each has a gate terminal being connected to a respective one of the output terminals of the first flip-flip. A device for activating the first and second flip-flops is triggered for amplifying and holding the data to activate the first flip-flop and to activate the second flip-flop after a time delay.
摘要翻译：用于放大和保持具有不同电源电压的数据的电路阵列包括以MOS技术构造的用于接收低电源电压的第一触发器和具有低电源电压的数据。第一个触发器具有输出端子。以MOS技术构造的第二个触发器接收高电源电压。第二个触发器具有负载段和输出端。至少一个额外的MOS晶体管与负载段和地之间的第二触发器的每个输出端串联连接。所述至少一个附加MOS晶体管的每个栅极端子连接到第一翻盖的输出端子的相应一个。触发用于激活第一和第二触发器的装置，用于放大和保持数据以激活第一触发器并在时间延迟之后激活第二触发器。

3. 发明授权

US5946249A Circuit configuration for a programmable nonvolatile memory and method for operating the circuit configuration 有权
标题翻译：用于可编程非易失性存储器的电路配置和用于操作电路配置的方法
公开(公告)号：US5946249A
公开(公告)日：1999-08-31
申请号：US145212
申请日：1998-08-31
申请人： Georg Georgakos , Thomas Kern , Diether Sommer , Thomas Zettler
发明人： Georg Georgakos , Thomas Kern , Diether Sommer , Thomas Zettler
IPC分类号： G11C16/10 , G11C29/28 , G11C13/00
CPC分类号： G11C29/28 , G11C16/10
摘要： A circuit configuration for a programmable nonvolatile memory having memory cells organized in rows and columns, includes a programming circuit which contains a first device for testing purposes that applies a programming current to a first predetermined number of memory cells in parallel for a first predetermined time period. During a second predetermined time period, the device thereupon connects a second predetermined number, which is greater than the first number, in parallel an applies the programming current to them. A method is provided for operating the circuit configuration.
摘要翻译：一种用于具有以行和列组织的存储器单元的可编程非易失性存储器的电路配置，包括编程电路，其包含用于测试目的的第一设备，用于将编程电流并行地施加到第一预定数量的存储器单元达第一预定时间段。在第二预定时间段期间，该装置在其上并联连接大于第一数目的第二预定数量并行编程电流。提供了一种用于操作电路配置的方法。

4. 发明申请

US20070230115A1 Memory module 审中-公开
标题翻译：内存模块
公开(公告)号：US20070230115A1
公开(公告)日：2007-10-04
申请号：US11707741
申请日：2007-02-16
申请人： Stephan Dobritz , Diether Sommer , Harald Grune
发明人： Stephan Dobritz , Diether Sommer , Harald Grune
IPC分类号： H05K7/20 , H05K7/02
CPC分类号： H01L23/3675 , H01L25/0657 , H01L2224/16 , H01L2225/06517 , H01L2225/06582 , H01L2225/06589 , H01L2924/01004 , H01L2924/0102 , H05K1/0203 , H05K3/284
摘要： A memory module includes a printed circuit board having a lateral contact portion and a plurality of memory chips being electrically coupled to the printed circuit board and arranged side-by-side at least one printed circuit board assembly side. An encapsulating-covering element is formed on the printed circuit board at the at least one printed circuit board assembly side. Furthermore, the plurality of memory chips are embedded in the encapsulating-covering element.
摘要翻译：存储器模块包括具有横向接触部分的印刷电路板和多个存储器芯片，其电连接到印刷电路板并并排设置在至少一个印刷电路板组件侧。封装覆盖元件形成在印刷电路板上的至少一个印刷电路板组装侧。此外，多个存储器芯片嵌入在封装覆盖元件中。

5. 发明授权

US06628152B1 Method for monitoring a proper functioning of an integrated circuit 有权
标题翻译：监控集成电路正常功能的方法
公开(公告)号：US06628152B1
公开(公告)日：2003-09-30
申请号：US09510640
申请日：2000-02-22
申请人： Thomas Kern , Diether Sommer
发明人： Thomas Kern , Diether Sommer
IPC分类号： H03L700
CPC分类号： G06F11/0754 , G06F1/28 , G11C5/143
摘要： A proper functioning of an integrated circuit is monitored by monitoring a supply voltage of the integrated circuit. Dips in the supply voltage are ascertained. A signaling of the dips in the supply voltage is only effected if the supply voltage falls below a given voltage for a given minimum duration. As a result, the reliability of the integrated circuit is increased.
摘要翻译：通过监视集成电路的电源电压来监视集成电路的正常工作。确定供电电压下降。只有在给定的最小持续时间内电源电压低于给定的电压时，才能对电源电压中的下降信号进行。结果，集成电路的可靠性提高。

6. 发明授权

US5657279A Redundant circuit configuration for an integrated semiconductor memory 失效
标题翻译：集成半导体存储器的冗余电路配置
公开(公告)号：US5657279A
公开(公告)日：1997-08-12
申请号：US514602
申请日：1995-08-14
申请人： Dominique Savignac , Diether Sommer , Oliver Kiehl
发明人： Dominique Savignac , Diether Sommer , Oliver Kiehl
IPC分类号： G11C29/00 , G11C29/04 , G11C8/00
CPC分类号： G11C29/806 , G11C29/812
摘要： A redundant circuit configuration for an integrated semiconductor memory has normal and redundant memory cells, in which addresses of arbitrary groups of memory cells of the memory are formed from a first partial address and a second partial address. M fixedly programmable address circuits, where M.gtoreq.1, are each assigned to one of the first partial addresses. Each fixedly programmable address circuit in an activated state has the second partial address of a group of normal memory cells to be replaced and has a first output at which an activation signal is applied in the activated state of the address circuit if the first partial address applied to the circuit configuration matches the first partial address assigned to the address circuit. One address comparator is common to all of the address circuits and has a first output. The comparator compares the second partial address stored in memory in one of the address circuits with the applied second partial address, at the applied activation signal of the one address circuit. The comparator supplies an enable signal at the first output of the address comparator if the two partial addresses match. Redundance decoders are triggered by the enable signal.
摘要翻译：用于集成半导体存储器的冗余电路配置具有正常和冗余的存储单元，其中存储器的任意存储单元组的地址由第一部分地址和第二部分地址形成。 M个固定可编程地址电路，其中M> / = 1，每个分配给第一部分地址之一。处于激活状态的每个固定可编程地址电路具有要被替换的一组正常存储器单元的第二部分地址，并且具有第一输出，在第一输出处，如果应用了第一部分地址，则在激活状态下施加激活信号电路配置匹配分配给地址电路的第一部分地址。一个地址比较器对于所有地址电路是公共的，并且具有第一输出。所述比较器在所述一个地址电路的所施加的激活信号上比较存储在其中一个地址电路中的所述第二部分地址与所施加的第二部分地址。如果两个部分地址匹配，比较器将在地址比较器的第一个输出端提供使能信号。冗余解码器由使能信号触发。

7. 发明授权

US5457655A Column redundance circuit configuration for a memory 失效
标题翻译：存储器的列冗余电路配置
公开(公告)号：US5457655A
公开(公告)日：1995-10-10
申请号：US198502
申请日：1994-02-17
申请人： Dominique Savignac , Jurgen Weidenhoefer , Diether Sommer
发明人： Dominique Savignac , Jurgen Weidenhoefer , Diether Sommer
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/83
摘要： A column redundance circuit configuration for a memory includes a memory blocks with memory cells disposed in x lines and y columns. Redundant memory cells are disposed in b lines and c columns. A column decoder and c redundant column decoders are provided. Each column decoder is assigned to a respective one of the c redundant columns of each of the memory blocks. D encoding elements each have an address decoding device for assigning it to an arbitrary memory block.
摘要翻译：用于存储器的列冗余电路配置包括具有设置在x行和y列中的存储单元的存储器块。冗余存储单元布置在b行和c列中。提供列解码器和c冗余列解码器。每个列解码器被分配给每个存储器块的c个冗余列中的相应一个。 D编码元件各自具有用于将其分配给任意存储块的地址解码装置。

8. 发明授权

US5444392A CMOS input stage 失效
标题翻译： CMOS输入级
公开(公告)号：US5444392A
公开(公告)日：1995-08-22
申请号：US128529
申请日：1993-09-29
申请人： Diether Sommer , Dominique Savignac
发明人： Diether Sommer , Dominique Savignac
IPC分类号： G01R31/28 , H03K17/00 , H03K17/30 , H03K19/00 , H03K19/0175 , H03K19/0185 , H03K19/0948 , H03K17/16
CPC分类号： H03K19/018585 , H03K19/0027
摘要： A CMOS input stage for operation with a supply voltage selectively having a first value or a second higher value, includes a supply voltage terminal selectively receiving a first value or a second value of a supply voltage during operation, a reference potential terminal, and an input terminal. A first field effect transistor of a first conduction type has a load path and a gate terminal, and a second field effect transistor of a second conduction type has a load path and a gate terminal. The load paths of the field effect transistors are connected in series between the supply voltage terminal and the reference potential terminal. The gate terminals of the field effect transistors are connected to the input terminal. A control device adjusts a resistance of the load path of at least one of the field effect transistors as a function of a particular value selected for the supply voltage.
摘要翻译：用于以选择性地具有第一值或第二较高值的电源电压进行操作的CMOS输入级包括在运行期间选择性地接收电源电压的第一值或第二值的电源电压端子，参考电位端子和输入终奌站。第一导电类型的第一场效应晶体管具有负载路径和栅极端子，第二导电类型的第二场效应晶体管具有负载路径和栅极端子。场效应晶体管的负载路径串联连接在电源电压端子和参考电位端子之间。场效应晶体管的栅极端子连接到输入端子。控制装置根据为电源电压选择的特定值来调整至少一个场效应晶体管的负载路径的电阻。

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