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1. 发明授权

US09400708B2 Integrated circuit and method of detecting a data integrity error 有权
标题翻译：集成电路和检测数据完整性错误的方法
公开(公告)号：US09400708B2
公开(公告)日：2016-07-26
申请号：US14483262
申请日：2014-09-11
申请人： Dirk Wendel , Michael Rohleder , Rolf Schlagenhaft
发明人： Dirk Wendel , Michael Rohleder , Rolf Schlagenhaft
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/079 , G06F11/0736 , G06F11/0751 , G06F11/0772
摘要： An integrated circuit comprises a write bus coupled to a register for storing control data. A storage unit is arranged to store reference signature data encoding a reference collective state of the register. First logic circuitry generates actual signature data encoding the actual collective state of the register. Second logic circuitry is coupled to the storage unit, receives the actual signature data and compares the actual signature data with the reference signature data. The second logic circuitry comprises an alert output to provide an alert signal in response to the comparison identifying a difference between the actual signature data and the reference signature data, thereby ensuring detection of a data integrity error in respect of the register. An alert inhibitor comprises a control input and is responsive to the control input and arranged to inhibit selectively onward propagation of the alert signal from the alert output.
摘要翻译：集成电路包括耦合到用于存储控制数据的寄存器的写总线。存储单元被布置为存储编码寄存器的参考集合状态的参考签名数据。第一逻辑电路生成编码寄存器的实际集体状态的实际签名数据。第二逻辑电路耦合到存储单元，接收实际签名数据并将实际签名数据与参考签名数据进行比较。第二逻辑电路包括警报输出，以响应于比较识别实际签名数据和参考签名数据之间的差异来提供警报信号，从而确保检测关于该寄存器的数据完整性错误。警报抑制器包括控制输入并且响应于控制输入并被布置成禁止警报信号从警报输出中选择性地向前传播。

2. 发明授权

US07098964B2 Apparatus and method for slope-enhancement of signal transitions in television pictures 有权
公开(公告)号：US07098964B2
公开(公告)日：2006-08-29
申请号：US10108232
申请日：2002-03-26
申请人： Peter Rieder , Marko Hahn , Günter Scheffler , Dirk Wendel
发明人： Peter Rieder , Marko Hahn , Günter Scheffler , Dirk Wendel
IPC分类号： H04N5/21 , H04N1/409
CPC分类号： H04N5/208
摘要： A time-discrete picture signal is formed from an analog picture signal, such as a luminance signal or a chrominance signal. Corresponding to the time-discrete picture signal, a time-discrete filter signal is formed, specifically a so-called “peaking signal,” which has a sequence of peaking signal values, of which one value each is associated with one signal value of the time-discrete picture signal. The discrete peaking signal is formed by a digital peaking filter from the discrete picture signal or by an analog peaking filter from the analog picture signal during subsequent sampling of the analog peaking signal. The peaking filter increases the amplitude of selected frequency components of the picture signal.

3. 发明授权

US09507373B2 Oscillator circuit and method of generating a clock signal 有权
标题翻译：振荡电路和产生时钟信号的方法
公开(公告)号：US09507373B2
公开(公告)日：2016-11-29
申请号：US14899170
申请日：2013-07-04
申请人： Hubert Bode , Dirk Wendel
发明人： Hubert Bode , Dirk Wendel
IPC分类号： G06F1/04 , G06F1/08 , H03K3/0231 , H03K3/023
CPC分类号： G06F1/08 , H03K3/023 , H03K3/0231
摘要： An oscillator circuit of the type comprising a flip-flop for generating a clock signal and two comparators for comparing a reference voltage with the voltage across a first capacitor which is charged during a first cycle of the clock signal and the voltage across a second capacitor which is charged during a second cycle of a clock signal provides a means for removing the effects of any offset in either comparator. This is achieved by reversing the inputs of the comparators for each cycle of the output frequency. Thus an offset in a comparator which would increase the clock period on one cycle will reduce the period of the next cycle by the same amount. As a net result, the period of time over two clock periods will stay constant regardless of any offset drift in a comparator.
摘要翻译：一种振荡器电路，包括用于产生时钟信号的触发器和用于将参考电压与在第一电容器的第一周期期间充电的第一电容器两端的电压进行比较的两个比较器，以及跨越第二电容器的电压在时钟信号的第二周期期间被充电提供了用于消除任一比较器中任何偏移的影响的装置。这是通过在输出频率的每个周期反转比较器的输入来实现的。因此，将在一个周期上增加时钟周期的比较器中的偏移将使下一个周期的周期减少相同的量。作为最终结果，无论比较器中有任何偏移漂移，两个时钟周期的时间段将保持不变。

4. 发明授权

US07532216B2 Method of scaling a graphic character 有权
标题翻译：缩放图形字符的方法
公开(公告)号：US07532216B2
公开(公告)日：2009-05-12
申请号：US11297123
申请日：2005-12-07
申请人： Dirk Wendel , Ulrich Langenkamp , Marko Hahn
发明人： Dirk Wendel , Ulrich Langenkamp , Marko Hahn
IPC分类号： G06T11/00 , G09G5/26 , G09G5/00
CPC分类号： G06T3/40
摘要： A graphic character that has a character matrix with a number of character units that are indivisible at least in either a horizontal direction or a vertical direction is scaled by dividing the character matrix into one first and at least one second character segment, each comprising at least one of the character units. The first character segment is symmetrically scaled using a first scaling factor and the second character segment is scaled using a second scaling factor different from the first scaling factor.
摘要翻译：具有至少在水平方向或垂直方向上不可分割的具有多个字符单元的字符矩阵的图形字符通过将字符矩阵划分成一个第一和至少一个第二字符段来缩放，每个字符段至少包括其中一个角色单位。使用第一缩放因子对第一字符段进行对称缩放，并且使用不同于第一缩放因子的第二缩放因子来缩放第二字符段。

5. 发明授权

US06950146B1 Method and circuit for inserting a picture into a video picture 失效
标题翻译：将图像插入视频图像的方法和电路
公开(公告)号：US06950146B1
公开(公告)日：2005-09-27
申请号：US09979079
申请日：2000-05-19
申请人： Maik Brett , Dirk Wendel , Matthias Burkert
发明人： Maik Brett , Dirk Wendel , Matthias Burkert
IPC分类号： H04N5/44 , H04N5/45 , H04N5/46
CPC分类号： H04N7/0122 , H04N5/45 , H04N21/4316
摘要： In display apparatuses, particularly television receivers and monitors, a video picture can be inserted into a main picture (HB) from a first video signal (VS1), in which a second picture (ZB) from a second video signal (VS2) has a first picture format and is composed of picture lines (BZ) and filling lines (FZ). The picture lines (BZ) forming a sub-picture (UB) with the second picture format is adjoined by the filling lines (FZ) in the vertical picture direction. The second picture format of the sub-picture (UB) is determined and the determined second picture format is used for determining the filling lines (FZ). The picture lines (BZ) and a portion of the filling lines (FZ) are inserted as an insertion picture into the main picture (HB). Additional insertions (OSD) from an additional signal, which at least partly lie within the filling lines (FZ), is displaced into the sub-picture (UB).
摘要翻译：在显示装置，特别是电视接收机和监视器中，视频图像可以从第一视频信号（VS 1）插入到主图像（HB）中，其中来自第二视频信号（VS2）的第二图像（ZB）具有第一图像格式并且由图像行（BZ）和填充线（FZ）组成。形成具有第二图像格式的子图像（UB）的图像行（BZ）在垂直图像方向上与填充线（FZ）相邻。确定子图像（UB）的第二图像格式，并且确定第二图像格式用于确定填充线（FZ）。图像线（BZ）和填充线（FZ）的一部分作为插入图像插入到主图像（HB）中。至少部分位于填充线（FZ）内的附加信号的附加插入（OSD）被移位到子图像（UB）中。

6. 发明授权

US06762800B1 Circuit for controlling luminance signal amplitude 失效
标题翻译：用于控制亮度信号幅度的电路
公开(公告)号：US06762800B1
公开(公告)日：2004-07-13
申请号：US09786451
申请日：2001-06-11
申请人： Xiaoning Nie , Dirk Wendel , Maik Brett
发明人： Xiaoning Nie , Dirk Wendel , Maik Brett
IPC分类号： H04N520
CPC分类号： H04N5/20 , H04N5/45
摘要： The circuit takes into account whether the image on a screen is too bright, whether more than one specific number of pixels have a luminance value that is greater than a given peak value and whether this condition is met in more than one specific number of lines in a picture and in more than one specific number of successive images with one such number of lines.
摘要翻译：该电路考虑了屏幕上的图像是否太亮，多于一个特定数量的像素是否具有大于给定峰值的亮度值，以及该条件是否满足多于一个特定数量的行一张照片和多于一个特定数量的连续图像，其中一条这样的行数。

7. 发明授权

US09641809B2 Circuit arrangement and method for processing a digital video stream and for detecting a fault in a digital video stream, digital video system and computer readable program product 有权
公开(公告)号：US09641809B2
公开(公告)日：2017-05-02
申请号：US14224167
申请日：2014-03-25
申请人： Michael Andreas Staudenmaier , Victor-Hugo Osornio Lopez , Dirk Wendel
发明人： Michael Andreas Staudenmaier , Victor-Hugo Osornio Lopez , Dirk Wendel
IPC分类号： H04N19/65 , H04N7/18 , H04N19/89
CPC分类号： H04N7/183 , H04N19/89
摘要： The present invention relates to a circuit arrangement for processing a digital video stream, the circuit arrangement comprising: an input interface for receiving a digital video stream, a processing circuit which is arranged to process the digital video stream, a hang-up detecting circuit for detecting a fault in the processed digital video stream, the hang-up detecting circuit comprising: a checksum generating circuit which is arranged to generate checksums for the frames of the processed digital video stream, a memory for storing generated checksums and an analyzing device arranged to compare a currently generated checksum to a plurality of corresponding checksums of preceding frames stored in the memory and to generate an error signal if at least one predefined amount of compared checksums are matching. The present invention also relates to a digital video system, a method for processing a digital video stream and a computer readable program product.

8. 发明授权

US07095446B2 Method and device for phase correction of a vertically distorted digital image 有权
标题翻译：用于垂直失真数字图像的相位校正的方法和装置
公开(公告)号：US07095446B2
公开(公告)日：2006-08-22
申请号：US10048730
申请日：2001-05-25
申请人： Mirko Hahn , Guenter Scheffler , Dirk Wendel
发明人： Mirko Hahn , Guenter Scheffler , Dirk Wendel
IPC分类号： H03L7/00
CPC分类号： H04N5/2628 , H04N3/2335
摘要： A device for correcting the phase of a vertically distorted digital picture receives picture data and a vertical phase correction signal, and assigns lines of the digital picture to a first half picture and to a second half picture. The lines of the second half picture are phase corrected with respect to the first half picture and the first and second half pictures are displayed sequentially. The phase correction is determined in response an increment signal that describes the change of an imaging factor in the veritcal direction of the digital picture on a line-by-line basis and a picture position signal indicative of whether the first half picture or the second half picture is being output.
摘要翻译：用于校正垂直失真的数字图像的相位的装置接收图像数据和垂直相位校正信号，并将数字图像的行分配给前半部分图像和第二半图像。第二半图像的行相对于第一半图像被相位校正，并且顺序地显示第一和第二半图像。相位校正是响应于逐行地描述数字图像的验证方向上的成像因子的变化的增量信号和指示上半部分图像或后半部分的图像位置信号图片正在输出。

9. 发明授权

US07002635B1 Method for superimposing pictures 失效
标题翻译：叠加图像的方法
公开(公告)号：US07002635B1
公开(公告)日：2006-02-21
申请号：US09914664
申请日：2000-03-03
申请人： Maik Brett , Matthias Burkert , Dirk Wendel
发明人： Maik Brett , Matthias Burkert , Dirk Wendel
IPC分类号： H04N5/45
CPC分类号： H04N5/45 , H04N21/4316
摘要： In the case of picture insertions, such as picture-in-picture, for example, fluctuations in the line duration are manifested in position displacements relative to the desired position of the inserted pictures.In order to prevent position displacements in the horizontal direction, it is provided that the insertion position is corrected in a manner dependent on a determined line duration. The method according to the invention is suitable in particular for picture-in-picture insertions in television receivers.
摘要翻译：在诸如画中画的图像插入的情况下，例如，线持续时间的波动表现在相对于插入的图像的期望位置的位置位移。

10. 发明授权

US06532483B1 Filter for time division multiplex filtering of a plurality of data trains, and operating methods therefor 失效
标题翻译：用于多个数据列的时分多路复用滤波的滤波器及其操作方法
公开(公告)号：US06532483B1
公开(公告)日：2003-03-11
申请号：US09536169
申请日：2000-03-27
申请人： Dirk Wendel , Sönke Mehrgardt , Xiaoning Nie
发明人： Dirk Wendel , Sönke Mehrgardt , Xiaoning Nie
IPC分类号： G06F1710
CPC分类号： H03H17/0292 , H03H17/06 , H03H17/0621 , H03H2218/06
摘要： A filter for filtering n data trains by time division multiplexing includes data channels for receiving data train values, registers subdivided into n groups for buffer storage of the data train values or derived values, and adders each having inputs. Each of the n groups is connected to one of the data channels. The adders and the registers alternatively connect to form a chain. The first input of respective adders connected upstream of a respective register of an ith group (0≦i≦n−1) has a connection to respective data channels assigned to the ith group, and the second input is connected to a respective register of a group having a number (i−1)mod n without an intervening register of another group. The filter is used to parallelly decimate data trains by a common factor. A filter configuration includes the filter and two multipliers. A method is also provided.
摘要翻译：用于通过时分复用滤波n个数据列的滤波器包括用于接收数据序列值的数据信道，被分成n组的寄存器，用于数据序列值或导出值的缓冲存储，以及每个具有输入的加法器。 n组中的每一个连接到其中一个数据通道。加法器和寄存器交替连接形成链。连接在第i组的相应寄存器的上游的相应加法器的第一输入（0 <= i <= n-1）具有与分配给第i组的相应数据通道的连接，并且第二输入连接到相应的寄存器具有数字（i-1）mod n的组，而没有另一组的中间寄存器。该滤波器用于通过共同因素并行抽取数据列。滤波器配置包括滤波器和两个乘法器。还提供了一种方法。

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