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1. 发明授权

US07225383B1 System and method for enhancing communication between devices in a computer system 有权
标题翻译：用于增强计算机系统中的设备之间的通信的系统和方法
公开(公告)号：US07225383B1
公开(公告)日：2007-05-29
申请号：US09487529
申请日：2000-01-19
申请人： David Wood , Robert C. Zak, Jr. , Monica Wong-Chan , Christopher J. Jackson , Thomas P. Webber , Mark D. Hill
发明人： David Wood , Robert C. Zak, Jr. , Monica Wong-Chan , Christopher J. Jackson , Thomas P. Webber , Mark D. Hill
IPC分类号： G06F11/00
CPC分类号： G06F13/4265 , Y10S707/99931
摘要： An apparatus and method for resending a request in a computer system using a delay value is provided. In response to receiving a request, a target device in a computer system may detect that it is temporarily unable to process the request. The target device can send a response to the sending device to indicate that it is temporarily unavailable. The response can include a delay value that can provide a hint to the sending device as to when to resend the request. The target device may generate the delay value according to the type of condition that is causing it to be temporarily unavailable. The delay value may be generated according to a static heuristic or a dynamic algorithm based on previous temporarily unavailable conditions. The delay value may also be used by an error recovery mechanism where a sending device exceeds a retry limit for a particular request.
摘要翻译：提供了一种使用延迟值在计算机系统中重新发送请求的装置和方法。响应于接收到请求，计算机系统中的目标设备可以检测到它暂时不能处理请求。目标设备可以向发送设备发送响应，以指示它暂时不可用。响应可以包括可以向发送设备提供关于何时重新发送请求的提示的延迟值。目标设备可以根据导致其暂时不可用的条件类型来生成延迟值。可以根据基于先前临时不可用条件的静态启发式或动态算法生成延迟值。延迟值还可以由发送设备超过特定请求的重试限制的错误恢复机制使用。

2. 发明授权

US6061772A Split write data processing mechanism for memory controllers utilizing inactive periods during write data processing for other transactions 失效
标题翻译：在其他交易的写入数据处理期间，利用非活动期间分割写入数据处理机制
公开(公告)号：US6061772A
公开(公告)日：2000-05-09
申请号：US884844
申请日：1997-06-30
申请人： Thomas P. Webber , Ketan P. Joshi
发明人： Thomas P. Webber , Ketan P. Joshi
IPC分类号： G06F13/16 , G06F12/00
CPC分类号： G06F13/1673
摘要： A memory controller provides fast processing of sequential split memory access instructions which include a split write instruction. In a split write instruction, a write address and write request are provided to the memory controller in an initial transaction while write data can be provided to the memory controller in a later transaction. The memory controller includes a sideline buffer, for buffering incomplete write instructions, and memory control logic which ensures proper execution of the sequential memory access instructions. Upon receiving an incomplete write instruction, the memory control logic stores the corresponding write request and write address in the sideline buffer until corresponding write data becomes available. The memory control logic determines if there is overlap between memory space to be occupied by an initial write data block and memory space to be occupied by a subsequent read data block or second write data block, of a read or write instruction respectively. By using a sideline buffer to temporarily store incomplete write instructions, processing of sequential memory access instructions can continue subject to observance of memory access conflict rules.
摘要翻译：存储器控制器提供包括分离写入指令的顺序分割存储器访问指令的快速处理。在分割写入指令中，写入地址和写入请求在初始事务中被提供给存储器控制器，而写入数据可以在稍后的事务中提供给存储器控制器。存储器控制器包括用于缓冲不完整写入指令的副线缓冲器以及确保顺序存储器访问指令的正确执行的存储器控制逻辑。在接收到不完整的写入指令时，存储器控制逻辑将对应的写入请求和写入地址存储在边线缓冲器中，直到相应的写入数据变得可用。存储器控制逻辑确定分别由读写指令分别由初始写数据块占据的存储器空间与要由后续读数据块或第二写数据块占据的存储空间之间是否重叠。通过使用副线缓冲器临时存储不完整的写指令，顺序存储器访问指令的处理可以继续遵守存储器访问冲突规则。

3. 发明授权

US5815023A Unbalanced multiplexer and arbiter combination 失效
标题翻译：不平衡多路复用器和仲裁器组合
公开(公告)号：US5815023A
公开(公告)日：1998-09-29
申请号：US821266
申请日：1997-03-20
申请人： Thomas P. Webber , Ting-Chuck Chiang
发明人： Thomas P. Webber , Ting-Chuck Chiang
IPC分类号： G06F7/00 , G06F13/362 , G06F13/364 , H03K17/62
CPC分类号： G06F13/364
摘要： A method and apparatus for high speed signal path arbitration and transfer of a plurality of source signals to a destination signal path, is provided. An arbiter system includes an arbiter and a multiplexer. The multiplexer includes a plurality of n inputs each coupled to receive a source signal from one of a plurality of source signal paths and an output coupled to provide an output signal to the destination signal path. The multiplexer is controlled by a plurality of n select signal values received from the arbiter. The arbiter is coupled to receive a plurality of request signal values which prompt the arbiter to control the multiplexer to pass one of the source signals to the destination signal path. The multiplexer includes a plurality of n multiplexer signal paths each extending from one of n multiplexer inputs to the multiplexer output. Time characteristics of each of the n multiplexer signal paths are unequal. Request signal transfer times are required by the arbiter for providing a select signal value corresponding to each of the n request signal values. In the present invention, the time characteristics of the multiplexer signal paths and the request signal transfer times are matched such that an arbiter system transfer time, required to process one of the request signal values over the arbiter and pass a source signal from the corresponding multiplexer input to the multiplexer output, is approximately equal for each of the inputs to the multiplexer.
摘要翻译：提供了一种用于高速信号路径仲裁和将多个源信号传送到目的地信号路径的方法和装置。仲裁系统包括仲裁器和多路复用器。多路复用器包括多个n个输入端，每个n个输入端被耦合以从多个源极信号路径中的一个接收源极信号，以及耦合到输出信号到目的地信号路径的输出端。多路复用器由从仲裁器接收的多个n个选择信号值控制。仲裁器被耦合以接收多个请求信号值，其提示仲裁器控制多路复用器将源信号之一传递到目的地信号路径。多路复用器包括多个n个多路复用器信号路径，每个多路复用器信号路径从n个多路复用器输入中的一个延 n个多路复用器信号路径中的每一个的时间特性是不相等的。仲裁器需要请求信号传送时间，以提供与n个请求信号值中的每一个对应的选择信号值。在本发明中，多路复用器信号路径的时间特性和请求信号传送时间相匹配，使得仲裁器系统传输时间是处理仲裁器之一的请求信号值之一并通过相应复用器的源信号对多路复用器输出的输入大致相等于多路复用器的每个输入。

4. 发明授权

US5687079A Method and apparatus for improved control of computer cooling fan speed 失效
标题翻译：改善计算机冷却风扇转速控制的方法和装置
公开(公告)号：US5687079A
公开(公告)日：1997-11-11
申请号：US457555
申请日：1995-06-01
申请人： Robert M. Bauer , Thomas P. Webber
发明人： Robert M. Bauer , Thomas P. Webber
IPC分类号： G06F1/20 , G06F1/32 , H05K7/20
CPC分类号： G06F1/3215 , G06F1/206 , G06F1/3203 , G06F1/325 , G06F1/3265 , Y02B60/1242 , Y02B60/1275
摘要： A computer has an AC power outlet, preferably a standard AC outlet, into which periperhal devices, such as video monitors, can be plugged. It can turn this outlet on and off under program control, preferably by writing an outlet control signal to an I/O port which controls the outlet. A activity monitor, preferably in software, generates outlet control signals when one or more of the computer's peripheral devices have been inactive for more than a predetermined time. In some embodiments, the activity monitor turn off different parts of the computer in response to different types of inactivity. Preferably the computer can turn off the AC outlet without turning off the computer as a whole, and preferably it turns off the AC power outlet when the computer is turned off. Normally the AC outlet and its switching circuitry are part of the computer's power supply. The invention also includes a computer which has one or more electrically powered fans and an I/O port to which its can write to produce different fan speed control signals. A control device varies the fan's speed in response to the different control signals generated by the port. In one embodiment, the computer stores a value in non-volatile memory, such as in a register on its CPU, indicating which fans speed control signal should be generated when the computer is turned on. Preferably the fan-speed-control device also includes a device for measuring air temperature and for controlling fan speed as a function of that temperature, as well as of the fan speed control signal. In some embodiments two fans are so controlled, with the fans being operated at different speeds to prevent audible beating between them.
摘要翻译：计算机具有交流电源插座，最好是标准交流电插座，其中可以插入诸如视频监视器之类的装置。它可以在程序控制下打开和关闭此插座，最好是通过将出口控制信号写入控制插座的I / O端口。活动监视器，优选地在软件中，当计算机的一个或多个外围设备已经不活动超过预定时间时，产生出口控制信号。在一些实施例中，活动监视器响应于不同类型的不活动而关闭计算机的不同部分。优选地，计算机可以在不关闭整个计算机的情况下关闭AC插座，并且优选地，当计算机关闭时，它关闭AC电源插座。通常交流电源插座及其开关电路是计算机电源的一部分。本发明还包括具有一个或多个电动风扇和I / O端口的计算机，其可以写入以产生不同的风扇速度控制信号。控制装置响应于由端口产生的不同控制信号来改变风扇的速度。在一个实施例中，计算机将值存储在诸如其CPU上的寄存器中的非易失性存储器中，指示当打开计算机时应当生成哪个风扇速度控制信号。优选地，风扇速度控制装置还包括用于测量空气温度并用于控制作为该温度的函数的风扇速度以及风扇速度控制信号的装置。在一些实施例中，两个风扇被如此控制，其中风扇以不同的速度操作以防止它们之间的可听见的打击。

5. 发明授权

US06965571B2 Precise error reporting 有权
标题翻译：精确的错误报告
公开(公告)号：US06965571B2
公开(公告)日：2005-11-15
申请号：US09939973
申请日：2001-08-27
申请人： Thomas P. Webber
发明人： Thomas P. Webber
IPC分类号： H04L1/18 , G06F11/00 , G11C29/00 , H04J3/14 , H04L1/00
CPC分类号： H04L1/1854
摘要： A method is provided for the precise reporting of errors in a flow of successive messages. The method includes detecting a transmission error in a message and then deferring the reporting of the transmission error. The method defers the reporting of the transmission error by saving a sequence number for the message and by setting a deferred error flag in a state saved for the flow. The method processes the deferred transmission error when it receives an acknowledgement that completes an immediately preceding message in the flow. When a positive acknowledgement is received, the deferred transmission error is reported. When a negative acknowledgement is received, the deferred transmission error is ignored and a remote error is reported.
摘要翻译：提供了一种用于精确地报告连续消息流中的错误的方法。该方法包括检测消息中的传输错误，然后延迟传输错误的报告。该方法通过保存消息的序列号并通过在为流保存的状态中设置延迟错误标志来延迟传输错误的报告。该方法在收到完成流程中紧邻的消息的确认时处理延迟传输错误。当接收到肯定确认时，报告延迟传输错误。收到否定确认后，延迟传输错误将被忽略，并报告远程错误。

6. 发明授权

US06880057B1 Split write data processing mechanism for memory controllers utilizing inactive periods during write data processing for other transactions 有权
标题翻译：在其他交易的写入数据处理期间，利用非活动期间分割写入数据处理机制
公开(公告)号：US06880057B1
公开(公告)日：2005-04-12
申请号：US09478140
申请日：2000-01-05
申请人： Thomas P. Webber , Ketan P. Joshi
发明人： Thomas P. Webber , Ketan P. Joshi
IPC分类号： G06F13/16 , G06F12/00
CPC分类号： G06F13/1673
摘要： A memory controller provides fast processing of sequential split memory access instructions which include a split write instruction. In a split write instruction, a write address and write request are provided to the memory controller in an initial transaction while write data can be provided to the memory controller in a later transaction. The memory controller includes a sideline buffer, for buffering incomplete write instructions, and memory control logic which ensures proper execution of the sequential memory access instructions. Upon receiving an incomplete write instruction, the memory control logic stores the corresponding write request and write address in the sideline buffer until corresponding write data becomes available. The memory control logic determines if there is overlap between memory space to be occupied by an initial write data block and memory space to be occupied by a subsequent read data block or second write data block, of a read or write instruction respectively. By using a sideline buffer to temporarily store incomplete write instructions, processing of sequential memory access instructions can continue subject to observance of memory access conflict rules.
摘要翻译：存储器控制器提供包括分离写入指令的顺序分割存储器访问指令的快速处理。在分割写入指令中，写入地址和写入请求在初始事务中被提供给存储器控制器，而写入数据可以在稍后的事务中提供给存储器控制器。存储器控制器包括用于缓冲不完整写入指令的副线缓冲器以及确保顺序存储器访问指令的正确执行的存储器控制逻辑。在接收到不完整的写入指令时，存储器控制逻辑将对应的写入请求和写入地址存储在边线缓冲器中，直到相应的写入数据变得可用。存储器控制逻辑确定分别由读写指令分别由初始写数据块占据的存储器空间与要由后续读数据块或第二写数据块占据的存储空间之间是否重叠。通过使用副线缓冲器临时存储不完整的写指令，顺序存储器访问指令的处理可以继续遵守存储器访问冲突规则。

7. 发明授权

US06857030B2 Methods, system and article of manufacture for pre-fetching descriptors 有权
标题翻译：用于预取描述符的方法，系统和制造
公开(公告)号：US06857030B2
公开(公告)日：2005-02-15
申请号：US09949928
申请日：2001-09-12
申请人： Thomas P. Webber
发明人： Thomas P. Webber
IPC分类号： H04L12/66 , G06F3/00 , G06F13/14 , G06F13/28
CPC分类号： H04L12/66
摘要： A system and method for reducing the number of memory accesses by a hardware device to a descriptor memory is disclosed. Methods, systems and articles of manufacture consistent with the present invention enable software to embed a subsequent descriptor it is posting in the descriptor memory into a current descriptor listed in the descriptor memory. Additionally, hardware is configured to transmit a data packet associated with the current descriptor to a recipient device. When hardware receives an acknowledgment message from the recipient device associated with the transmitted data packet, it fetches the current descriptor to update a completion code within the current descriptor using a Read-Modify-Write (RMW) transfer sequence. As part of the RMW memory operation, hardware may use the embedded copy of the subsequent descriptor within the current descriptor to transmit the next data packet associated with the subsequent descriptor. This process avoids hardware from having to fetch the embedded descriptor from the descriptor memory before transmitting the next data packet.
摘要翻译：公开了一种用于将硬件设备的存储器访问次数减少到描述符存储器的系统和方法。与本发明一致的方法，系统和制品使软件能够将其在描述符存储器中发布的后续描述符嵌入描述符存储器中列出的当前描述符。此外，硬件被配置为将与当前描述符相关联的数据分组发送到接收方设备。当硬件从与发送的数据分组相关联的接收设备接收到确认消息时，它使用读 - 修改 - 写（RMW）传送序列取出当前描述符来更新当前描述符内的完成代码。作为RMW存储器操作的一部分，硬件可以使用当前描述符内的后续描述符的嵌入副本来发送与后续描述符相关联的下一个数据分组。该过程避免硬件在传送下一个数据包之前必须从描述符存储器中获取嵌入式描述符。

8. 发明授权

US06347348B1 Buffer management system having an output control configured to retrieve data in response to a retrieval request from a requesting one of a plurality of destinations 失效
标题翻译：具有输出控制的缓冲器管理系统被配置为响应于来自多个目的地中的请求的一个的检索请求来检索数据
公开(公告)号：US06347348B1
公开(公告)日：2002-02-12
申请号：US09108918
申请日：1998-06-30
申请人： Thomas P. Webber
发明人： Thomas P. Webber
IPC分类号： G06F1314
CPC分类号： G06F5/065
摘要： A buffer management subsystem receives data from one or more source processes for transfer to one or more destination processes. The buffer management subsystem includes a buffer memory and a buffer pointer FIFO that associated with one of the destination process. The buffer pointer FIFO stores pointers to buffers in the buffer memory which are available to be used to store data from the source process(es) for transfer to the respective associated destination process. When data is received from a source process for transfer to a destination process, a buffer pointer is retrieved from the buffer pointer FIFO associated with the destination process and used in storing the data in the buffer pointed to by the buffer pointer. When the data is retrieved from the buffer for transfer to the destination process, the buffer pointer to the buffer is returned to the buffer pointer FIFO.
摘要翻译：缓冲器管理子系统从一个或多个源处理接收数据以传送到一个或多个目的地进程。缓冲器管理子系统包括与目的地进程之一相关联的缓冲存储器和缓冲器指针FIFO。缓冲指针FIFO存储指向缓冲存储器中的缓冲器的指针，这些缓冲存储器可用于存储来自源进程的数据以传送到相应的相关联的目的地进程。当从用于传送到目的地处理的源处理接收到数据时，从与目的地处理相关联的缓冲器指针FIFO中检索缓冲器指针，并将其用于将数据存储在由缓冲器指针指向的缓冲器中。当从缓冲器中检索数据以传送到目的地进程时，缓冲区的指针返回到缓冲区指针FIFO。

9. 发明授权

US6035348A Method for managing multiple ordered sets by dequeuing selected data packet from single memory structure 失效
标题翻译：通过从单个存储器结构排队所选数据分组来管理多个有序集的方法
公开(公告)号：US6035348A
公开(公告)日：2000-03-07
申请号：US885010
申请日：1997-06-30
申请人： Thomas P. Webber , Paul A. Wilcox
发明人： Thomas P. Webber , Paul A. Wilcox
IPC分类号： G06F5/10 , G06F12/02
CPC分类号： G06F5/10
摘要： A turnstile FIFO stores data packet from each of a number of separate ordered sets in a generally circular list structure. A select data packet can be dequeued if no older data packet of the same ordered set is stored in the turnstile FIFO. The data packets are stored in the turnstile FIFO in a globally sequential order such that older data packets precede younger data packets regardless of membership in the one or more ordered sets. Turnstile logic determines whether the selected data packet is the oldest data packet of a given ordered set by determining set membership of all older data packets stored in the turnstile FIFO. Older data packets are stored in positions within the turnstile FIFO which precede the position of the selected data packet. If no older data packet is a member of the same set of which the selected data packet is a member, the selected data packet can be dequeued from the turnstile FIFO without violated the sequential order of data packets of the ordered set to which the data packet belong. Conversely, if an older data packet is of the same ordered set, the selected data packet cannot be dequeued. A turnstile FIFO according to the present invention can be particularly useful in routing traffic within a crossbar between various devices.
摘要翻译：十字转门FIFO以大致循环的列表结构存储来自多个单独的有序集合中的每一个的数据分组。如果没有相同有序集的旧数据分组存储在转位FIFO中，则可以将选择数据分组出队。数据分组以全局顺序的顺序存储在十字转换FIFO中，使得较老的数据分组先于较年轻的数据分组，而不管一个或多个有序集合中的隶属关系。旋转门逻辑通过确定存储在十字位FIFO中的所有旧数据分组的集合隶属度来确定所选数据分组是否是给定有序集的最旧数据分组。较旧的数据分组被存储在在所选数据分组的位置之前的十字转置FIFO内的位置。如果没有较旧的数据分组是所选择的数据分组所属的相同集合的成员，则所选择的数据分组可以从十字转换FIFO中排队，而不会违反数据分组的有序集的数据分组的顺序属于。相反，如果较旧的数据包是相同的有序集，则所选择的数据包不能出队。根据本发明的十字门FIFO可以在各种设备之间的交叉开关中路由业务特别有用。

10. 发明授权

US07099345B2 Method and system for buffering a data packet for transmission to a network 有权
公开(公告)号：US07099345B2
公开(公告)日：2006-08-29
申请号：US09995356
申请日：2001-11-27
申请人： Robert A. Dickson , Farroukh Touserkani , Thomas P. Webber , Hugh Kurth
发明人： Robert A. Dickson , Farroukh Touserkani , Thomas P. Webber , Hugh Kurth
IPC分类号： H04L12/54 , H04L12/28
CPC分类号： H04L49/90
摘要： Memory requests and responses thereto include a tag that has a shift value indicating the misalignment between the first byte of required packet data and the first byte of a line of data in memory. A packet buffer controller receiving data with an associated tag uses the shift value to shift the received line of data accordingly. The first line of data for the packet data payload is shifted accordingly and written into the packet buffer. Subsequent lines of data require masking the previous line of data except for the last N bytes where N equals the shift value. The shifted line of data is written over the previous line so that the lower order bytes of the shifted received line of data are written. Then the shifted line of data is written into the next line of the packet buffer. The packet buffer may be divided into sections containing alternating lines of data to increase storage speed.

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