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1. 发明授权

US07225383B1 System and method for enhancing communication between devices in a computer system 有权
标题翻译：用于增强计算机系统中的设备之间的通信的系统和方法
公开(公告)号：US07225383B1
公开(公告)日：2007-05-29
申请号：US09487529
申请日：2000-01-19
申请人： David Wood , Robert C. Zak, Jr. , Monica Wong-Chan , Christopher J. Jackson , Thomas P. Webber , Mark D. Hill
发明人： David Wood , Robert C. Zak, Jr. , Monica Wong-Chan , Christopher J. Jackson , Thomas P. Webber , Mark D. Hill
IPC分类号： G06F11/00
CPC分类号： G06F13/4265 , Y10S707/99931
摘要： An apparatus and method for resending a request in a computer system using a delay value is provided. In response to receiving a request, a target device in a computer system may detect that it is temporarily unable to process the request. The target device can send a response to the sending device to indicate that it is temporarily unavailable. The response can include a delay value that can provide a hint to the sending device as to when to resend the request. The target device may generate the delay value according to the type of condition that is causing it to be temporarily unavailable. The delay value may be generated according to a static heuristic or a dynamic algorithm based on previous temporarily unavailable conditions. The delay value may also be used by an error recovery mechanism where a sending device exceeds a retry limit for a particular request.
摘要翻译：提供了一种使用延迟值在计算机系统中重新发送请求的装置和方法。响应于接收到请求，计算机系统中的目标设备可以检测到它暂时不能处理请求。目标设备可以向发送设备发送响应，以指示它暂时不可用。响应可以包括可以向发送设备提供关于何时重新发送请求的提示的延迟值。目标设备可以根据导致其暂时不可用的条件类型来生成延迟值。可以根据基于先前临时不可用条件的静态启发式或动态算法生成延迟值。延迟值还可以由发送设备超过特定请求的重试限制的错误恢复机制使用。

2. 发明授权

US5862357A Hierarchical SMP computer system 失效
公开(公告)号：US5862357A
公开(公告)日：1999-01-19
申请号：US674688
申请日：1996-07-02
申请人： Erik E. Hagersten , Mark D. Hill
发明人： Erik E. Hagersten , Mark D. Hill
IPC分类号： G06F15/16 , G06F12/06 , G06F15/173 , G06F13/00
CPC分类号： G06F12/0692 , G06F12/0284
摘要： A symmetrical multiprocessing system includes a plurality of nodes interconnected by a hierarchical bus. To allow for the transfer of data between nodes and to restrict the global transfer of local transactions, a plurality of address partitions are defined: global space, local space, remote read space, and remote read and write space. Process private and local data is accessed using local space. Global data is accessed using global space. In one embodiment, a kernel of the operating system is resident in the local space of each node. Because the memory space where the kernel resides is designated as local space, no other nodes can write to, or corrupt, the node's kernel.

3. 发明申请

US20130138892A1 DRAM CACHE WITH TAGS AND DATA JOINTLY STORED IN PHYSICAL ROWS 有权
标题翻译：具有标签和数据的DRAM高速缓存存储在物理路径中
公开(公告)号：US20130138892A1
公开(公告)日：2013-05-30
申请号：US13307776
申请日：2011-11-30
申请人： Gabriel H. Loh , Mark D. Hill
发明人： Gabriel H. Loh , Mark D. Hill
IPC分类号： G06F12/12
CPC分类号： G06F12/0893 , G06F12/0831 , G06F12/0864 , G06F12/0879 , G06F12/123 , Y02D10/13
摘要： A system and method for efficient cache data access in a large row-based memory of a computing system. A computing system includes a processing unit and an integrated three-dimensional (3D) dynamic random access memory (DRAM). The processing unit uses the 3D DRAM as a cache. Each row of the multiple rows in the memory array banks of the 3D DRAM stores at least multiple cache tags and multiple corresponding cache lines indicated by the multiple cache tags. In response to receiving a memory request from the processing unit, the 3D DRAM performs a memory access according to the received memory request on a given cache line indicated by a cache tag within the received memory request. Rather than utilizing multiple DRAM transactions, a single, complex DRAM transaction may be used to reduce latency and power consumption.
摘要翻译：一种用于在计算系统的大型基于行的存储器中高效缓存数据访问的系统和方法。计算系统包括处理单元和集成三维（3D）动态随机存取存储器（DRAM）。处理单元使用3D DRAM作为高速缓存。 3D DRAM的存储器阵列组中的多行的每一行存储由多个高速缓存标签指示的至少多个高速缓存标签和多个对应的高速缓存行。响应于从处理单元接收到存储器请求，3D DRAM根据在所接收的存储器请求中由高速缓存标签指示的给定高速缓存线上的接收到的存储器请求执行存储器访问。可以使用单个复杂DRAM事务来减少等待时间和功耗，而不是利用多个DRAM事务。

4. 发明授权

US07136980B2 Computer system implementing synchronized broadcast using skew control and queuing 有权
标题翻译：计算机系统使用偏移控制和排队实现同步广播
公开(公告)号：US07136980B2
公开(公告)日：2006-11-14
申请号：US10610447
申请日：2003-06-30
申请人： Robert E. Cypher , Mark D. Hill , David A. Wood
发明人： Robert E. Cypher , Mark D. Hill , David A. Wood
IPC分类号： G06F12/06
CPC分类号： G06F12/0833 , G06F12/0813
摘要： A mechanism and method for maintaining cache consistency in computer systems that implements synchronized broadcasts using skew control and queuing. An access right corresponding to a given block allocated in a first active device may be configured to transition in response to a corresponding data packet being received through a data network. Additionally, transitions in ownership of the given block may occur at a different time than the time at which the access right to the given block is changed. To implement synchronized broadcasts, the address and data networks are configured such that a maximum amount of time from when a given broadcast packet conveyed on the address network arrives at a first active device to a time when the given broadcast packet arrives at a second active device is less than or equal to a minimum amount of time from when a data packet sent on the data network from the first active device arrives at the second active device. Each of the active devices may further comprise a queue control circuit coupled to an address-in queue and a data-in queue. The queue control circuit may be configured to prevent processing of a particular data packet that arrived in the data-in queue until all address packets that arrived earlier in the address-in queue are processed.
摘要翻译：用于在使用偏移控制和排队实现同步广播的计算机系统中保持高速缓存一致性的机制和方法。对应于分配在第一有源设备中的给定块的访问权限可以被配置为响应于通过数据网络接收的相应数据分组而转变。此外，给定块的所有权转换可以在与给定块的访问权限改变的时间不同的时间发生。为了实现同步广播，地址和数据网络被配置为使得从地址网络上传送的给定广播分组到达第一活动设备的时间的最大时间到给定广播分组到达第二活动设备小于或等于从第一有源设备在数据网络上发送的数据分组到达第二活动设备时的最小时间量。每个活动设备还可以包括与地址输入队列和数据输入队列耦合的队列控制电路。队列控制电路可以被配置为防止到达数据队列中的特定数据分组的处理，直到在地址队列中较早到达的所有地址分组被处理。

5. 发明授权

US06826660B2 Hierarchical SMP computer system 有权
标题翻译：分层SMP计算机系统
公开(公告)号：US06826660B2
公开(公告)日：2004-11-30
申请号：US10073712
申请日：2002-02-11
申请人： Erik E. Hagersten , Mark D. Hill
发明人： Erik E. Hagersten , Mark D. Hill
IPC分类号： G06F1200
CPC分类号： G06F12/0692 , G06F12/0284
摘要： A symmetrical multiprocessing system includes a plurality of nodes interconnected by a hierarchical bus. To allow for the transfer of data between nodes and to restrict the global transfer of local transactions, a plurality of address partitions are defined: global space, local space, remote read space, and remote read and write space. Process private and local data is accessed using local space. Global data is accessed using global space. In one embodiment, a kernel of the operating system is resident in the local space of each node.
摘要翻译：对称多处理系统包括通过分层总线互连的多个节点。为了允许在节点之间传输数据并限制本地事务的全局传输，定义了多个地址分区：全局空间，本地空间，远程读取空间以及远程读写空间。使用本地空间访问处理私有数据和本地数据。使用全局空间访问全局数据。在一个实施例中，操作系统的内核驻留在每个节点的本地空间中。

6. 发明授权

US06654866B2 Skewed finite hashing function 有权
公开(公告)号：US06654866B2
公开(公告)日：2003-11-25
申请号：US09940172
申请日：2001-08-27
申请人： Erik E. Hagersten , Mark D. Hill
发明人： Erik E. Hagersten , Mark D. Hill
IPC分类号： G06F1210
CPC分类号： G06F11/0712 , G06F11/0724 , G06F11/073 , G06F11/0766 , G06F12/0284 , G06F12/0864 , G06F12/1018 , G06F12/1072 , G06F2212/2542 , G06F2212/272
摘要： A portion of the global memory of a multiprocessing computer system is allocated to each node, called local memory space. Data from a remote node may be copied to local memory space of a node such that accesses to the data may be performed locally rather than globally. The global address of the data is translated to a local physical address for the node to which the data is copied. To reduce the size of the translation tables for converting between global addresses and local physical addresses, multiple pages of the address space are mapped to an entry in a translation table. To decrease the probability that an entry is not available for a page, the translation table may be implemented as a skewed-associative cache that implements an insertion algorithm that realigns the translations in the table to maximize the utilization of the available entries is implemented.

7. 发明授权

US5893150A Efficient allocation of cache memory space in a computer system 失效
标题翻译：在计算机系统中高效地分配高速缓存存储空间
公开(公告)号：US5893150A
公开(公告)日：1999-04-06
申请号：US675306
申请日：1996-07-01
申请人： Erik E. Hagersten , Mark D. Hill
发明人： Erik E. Hagersten , Mark D. Hill
IPC分类号： G06F15/16 , G06F12/08 , G06F12/12
CPC分类号： G06F12/0888 , G06F12/0813
摘要： An efficient cache allocation scheme is provided for both uniprocessor and multiprocessor computer systems having at least one cache. In one embodiment, upon the detection of a cache miss, a determination of whether the cache miss is "avoidable" is made. In other words, would the present cache miss have occurred if the data had been cached previously and if the data had remained in the cache. One example of an avoidable cache miss in a multiprocessor system having a distributed memory architecture is an excess cache miss. An excess cache miss is either a capacity miss or a conflict miss. A capacity miss is caused by the insufficient size of the cache. A conflict miss is caused by insufficient depth in the associativity of the cache. The determination of the excess cache miss involves tracking read and write requests for data by the various processors and storing some record of the read/write request history in a table or linked list. Data is cached only after an avoidable cache miss has occurred. By caching only after at least one avoidable cache miss instead of upon every (initial) access, cache space can be allocated in a highly efficient manner thereby minimizing the number of data fetches caused by cache misses.
摘要翻译：为具有至少一个高速缓存的单处理器和多处理器计算机系统提供有效的高速缓存分配方案。在一个实施例中，当检测到高速缓存未命中时，确定高速缓存未命中是否“可避免”。换句话说，如果先前缓存了数据，并且数据保留在高速缓存中，现在的高速缓存未命中是否发生。具有分布式存储器架构的多处理器系统中的可避免的高速缓存未命中的一个示例是多余的高速缓存未命中。多余的高速缓存未命中是容量错误或冲突错过。容量丢失是由缓存大小不足引起的。冲突错过是由缓存的关联性不够深造成的。多余缓存未命中的确定包括跟踪各种处理器对数据的读和写请求，并将读/写请求历史的一些记录存储在表或链表中。仅在发生可避免的缓存未命中之后才会缓存数据。通过仅在至少一个可避免的缓存未命中而不是每次（初始）访问之后进行缓存，可以高效地分配高速缓存空间，从而最小化由高速缓存未命中引起的数据获取的数量。

8. 发明授权

US09753858B2 DRAM cache with tags and data jointly stored in physical rows 有权
公开(公告)号：US09753858B2
公开(公告)日：2017-09-05
申请号：US13307776
申请日：2011-11-30
申请人： Gabriel H. Loh , Mark D. Hill
发明人： Gabriel H. Loh , Mark D. Hill
IPC分类号： G06F12/00 , G06F12/0893 , G06F12/0864 , G06F12/123 , G06F12/0879 , G06F12/0831
CPC分类号： G06F12/0893 , G06F12/0831 , G06F12/0864 , G06F12/0879 , G06F12/123 , Y02D10/13
摘要： A system and method for efficient cache data access in a large row-based memory of a computing system. A computing system includes a processing unit and an integrated three-dimensional (3D) dynamic random access memory (DRAM). The processing unit uses the 3D DRAM as a cache. Each row of the multiple rows in the memory array banks of the 3D DRAM stores at least multiple cache tags and multiple corresponding cache lines indicated by the multiple cache tags. In response to receiving a memory request from the processing unit, the 3D DRAM performs a memory access according to the received memory request on a given cache line indicated by a cache tag within the received memory request. Rather than utilizing multiple DRAM transactions, a single, complex DRAM transaction may be used to reduce latency and power consumption.

9. 发明授权

US08868843B2 Hardware filter for tracking block presence in large caches 有权
标题翻译：用于跟踪大型缓存中的块的硬件过滤器
公开(公告)号：US08868843B2
公开(公告)日：2014-10-21
申请号：US13307815
申请日：2011-11-30
申请人： Gabriel H. Loh , Mark D. Hill
发明人： Gabriel H. Loh , Mark D. Hill
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/0893 , Y02D10/13
摘要： A system and method for efficiently determining whether a requested memory location is in a large row-based memory of a computing system. A computing system includes a processing unit that generates memory requests on a first chip and a cache (LLC) on a second chip connected to the first chip. The processing unit includes an access filter that determines whether to access the cache. The cache is fabricated on top of the processing unit. The processing unit determines whether to access the access filter for a given memory request. The processing unit accesses the access filter to determine whether given data associated with a given memory request is stored within the cache. In response to determining the access filter indicates the given data is not stored within the cache, the processing unit generates a memory request to send to off-package memory.
摘要翻译：一种用于有效地确定所请求的存储器位置是否在计算系统的大型基于行的存储器中的系统和方法。计算系统包括处理单元，其在与第一芯片连接的第二芯片上的第一芯片上生成存储器请求和高速缓存（LLC）。处理单元包括确定是否访问高速缓存的访问过滤器。高速缓存是在处理单元之上制造的。处理单元确定是否访问给定存储器请求的访问过滤器。处理单元访问访问过滤器以确定与给定存储器请求相关联的给定数据是否存储在高速缓存中。响应于确定访问过滤器指示给定数据未被存储在高速缓存中，处理单元产生存储器请求以发送到脱机存储器。

10. 发明授权

US08239633B2 Non-broadcast signature-based transactional memory 有权
标题翻译：非广播基于签名的事务内存
公开(公告)号：US08239633B2
公开(公告)日：2012-08-07
申请号：US12217811
申请日：2008-07-09
申请人： David A. Wood , Mark D. Hill , Michael M. Swift , Michael R. Marty , Luke Yen , Kevin E. Moore , Jayaram Bobba , Haris Volos
发明人： David A. Wood , Mark D. Hill , Michael M. Swift , Michael R. Marty , Luke Yen , Kevin E. Moore , Jayaram Bobba , Haris Volos
IPC分类号： G06F12/08
CPC分类号： G06F12/0815
摘要： A coherence controller in hardware of an apparatus in an example detects conflicts on coherence requests through direct, non-broadcast employment of signatures that: summarize read-sets and write-sets of memory transactions; and provide false positives but no false negatives for the conflicts on the coherence requests. The signatures comprise fixed-size representations of a substantially arbitrary set of addresses for the read-sets and the write-sets of the memory transactions.
摘要翻译：在示例中的装置的硬件中的相干控制器通过直接，非广播使用签名来检测对相干请求的冲突，所述签名总结了存储器事务的读取集和写入集合; 并提供错误的肯定，但对于一致性要求的冲突没有错误的否定。签名包括对于存储器事务的读取集合和写入集合的基本上任意的地址集的固定大小表示。

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