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1. 发明授权

US06880057B1 Split write data processing mechanism for memory controllers utilizing inactive periods during write data processing for other transactions 有权
标题翻译：在其他交易的写入数据处理期间，利用非活动期间分割写入数据处理机制
公开(公告)号：US06880057B1
公开(公告)日：2005-04-12
申请号：US09478140
申请日：2000-01-05
申请人： Thomas P. Webber , Ketan P. Joshi
发明人： Thomas P. Webber , Ketan P. Joshi
IPC分类号： G06F13/16 , G06F12/00
CPC分类号： G06F13/1673
摘要： A memory controller provides fast processing of sequential split memory access instructions which include a split write instruction. In a split write instruction, a write address and write request are provided to the memory controller in an initial transaction while write data can be provided to the memory controller in a later transaction. The memory controller includes a sideline buffer, for buffering incomplete write instructions, and memory control logic which ensures proper execution of the sequential memory access instructions. Upon receiving an incomplete write instruction, the memory control logic stores the corresponding write request and write address in the sideline buffer until corresponding write data becomes available. The memory control logic determines if there is overlap between memory space to be occupied by an initial write data block and memory space to be occupied by a subsequent read data block or second write data block, of a read or write instruction respectively. By using a sideline buffer to temporarily store incomplete write instructions, processing of sequential memory access instructions can continue subject to observance of memory access conflict rules.
摘要翻译：存储器控制器提供包括分离写入指令的顺序分割存储器访问指令的快速处理。在分割写入指令中，写入地址和写入请求在初始事务中被提供给存储器控制器，而写入数据可以在稍后的事务中提供给存储器控制器。存储器控制器包括用于缓冲不完整写入指令的副线缓冲器以及确保顺序存储器访问指令的正确执行的存储器控制逻辑。在接收到不完整的写入指令时，存储器控制逻辑将对应的写入请求和写入地址存储在边线缓冲器中，直到相应的写入数据变得可用。存储器控制逻辑确定分别由读写指令分别由初始写数据块占据的存储器空间与要由后续读数据块或第二写数据块占据的存储空间之间是否重叠。通过使用副线缓冲器临时存储不完整的写指令，顺序存储器访问指令的处理可以继续遵守存储器访问冲突规则。

2. 发明授权

US6061772A Split write data processing mechanism for memory controllers utilizing inactive periods during write data processing for other transactions 失效
标题翻译：在其他交易的写入数据处理期间，利用非活动期间分割写入数据处理机制
公开(公告)号：US6061772A
公开(公告)日：2000-05-09
申请号：US884844
申请日：1997-06-30
申请人： Thomas P. Webber , Ketan P. Joshi
发明人： Thomas P. Webber , Ketan P. Joshi
IPC分类号： G06F13/16 , G06F12/00
CPC分类号： G06F13/1673
摘要： A memory controller provides fast processing of sequential split memory access instructions which include a split write instruction. In a split write instruction, a write address and write request are provided to the memory controller in an initial transaction while write data can be provided to the memory controller in a later transaction. The memory controller includes a sideline buffer, for buffering incomplete write instructions, and memory control logic which ensures proper execution of the sequential memory access instructions. Upon receiving an incomplete write instruction, the memory control logic stores the corresponding write request and write address in the sideline buffer until corresponding write data becomes available. The memory control logic determines if there is overlap between memory space to be occupied by an initial write data block and memory space to be occupied by a subsequent read data block or second write data block, of a read or write instruction respectively. By using a sideline buffer to temporarily store incomplete write instructions, processing of sequential memory access instructions can continue subject to observance of memory access conflict rules.
摘要翻译：存储器控制器提供包括分离写入指令的顺序分割存储器访问指令的快速处理。在分割写入指令中，写入地址和写入请求在初始事务中被提供给存储器控制器，而写入数据可以在稍后的事务中提供给存储器控制器。存储器控制器包括用于缓冲不完整写入指令的副线缓冲器以及确保顺序存储器访问指令的正确执行的存储器控制逻辑。在接收到不完整的写入指令时，存储器控制逻辑将对应的写入请求和写入地址存储在边线缓冲器中，直到相应的写入数据变得可用。存储器控制逻辑确定分别由读写指令分别由初始写数据块占据的存储器空间与要由后续读数据块或第二写数据块占据的存储空间之间是否重叠。通过使用副线缓冲器临时存储不完整的写指令，顺序存储器访问指令的处理可以继续遵守存储器访问冲突规则。

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