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1. 发明授权

US09135185B2 Die-stacked memory device providing data translation 有权
标题翻译：提供数据转换的堆叠式存储器件
公开(公告)号：US09135185B2
公开(公告)日：2015-09-15
申请号：US13726143
申请日：2012-12-23
申请人： Gabriel H. Loh , Bradford M. Beckmann , James M. O'Connor , Michael Ignatowski , Michael J. Schulte , Lisa R. Hsu , Nuwan S. Jayasena
发明人： Gabriel H. Loh , Bradford M. Beckmann , James M. O'Connor , Michael Ignatowski , Michael J. Schulte , Lisa R. Hsu , Nuwan S. Jayasena
IPC分类号： G06F12/02 , G06F12/10
CPC分类号： G06F12/1027 , H01L25/18 , H01L2224/16225 , H01L2225/06565 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： A die-stacked memory device incorporates a data translation controller at one or more logic dies of the device to provide data translation services for data to be stored at, or retrieved from, the die-stacked memory device. The data translation operations implemented by the data translation controller can include compression/decompression operations, encryption/decryption operations, format translations, wear-leveling translations, data ordering operations, and the like. Due to the tight integration of the logic dies and the memory dies, the data translation controller can perform data translation operations with higher bandwidth and lower latency and power consumption compared to operations performed by devices external to the die-stacked memory device.
摘要翻译：芯片堆叠存储器件在器件的一个或多个逻辑管芯上并入数据转换控制器，以提供数据转换服务，用于存储在芯片堆叠存储器件中或从芯片堆叠的存储器件中取出的数据。由数据转换控制器实现的数据转换操作可以包括压缩/解压缩操作，加密/解密操作，格式转换，磨损均衡转换，数据排序操作等。由于逻辑管芯和存储器管芯的紧密集成，与堆叠式存储器件外部的器件执行的操作相比，数据转换控制器可以执行具有更高带宽和更低延迟和功耗的数据转换操作。

2. 发明授权

US08775762B2 Method and apparatus for batching memory requests 有权
标题翻译：批量存储器请求的方法和装置
公开(公告)号：US08775762B2
公开(公告)日：2014-07-08
申请号：US13465153
申请日：2012-05-07
申请人： Gabriel H. Loh , Rachata Ausavarungnirun
发明人： Gabriel H. Loh , Rachata Ausavarungnirun
IPC分类号： G06F12/02 , G06F13/16
CPC分类号： G06F13/1642
摘要： A memory controller includes a batch unit, a batch scheduler, and a memory command scheduler. The batch unit includes a plurality of source queues for receiving memory requests from a plurality of sources. Each source is associated with a selected one of the source queues. The batch unit is operable to generate batches of memory requests in the source queues. The batch scheduler is operable to select a batch from one of the source queues. The memory command scheduler is operable to receive the selected batch from the batch scheduler and issue the memory requests in the selected batch to a memory interfacing with the memory controller.
摘要翻译：存储器控制器包括批量单元，批量调度器和存储器命令调度器。批量单元包括用于从多个源接收存储器请求的多个源队列。每个源与选定的一个源队列相关联。批处理单元可操作以在源队列中生成批次的存储器请求。批处理调度器可操作以从源队列中的一个队列中选择一批。存储器命令调度器可操作以从批处理调度器接收所选批次，并将所选批次中的存储器请求发送到与存储器控制器接口的存储器。

3. 发明申请

US20140108885A1 HIGH RELIABILITY MEMORY CONTROLLER 有权
标题翻译：高可靠性存储控制器
公开(公告)号：US20140108885A1
公开(公告)日：2014-04-17
申请号：US13649745
申请日：2012-10-11
申请人： Gabriel H. Loh , Vilas K. Sridharan
发明人： Gabriel H. Loh , Vilas K. Sridharan
IPC分类号： G06F12/00 , G06F11/00
CPC分类号： G06F11/1044
摘要： An integrated circuit includes a memory having an address space and a memory controller coupled to the memory for accessing the address space in response to received memory accesses. The memory controller further accesses a plurality of data elements in a first portion of the address space, and reliability data corresponding to the plurality of data elements in a second portion of the address space.
摘要翻译：集成电路包括具有地址空间的存储器和耦合到存储器的存储器控制器，用于响应于接收到的存储器访问来访问地址空间。存储器控制器还访问地址空间的第一部分中的多个数据元素以及与地址空间的第二部分中的多个数据元素相对应的可靠性数据。

4. 发明申请

US20140082322A1 PROGRAMMABLE PHYSICAL ADDRESS MAPPING FOR MEMORY 有权
标题翻译：存储器的可编程物理地址映射
公开(公告)号：US20140082322A1
公开(公告)日：2014-03-20
申请号：US13617673
申请日：2012-09-14
申请人： Gabriel H. Loh , Mauricio Breternitz, JR.
发明人： Gabriel H. Loh , Mauricio Breternitz, JR.
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , G06F12/0207 , G06F12/0653 , G06F2212/1016
摘要： A memory implements a programmable physical address mapping that can change to reflect changing memory access patterns, observed or anticipated, to the memory. The memory employs address decode logic that can implement any of a variety of physical address mappings between physical addresses and corresponding memory locations. The physical address mappings may locate the data within one or more banks and rows of the memory so as to facilitate more efficient memory accesses for a given access pattern. The programmable physical address mapping employed by the hardware of the memory can include, but is not limited to, hardwired logic gates, programmable look-up tables or other mapping tables, reconfigurable logic, or combinations thereof. The physical address mapping may be programmed for the entire memory or on a per-memory region basis.
摘要翻译：存储器实现可编程物理地址映射，可以改变以反映对存储器的观察或预期的改变的存储器访问模式。存储器采用地址解码逻辑，其可以实现物理地址和相应存储器位置之间的各种物理地址映射中的任何一种。物理地址映射可以将数据定位在存储器的一个或多个存储体和行中，以便于给定访问模式更有效的存储器访问。存储器的硬件采用的可编程物理地址映射可以包括但不限于硬连线逻辑门，可编程查找表或其它映射表，可重构逻辑或其组合。物理地址映射可以针对整个存储器或基于每存储器区域编程。

5. 发明授权

US08621131B2 Uniform multi-chip identification and routing system 有权
标题翻译：统一的多芯片识别和路由系统
公开(公告)号：US08621131B2
公开(公告)日：2013-12-31
申请号：US13221465
申请日：2011-08-30
申请人： Gabriel H. Loh , Bradford M. Beckmann , Jaewoong Chung , Subho Chatterjee
发明人： Gabriel H. Loh , Bradford M. Beckmann , Jaewoong Chung , Subho Chatterjee
IPC分类号： G06F13/00
CPC分类号： G06F13/4265 , G06F2213/0038
摘要： Various methods, computer-readable mediums, articles of manufacture and systems are disclosed. In one aspect, a method is provided that includes generating a packet with a first semiconductor chip. The packet is destined to transit a first substrate and be received by a node of a second semiconductor chip. The packet includes a packet header and packet body. The packet header includes an identification of a first exit point from the first substrate and an identification of the node. The packet is sent to the first substrate and eventually to the node of the second semiconductor chip.
摘要翻译：公开了各种方法，计算机可读介质，制品和系统。一方面，提供一种包括用第一半导体芯片产生分组的方法。分组旨在传送第一衬底并由第二半导体芯片的节点接收。分组包括分组报头和分组主体。分组报头包括来自第一基板的第一出口点的标识和节点的标识。分组被发送到第一衬底并且最终传送到第二半导体芯片的节点。

6. 发明申请

US20130346695A1 INTEGRATED CIRCUIT WITH HIGH RELIABILITY CACHE CONTROLLER AND METHOD THEREFOR 审中-公开
标题翻译：具有高可靠性缓存控制器的集成电路及其方法
公开(公告)号：US20130346695A1
公开(公告)日：2013-12-26
申请号：US13532125
申请日：2012-06-25
申请人： Gabriel H. Loh , Vilas Sridharan
发明人： Gabriel H. Loh , Vilas Sridharan
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F12/0897
摘要： An integrated circuit includes a register including a field for defining a high reliability mode of the integrated circuit and a cache and memory controller coupled to the register and responsive to the high reliability mode to access a memory to store, in a row of the memory, a first multiple number of cache lines, a first multiple number of tags corresponding to the first multiple number of cache lines, and reliability data corresponding to at least the first multiple number of cache lines.
摘要翻译：集成电路包括寄存器，其包括用于定义集成电路的高可靠性模式的字段和耦合到寄存器的高速缓存和存储器控制器，并且响应于高可靠性模式访问存储器以存储在存储器的一行中，第一多个高速缓存行，对应于第一多个高速缓存行的第一多个标签，以及对应于至少第一多个高速缓存行的可靠性数据。

7. 发明申请

US20120311269A1 NON-UNIFORM MEMORY-AWARE CACHE MANAGEMENT 审中-公开
标题翻译：非统一存储器 - 高速缓存管理
公开(公告)号：US20120311269A1
公开(公告)日：2012-12-06
申请号：US13153102
申请日：2011-06-03
申请人： Gabriel H. Loh , Jaewoong Chung , Nuwan Jayasena , Steve Reinhardt , James O'Connor , Kevin McGrath
发明人： Gabriel H. Loh , Jaewoong Chung , Nuwan Jayasena , Steve Reinhardt , James O'Connor , Kevin McGrath
IPC分类号： G06F12/08
CPC分类号： G06F12/126 , Y02D10/13
摘要： An apparatus is disclosed for caching memory data in a computer system with multiple system memories. The apparatus comprises a data cache for caching memory data. The apparatus is configured to determine a retention priority for a cache block stored in the data cache. The retention priority is based on a performance characteristic of a system memory from which the cache block is cached.
摘要翻译：公开了一种用于在具有多个系统存储器的计算机系统中缓存存储器数据的装置。该装置包括用于缓存存储器数据的数据高速缓存。该装置被配置为确定存储在数据高速缓存中的高速缓存块的保留优先级。保留优先级基于高速缓存块被缓存的系统存储器的性能特性。

8. 发明授权

US09753858B2 DRAM cache with tags and data jointly stored in physical rows 有权
公开(公告)号：US09753858B2
公开(公告)日：2017-09-05
申请号：US13307776
申请日：2011-11-30
申请人： Gabriel H. Loh , Mark D. Hill
发明人： Gabriel H. Loh , Mark D. Hill
IPC分类号： G06F12/00 , G06F12/0893 , G06F12/0864 , G06F12/123 , G06F12/0879 , G06F12/0831
CPC分类号： G06F12/0893 , G06F12/0831 , G06F12/0864 , G06F12/0879 , G06F12/123 , Y02D10/13
摘要： A system and method for efficient cache data access in a large row-based memory of a computing system. A computing system includes a processing unit and an integrated three-dimensional (3D) dynamic random access memory (DRAM). The processing unit uses the 3D DRAM as a cache. Each row of the multiple rows in the memory array banks of the 3D DRAM stores at least multiple cache tags and multiple corresponding cache lines indicated by the multiple cache tags. In response to receiving a memory request from the processing unit, the 3D DRAM performs a memory access according to the received memory request on a given cache line indicated by a cache tag within the received memory request. Rather than utilizing multiple DRAM transactions, a single, complex DRAM transaction may be used to reduce latency and power consumption.

9. 发明授权

US09331053B2 Stacked semiconductor chip device with phase change material 有权
标题翻译：具相变材料的叠层半导体芯片器件
公开(公告)号：US09331053B2
公开(公告)日：2016-05-03
申请号：US14016063
申请日：2013-08-31
申请人： Manish Arora , Nuwan Jayasena , Gabriel H. Loh , Michael J. Schulte
发明人： Manish Arora , Nuwan Jayasena , Gabriel H. Loh , Michael J. Schulte
IPC分类号： H01L21/00 , H01L25/065 , H01L23/00 , H01L23/427
CPC分类号： H01L25/0657 , H01L23/427 , H01L24/01 , H01L24/05 , H01L24/08 , H01L24/80 , H01L2224/0557 , H01L2224/05571 , H01L2224/08146 , H01L2224/16227 , H01L2225/06541 , H01L2225/06589 , H01L2924/01322 , H01L2924/12042 , H01L2924/00 , H01L2924/00012
摘要： Various stacked semiconductor chip arrangements and methods of manufacturing the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip, a second semiconductor chip mounted on the first semiconductor chip, and a first portion of a phase change material positioned in a first pocket associated with the first semiconductor chip or the second semiconductor chip to store heat generated by one or both of the first and second semiconductor chips.
摘要翻译：公开了各种叠层半导体芯片布置及其制造方法。一方面，提供了一种装置，其包括第一半导体芯片，安装在第一半导体芯片上的第二半导体芯片和位于与第一半导体芯片或第二半导体芯片相关联的第一凹槽中的相变材料的第一部分芯片以存储由第一和第二半导体芯片中的一个或两个产生的热量。

10. 发明授权

US09146846B2 Programmable physical address mapping for memory 有权
标题翻译：存储器的可编程物理地址映射
公开(公告)号：US09146846B2
公开(公告)日：2015-09-29
申请号：US13617673
申请日：2012-09-14
申请人： Gabriel H. Loh , Mauricio Breternitz, Jr.
发明人： Gabriel H. Loh , Mauricio Breternitz, Jr.
IPC分类号： G06F12/06 , G06F12/00 , G06F12/02
CPC分类号： G06F12/00 , G06F12/0207 , G06F12/0653 , G06F2212/1016
摘要： A memory implements a programmable physical address mapping that can change to reflect changing memory access patterns, observed or anticipated, to the memory. The memory employs address decode logic that can implement any of a variety of physical address mappings between physical addresses and corresponding memory locations. The physical address mappings may locate the data within one or more banks and rows of the memory so as to facilitate more efficient memory accesses for a given access pattern. The programmable physical address mapping employed by the hardware of the memory can include, but is not limited to, hardwired logic gates, programmable look-up tables or other mapping tables, reconfigurable logic, or combinations thereof. The physical address mapping may be programmed for the entire memory or on a per-memory region basis.
摘要翻译：存储器实现可编程物理地址映射，可以改变以反映对存储器的观察或预期的改变的存储器访问模式。存储器采用地址解码逻辑，其可以实现物理地址和相应存储器位置之间的各种物理地址映射中的任何一种。物理地址映射可以将数据定位在存储器的一个或多个存储体和行中，以便于给定访问模式更有效的存储器访问。存储器的硬件采用的可编程物理地址映射可以包括但不限于硬连线逻辑门，可编程查找表或其它映射表，可重构逻辑或其组合。物理地址映射可以针对整个存储器或基于每存储器区域编程。

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