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1. 发明授权

US06489837B2 Digitally controlled impedance for I/O of an integrated circuit device 有权
标题翻译：用于集成电路器件的I / O的数字控制阻抗
公开(公告)号：US06489837B2
公开(公告)日：2002-12-03
申请号：US10007167
申请日：2001-11-30
申请人： David P. Schultz , Suresh M. Menon , Eunice Y. D. Hao , Jason R. Bergendahl , Jian Tan
发明人： David P. Schultz , Suresh M. Menon , Eunice Y. D. Hao , Jason R. Bergendahl , Jian Tan
IPC分类号： G05F110
CPC分类号： H03K19/00384 , H03K19/0005 , H04L25/0278
摘要： A system for controlling the impedances of circuits on an integrated circuit chip is provided. At least one circuit is selected to operate as a p-channel reference circuit, and at least one circuit is selected to operate as an n-channel reference circuit. Other circuits are selected to operate as circuits and/or line termination circuits. A digitally controlled impedance (DCI) circuit controls the p-channel reference circuit to determine a desired configuration of p-channel transistors for use in the circuits. The DCI circuit further controls the n-channel reference circuit to determine a desired configuration of n-channel transistors for use in the circuits. The DCI circuit takes into account such factors as resistances of p-channel transistors in the p-channel reference circuit, resistances of n-channel transistors in the n-channel reference circuit, as well as temperature, voltage and process variations. The DCI circuit relays information identifying the desired configurations of the n-channel and p-channel transistors to the circuits. The circuits are then configured in response to this information.
摘要翻译：提供一种用于控制集成电路芯片上的电路的阻抗的系统。选择至少一个电路作为p沟道参考电路工作，并且选择至少一个电路作为n沟道参考电路进行工作。选择其他电路用作电路和/或线路终端电路。数字控制阻抗（DCI）电路控制p沟道参考电路以确定用于电路中的p沟道晶体管的期望配置。 DCI电路进一步控制n沟道参考电路以确定在电路中使用的n沟道晶体管的期望配置。 DCI电路考虑了p沟道参考电路中p沟道晶体管的电阻，n沟道参考电路中n沟道晶体管的电阻以及温度，电压和工艺变化等因素。 DCI电路将识别n沟道和p沟道晶体管的期望配置的信息中继到电路。然后响应于该信息配置电路。

2. 发明授权

US06445245B1 Digitally controlled impedance for I/O of an integrated circuit device 有权
公开(公告)号：US06445245B1
公开(公告)日：2002-09-03
申请号：US09684539
申请日：2000-10-06
申请人： David P. Schultz , Suresh M. Menon , Eunice Y. D. Hao , Jason R. Bergendahl , Jian Tan
发明人： David P. Schultz , Suresh M. Menon , Eunice Y. D. Hao , Jason R. Bergendahl , Jian Tan
IPC分类号： G05F110
CPC分类号： H03K19/00384 , H03K19/0005 , H04L25/0278
摘要： A system for controlling the impedances of circuits on an integrated circuit chip is provided. At least one circuit is selected to operate as a p-channel reference circuit, and at least one circuit is selected to operate as an n-channel reference circuit. Other circuits are selected to operate as circuits and/or line termination circuits. A digitally controlled impedance (DCI) circuit controls the p-channel reference circuit to determine a desired configuration of p-channel transistors for use in the circuits. The DCI circuit further controls the n-channel reference circuit to determine a desired configuration of n-channel transistors for use in the circuits. The DCI circuit takes into account such factors as resistances of p-channel transistors in the p-channel reference circuit, resistances of n-channel transistors in the n-channel reference circuit, as well as temperature, voltage and process variations. The DCI circuit relays information identifying the desired configurations of the n-channel and p-channel transistors to the circuits. The circuits are then configured in response to this information.

3. 发明授权

US07254677B1 First-in, first-out memory system with reduced cycle latency 有权
标题翻译：先进先出的内存系统，缩短了周期延迟
公开(公告)号：US07254677B1
公开(公告)日：2007-08-07
申请号：US10839402
申请日：2004-05-04
申请人： Wayson J. Lowe , Eunice Y. D. Hao , Tony K. Ngai , Peter H. Alfke
发明人： Wayson J. Lowe , Eunice Y. D. Hao , Tony K. Ngai , Peter H. Alfke
IPC分类号： G06F12/00
CPC分类号： G06F5/10
摘要： A first-in, first-out (“FIFO”) memory system embedded in a programmable logic device has an embedded FIFO memory array coupled to an output register. If the embedded FIFO memory is empty, the first word written to the FIFO memory system is pre-fetched to the output register. A first-word detection circuit asserts a DATA VALID signal if the first word is available to be read from the output register when READ ENABLE is asserted. In an alternative embodiment, the first word is pre-fetched to the output of the output register and is available to be read before READ ENABLE is asserted.
摘要翻译：嵌入在可编程逻辑器件中的先进先出（“FIFO”）存储器系统具有耦合到输出寄存器的嵌入式FIFO存储器阵列。如果嵌入式FIFO存储器为空，则写入FIFO存储器系统的第一个字被预取到输出寄存器。如果在启用READ ENABLE时，如果第一个字可用于从输出寄存器读取，则第一个字检测电路会断言DATA VALID信号。在替代实施例中，第一个字被预取到输出寄存器的输出，并且可以在READ ENABLE被声明之前被读取。

4. 发明授权

US06934198B1 First-in, first-out buffer system in an integrated circuit 有权
标题翻译：先进先出的缓冲系统在集成电路中
公开(公告)号：US06934198B1
公开(公告)日：2005-08-23
申请号：US10838957
申请日：2004-05-04
申请人： Wayson J. Lowe , Eunice Y. D. Hao , Tony K. Ngai , Peter H. Alfke
发明人： Wayson J. Lowe , Eunice Y. D. Hao , Tony K. Ngai , Peter H. Alfke
IPC分类号： G06F5/14 , G11C7/00
CPC分类号： G06F5/14 , G06F2205/102 , G06F2205/126
摘要： An integrated circuit having an embedded first-in, first-out (“FIFO”) memory system uses an embedded block random access memory (“BRAM”). Counters operate in both the read and write clock domains. A binary adder adds a first selected offset value and to a first pointer address, and the sum is converted to a first gray code value. The first gray code value is compared to a second gray code value that represents a second pointer address. If the first gray code value equals the second gray code value, the output of the comparator is provided to a logic block that produces a status flag (e.g. ALMOST FULL or ALMOST EMPTY) in the correct clock domain.
摘要翻译：具有嵌入式先进先出（“FIFO”）存储器系统的集成电路使用嵌入式块随机存取存储器（“BRAM”）。计数器在读和写时钟域都工作。二进制加法器将第一选择的偏移值和第一指针地址相加，并将和转换为第一灰度代码值。将第一灰度代码值与表示第二指针地址的第二灰度代码值进行比较。如果第一灰度代码值等于第二灰度代码值，则将比较器的输出提供给在正确的时钟域中产生状态标志（例如ALMOST FULL或ALMOST EMPTY）的逻辑块。

5. 发明授权

US07161849B1 First-in, first-out buffer system in an integrated circuit 有权
标题翻译：先进先出的缓冲系统在集成电路中
公开(公告)号：US07161849B1
公开(公告)日：2007-01-09
申请号：US11140019
申请日：2005-05-27
申请人： Wayson J. Lowe , Eunice Y. D. Hao , Tony K. Ngai , Peter H. Alfke
发明人： Wayson J. Lowe , Eunice Y. D. Hao , Tony K. Ngai , Peter H. Alfke
IPC分类号： G11C7/10
CPC分类号： G06F5/14 , G06F2205/102 , G06F2205/126
摘要： An integrated circuit having an embedded first-in, first-out (“FIFO”) memory system uses an embedded block random access memory (“BRAM”). Counters operate in both the read and write clock domains. A binary adder adds a first selected offset value and to a first pointer address, and the sum is converted to a first gray code value. The first gray code value is compared to a second gray code value that represents a second pointer address. If the first gray code value equals the second gray code value, the output of the comparator is provided to a logic block that produces a status flag (e.g. ALMOST FULL or ALMOST EMPTY) in the correct clock domain.
摘要翻译：具有嵌入式先进先出（“FIFO”）存储器系统的集成电路使用嵌入式块随机存取存储器（“BRAM”）。计数器在读和写时钟域都工作。二进制加法器将第一选择的偏移值和第一指针地址相加，并将和转换为第一灰度代码值。将第一灰度代码值与表示第二指针地址的第二灰度代码值进行比较。如果第一灰度代码值等于第二灰度代码值，则将比较器的输出提供给在正确的时钟域中产生状态标志（例如ALMOST FULL或ALMOST EMPTY）的逻辑块。

6. 发明授权

US07417918B1 Method and apparatus for configuring the operating speed of a programmable logic device through a self-timed reference circuit 有权
标题翻译：用于通过自定时参考电路配置可编程逻辑器件的工作速度的方法和装置
公开(公告)号：US07417918B1
公开(公告)日：2008-08-26
申请号：US10954927
申请日：2004-09-29
申请人： Eunice Y. D. Hao , Tony K. Ngai , Jennifer Wong , Alvin Y. Ching
发明人： Eunice Y. D. Hao , Tony K. Ngai , Jennifer Wong , Alvin Y. Ching
IPC分类号： G11C8/18
CPC分类号： G11C29/02 , G11C11/41 , G11C29/023 , G11C29/028 , H03K19/17748 , H03K19/17764 , H03K19/17792
摘要： Method and apparatus for configuring a programmable logic device to operate at a plurality of clock frequencies comprising configurable programmable self-timed delay circuits and associated configuration software. The configurable IC clock frequencies increase device performance and manufacturing yield.
摘要翻译：用于配置可编程逻辑器件以在多个时钟频率下操作的方法和装置，包括可配置可编程自定时延迟电路和相关配置软件。可配置的IC时钟频率提高了器件性能和制造产量。

7. 发明授权

US06956776B1 Almost full, almost empty memory system 有权
标题翻译：几乎完整，几乎空的内存系统
公开(公告)号：US06956776B1
公开(公告)日：2005-10-18
申请号：US10839201
申请日：2004-05-04
申请人： Wayson J. Lowe , Eunice Y. D. Hao , Tony K. Ngai , Peter H. Alfke
发明人： Wayson J. Lowe , Eunice Y. D. Hao , Tony K. Ngai , Peter H. Alfke
IPC分类号： G06F5/14 , G11C7/00
CPC分类号： G06F5/14 , G06F2205/102 , G06F2205/106 , G06F2205/126
摘要： A buffer memory status detection circuit has a binary logic gate (e.g. an OR gate) coupled to a comparator output signal that is asserted when a sum of a first address pointer of a FIFO memory array plus a first offset equals a second address pointer, and to a reset signal. Binary logic provides a binary output (i.e. “0” or “1”) in a first clock domain to two synchronization registers in series that convert the output to a second clock domain. An optional pipeline register improves timing of the output in the second clock domain, and is particularly desirable for use with high-speed clocks.
摘要翻译：缓冲存储器状态检测电路具有耦合到比较器输出信号的二进制逻辑门（例如或门），当FIFO存储器阵列的第一地址指针和第一偏移的和等于第二地址指针时，比较器输出信号被置位;以及到复位信号。二进制逻辑将第一时钟域中的二进制输出（即“0”或“1”）提供给将输出转换为第二时钟域的串联的两个同步寄存器。可选的流水线寄存器提高了第二个时钟域的输出时序，特别适用于高速时钟。

8. 发明授权

US06937172B1 Method and system for gray-coding counting 有权
标题翻译：灰色编码计数方法和系统
公开(公告)号：US06937172B1
公开(公告)日：2005-08-30
申请号：US10838965
申请日：2004-05-04
申请人： Wayson J. Lowe , Eunice Y. D. Hao , Tony K. Ngai , Peter H. Alfke
发明人： Wayson J. Lowe , Eunice Y. D. Hao , Tony K. Ngai , Peter H. Alfke
IPC分类号： G06F5/14 , H03K23/00 , H03M7/04
CPC分类号： G06F5/14 , G06F2205/102 , G06F2205/126 , H03K23/005
摘要： A system for gray-code counting in an integrated circuit such as a programmable logic device uses a binary adder coupled to a binary counter output and to a selected binary offset value. The binary adder provides a binary sum that is converted to a gray code value by a binary-to-gray converter. The gray code value represents the binary sum output.
摘要翻译：在诸如可编程逻辑器件的集成电路中的用于灰度计数的系统使用耦合到二进制计数器输出和选择的二进制偏移值的二进制加法器。二进制加法器提供通过二进制到灰色转换器转换为灰度值的二进制和。灰色代码值表示二进制和输出。

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