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1. 发明授权

US07644221B1 System interface unit 有权
标题翻译：系统接口单元
公开(公告)号：US07644221B1
公开(公告)日：2010-01-05
申请号：US11103319
申请日：2005-04-11
申请人： Paul G. Chan , Ricky C. Hetherington
发明人： Paul G. Chan , Ricky C. Hetherington
IPC分类号： G06F13/36
CPC分类号： G06F13/387
摘要： A processor including an integrated system interface unit configured to manage multiple I/O interfaces and multiple protocols. A processor includes a plurality of processing cores, a cache comprising a plurality of banks, and a system interface unit coupled to the processing cores and the cache. The system interface unit includes an inbound unit configured to receive inbound transactions from a first I/O unit and a second I/O unit, and an outbound unit configured to convey outbound transactions to either the first I/O unit or the second I/O unit. Each of the first and second I/O units is configured to support different protocols. Prior to conveying transaction data to the system interface, the first I/O unit and second I/O units reformat transaction data to conform to a common format. The system interface receives and stores transaction data in either queues dedicated for cacheable transactions or queues dedicated for non-cacheable transactions. In addition, each of the I/O units may also indicate in the common format whether a given transaction is to be ordered with respect to other transactions. The system interface may separately store ordered transactions from those which are non-ordered.
摘要翻译：一种处理器，包括被配置为管理多个I / O接口和多个协议的集成系统接口单元。处理器包括多个处理核心，包括多个存储体的高速缓存以及耦合到处理核心和高速缓存的系统接口单元。系统接口单元包括配置成从第一I / O单元和第二I / O单元接收入站事务的入站单元，以及配置为将出站事务传送到第一I / O单元或第二I / O单位。第一和第二I / O单元中的每一个被配置为支持不同的协议。在将交易数据传送到系统接口之前，第一个I / O单元和第二个I / O单元重新格式化交易数据以符合通用格式。系统接口将事务数据接收并存储在专用于可缓存事务的队列或专用于不可缓存事务的队列中。此外，每个I / O单元还可以以通用格式指示给定的交易是否相对于其他交易被排序。系统接口可以分别存储有序的事务和非有序事务。

2. 发明授权

US08024522B1 Memory ordering queue/versioning cache circuit 有权
标题翻译：内存订购队列/版本控制缓存电路
公开(公告)号：US08024522B1
公开(公告)日：2011-09-20
申请号：US12030851
申请日：2008-02-13
申请人： John Gregory Favor , Paul G. Chan , Graham Ricketson Murphy , Joseph Byron Rowlands
发明人： John Gregory Favor , Paul G. Chan , Graham Ricketson Murphy , Joseph Byron Rowlands
IPC分类号： G06F9/00 , G06F13/00
CPC分类号： G06F9/3857 , G06F9/3004 , G06F9/3808 , G06F9/3834 , G06F9/3851 , G06F9/3863 , G06F12/0875 , Y02D10/13
摘要： A processor includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them. At least some of the active memory operations access the memory in an execution order that is different from the program order. During the operation of the circuit, none of the operations of a given trace has any effect on the execution unit's architectural state prior to committing that trace. Each trace becomes eligible for commitment after all operations in the trace complete executing. The circuit also includes a sub-circuit that holds memory operation ordering information corresponding to the active memory operations. The sub-circuit detects violations of ordering constraints. After each trace is committed, the sub-circuit invalidates all of the memory operation ordering information associated with the trace.
摘要翻译：处理器包括用于跟踪基于跟踪的执行的存储器操作的电路。每个跟踪包括包括零个或多个存储器操作的一系列操作。正在执行的存储器操作形成一组在其间具有预定义的程序顺序的活动存储器操作。至少一些主动存储器操作以与程序顺序不同的执行顺序访问存储器。在电路运行期间，在提交跟踪之前，给定跟踪的任何操作都不会对执行单元的架构状态产生任何影响。轨迹中的所有操作完成执行后，每个轨迹都将有资格获得承诺。该电路还包括保持对应于活动存储器操作的存储器操作排序信息的子电路。子电路检测到排序限制的违规。在每个跟踪提交之后，子电路使与跟踪相关联的所有存储器操作排序信息无效。

3. 发明授权

US08370609B1 Data cache rollbacks for failed speculative traces with memory operations 有权
标题翻译：具有内存操作的失败的推测性跟踪的数据高速缓存回滚
公开(公告)号：US08370609B1
公开(公告)日：2013-02-05
申请号：US12030854
申请日：2008-02-13
申请人： John Gregory Favor , Paul G. Chan , Graham Ricketson Murphy , Joseph Byron Rowlands
发明人： John Gregory Favor , Paul G. Chan , Graham Ricketson Murphy , Joseph Byron Rowlands
IPC分类号： G06F9/312
CPC分类号： G06F9/3808 , G06F9/3834 , G06F9/3863 , G06F11/3636
摘要： This invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. Each entry refers to a checkpoint location. Memory operation ordering entries correspond to each one of the active memory operations. Violations of the ordering constraints result in overwriting the checkpoint locations associated with the selected trace as well as the checkpoint locations associated with traces that are younger than the selected trace.
摘要翻译：本发明包括用于跟踪基于跟踪的执行的存储器操作的电路。每个跟踪包括包括零个或多个存储器操作的一系列操作。正在执行的存储器操作形成一组活动存储器操作，它们之间具有预定义的程序顺序和相应的排序限制。至少一些主动存储器操作以与程序顺序不同的执行顺序访问存储器。检查点条目与每个跟踪相关联。每个条目指的是检查点位置。存储器操作排序条目对应于每个活动存储器操作。违反排序限制导致覆盖与所选跟踪相关联的检查点位置以及与所选跟踪较年轻的跟踪关联的检查点位置。

4. 发明授权

US08010745B1 Rolling back a speculative update of a non-modifiable cache line 有权
标题翻译：回滚不可修改的缓存行的推测更新
公开(公告)号：US08010745B1
公开(公告)日：2011-08-30
申请号：US12030859
申请日：2008-02-13
申请人： John Gregory Favor , Paul G. Chan , Graham Ricketson Murphy , Joseph Byron Rowlands
发明人： John Gregory Favor , Paul G. Chan , Graham Ricketson Murphy , Joseph Byron Rowlands
IPC分类号： G06F9/00 , G06F13/00
CPC分类号： G06F9/3808 , G06F9/3017 , G06F9/3834 , G06F9/3836 , G06F9/3861
摘要： An embodiment of the present invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. When a memory operation attempts to update a cache line that may not be updated, the circuit attempts to upgrade the cache line. If this fails, a rollback request is generated that indicates the trace involved. The checkpoint locations associated with the indicated trace are overwritten along with those locations associated with all younger traces.
摘要翻译：本发明的一个实施例包括用于跟踪基于跟踪的执行的存储器操作的电路。每个跟踪包括包括零个或多个存储器操作的一系列操作。正在执行的存储器操作形成一组活动存储器操作，它们之间具有预定义的程序顺序和相应的排序限制。至少一些主动存储器操作以与程序顺序不同的执行顺序访问存储器。检查点条目与每个跟踪相关联。当内存操作尝试更新可能未更新的高速缓存行时，该电路会尝试升级缓存行。如果失败，则会生成一个回滚请求，指示涉及的跟踪。与指示轨迹相关联的检查点位置与与所有较年轻轨迹相关联的那些位置被覆盖。

5. 发明授权

US07779307B1 Memory ordering queue tightly coupled with a versioning cache circuit 有权
标题翻译：存储器排序队列与版本缓存电路紧密耦合
公开(公告)号：US07779307B1
公开(公告)日：2010-08-17
申请号：US12030857
申请日：2008-02-13
申请人： John Gregory Favor , Paul G. Chan , Graham Ricketson Murphy , Joseph Byron Rowlands
发明人： John Gregory Favor , Paul G. Chan , Graham Ricketson Murphy , Joseph Byron Rowlands
IPC分类号： G06F11/00
CPC分类号： G06F11/1407
摘要： An embodiment of the present invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. There is a one-to-one correspondence between checkpoint entries and memory operation ordering entries. Each checkpoint entry refers to a checkpoint location. Rollback requests cause the circuit to overwrite checkpoint entries associated with the corresponding trace.
摘要翻译：本发明的一个实施例包括用于跟踪基于跟踪的执行的存储器操作的电路。每个跟踪包括包括零个或多个存储器操作的一系列操作。正在执行的存储器操作形成一组活动存储器操作，它们之间具有预定义的程序顺序和相应的排序限制。至少一些主动存储器操作以与程序顺序不同的执行顺序访问存储器。检查点条目与每个跟踪相关联。检查点条目和内存操作顺序条目之间存在一一对应关系。每个检查点条目指的是检查点位置。回滚请求导致电路覆盖与相应跟踪相关联的检查点条目。

6. 发明授权

US08051247B1 Trace based deallocation of entries in a versioning cache circuit 有权
标题翻译：版本缓存电路中的条目的基于跟踪的解除分配
公开(公告)号：US08051247B1
公开(公告)日：2011-11-01
申请号：US12030846
申请日：2008-02-13
申请人： John Gregory Favor , Paul G. Chan , Graham Ricketson Murphy , Joseph Byron Rowlands
发明人： John Gregory Favor , Paul G. Chan , Graham Ricketson Murphy , Joseph Byron Rowlands
IPC分类号： G06F9/00 , G06F13/00
CPC分类号： G06F9/3004 , G06F9/3808 , G06F9/3834 , G06F9/3851 , G06F9/3857 , G06F9/3863
摘要： A circuit for tracking memory operations with trace-based execution is disclosed. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. Each entry refers to a checkpoint location. Executing one of the active memory operations updates a checkpoint location. During the operation of the circuit, none of the operations of a given trace has any effect on the execution unit's architectural state prior to committing that trace. Each trace becomes eligible for commitment after all operations in the trace complete executing. After the trace is committed, all of the checkpoint entries associated with the trace are invalidated.
摘要翻译：公开了一种用于跟踪基于跟踪的执行的存储器操作的电路。每个跟踪包括包括零个或多个存储器操作的一系列操作。正在执行的存储器操作形成一组在其间具有预定义的程序顺序的活动存储器操作。至少一些主动存储器操作以与程序顺序不同的执行顺序访问存储器。检查点条目与每个跟踪相关联。每个条目指的是检查点位置。执行其中一个活动内存操作更新检查点位置。在电路运行期间，在提交跟踪之前，给定跟踪的任何操作都不会对执行单元的架构状态产生任何影响。轨迹中的所有操作完成执行后，每个轨迹都将有资格获得承诺。提交跟踪后，与跟踪相关联的所有检查点条目都将失效。

7. 发明授权

US07877630B1 Trace based rollback of a speculatively updated cache 有权
标题翻译：推测更新的缓存的基于跟踪的回滚
公开(公告)号：US07877630B1
公开(公告)日：2011-01-25
申请号：US12030852
申请日：2008-02-13
申请人： John Gregory Favor , Paul G. Chan , Graham Ricketson Murphy , Joseph Byron Rowlands
发明人： John Gregory Favor , Paul G. Chan , Graham Ricketson Murphy , Joseph Byron Rowlands
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F9/3004 , G06F9/3808 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3863 , G06F11/3648
摘要： This invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. Traces execute atomically and become eligible for commitment after all the operations in the trace have executed. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. Each entry refers to a checkpoint location. Memory operation ordering entries correspond to each one of the active memory operations. Rollback requests result in overwriting the checkpoint locations associated with the selected trace as well as the checkpoint locations associated with traces that are younger than the selected trace.
摘要翻译：本发明包括用于跟踪基于跟踪的执行的存储器操作的电路。每个跟踪包括包括零个或多个存储器操作的一系列操作。跟踪中的所有操作执行完毕后，跟踪将以原子方式执行并成为合格的承诺。正在执行的存储器操作形成一组活动存储器操作，它们之间具有预定义的程序顺序和相应的排序限制。至少一些主动存储器操作以与程序顺序不同的执行顺序访问存储器。检查点条目与每个跟踪相关联。每个条目指的是检查点位置。存储器操作排序条目对应于每个活动存储器操作。回滚请求导致覆盖与所选跟踪相关联的检查点位置以及与所选跟踪较年轻的跟踪关联的检查点位置。

8. 发明授权

US08370576B1 Cache rollback acceleration via a bank based versioning cache ciruit 有权
标题翻译：通过基于银行的版本缓存缓存来缓存回滚加速
公开(公告)号：US08370576B1
公开(公告)日：2013-02-05
申请号：US12030858
申请日：2008-02-13
申请人： John Gregory Favor , Paul G. Chan , Graham Ricketson Murphy , Joseph Byron Rowlands
发明人： John Gregory Favor , Paul G. Chan , Graham Ricketson Murphy , Joseph Byron Rowlands
IPC分类号： G06F12/00
CPC分类号： G06F12/0855 , G06F9/3863 , Y02D10/13
摘要： An embodiment of the present invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. At least some of the active memory operations access the memory in an execution order that is different from the program order. The circuit includes a first memory that caches data accessed by the memory operations. This memory is partitioned into N banks. Checkpoint entries, which are stored in a second memory also partitioned into N banks, are associated with each trace. Each entry refers to a checkpoint location in the first memory. A sub-circuit receives rollback requests and responds by overwriting checkpoint locations. Each of the N memory units consisting of a bank in the first memory and the corresponding bank in the second memory may be rolled back independently and concurrently with other memory units.
摘要翻译：本发明的一个实施例包括用于跟踪基于跟踪的执行的存储器操作的电路。每个跟踪包括包括零个或多个存储器操作的一系列操作。至少一些主动存储器操作以与程序顺序不同的执行顺序访问存储器。该电路包括缓存由存储器操作访问的数据的第一存储器。该内存被划分为N个存储区。存储在也划分为N个存储区的第二个存储器中的检查点条目与每个跟踪相关联。每个条目是指第一个内存中的检查点位置。子电路接收回滚请求并通过覆盖检查点位置进行响应。由第一存储器中的存储体和第二存储器中的相应存储体组成的N个存储器单元中的每一个可以独立地并与其它存储器单元一起回滚。

9. 发明授权

US08019944B1 Checking for a memory ordering violation after a speculative cache write 有权
标题翻译：在推测缓存写入后检查内存排序违规
公开(公告)号：US08019944B1
公开(公告)日：2011-09-13
申请号：US12030862
申请日：2008-02-13
申请人： John Gregory Favor , Paul G. Chan , Graham Ricketson Murphy , Joseph Byron Rowlands
发明人： John Gregory Favor , Paul G. Chan , Graham Ricketson Murphy , Joseph Byron Rowlands
IPC分类号： G06F9/00 , G06F13/00
CPC分类号： G06F9/3808 , G06F9/3826 , G06F9/3834 , G06F9/384 , G06F9/3857 , G06F9/3859 , G06F9/3863 , G06F9/3867 , G06F9/3873 , G06F12/0831 , G06F2212/507 , Y02D10/13
摘要： An embodiment of the present invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. Violations of the ordering constraints may be signaled too late to prevent an update of the cached data associated with the memory operations. A sub-circuit detects this condition and invalidates the checkpoint locations indicated by the checkpoint entries associated with the trace experiencing the violation and all younger traces.
摘要翻译：本发明的一个实施例包括用于跟踪基于跟踪的执行的存储器操作的电路。每个跟踪包括包括零个或多个存储器操作的一系列操作。正在执行的存储器操作形成一组活动存储器操作，它们之间具有预定义的程序顺序和相应的排序限制。至少一些主动存储器操作以与程序顺序不同的执行顺序访问存储器。检查点条目与每个跟踪相关联。违反订购约束的信号可能太晚，以防止与存储器操作相关联的缓存数据的更新。子电路检测到这种情况，并使由与经历违规的跟踪相关联的检查点条目指示的检查点位置和所有较年轻的跟踪无效。

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