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1. 发明授权

US06248635B1 Process for fabricating a bit-line in a monos device using a dual layer hard mask 有权
标题翻译：使用双层硬掩模在单体器件中制造位线的工艺
公开(公告)号：US06248635B1
公开(公告)日：2001-06-19
申请号：US09426205
申请日：1999-10-25
申请人： David K. Foote , Hideki Komori , Bharath Rangarajan , Steven K. Park
发明人： David K. Foote , Hideki Komori , Bharath Rangarajan , Steven K. Park
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833 , Y10S438/954
摘要： A process for fabricating a MONOS device having a buried bit-line includes providing a semiconductor substrate and forming an ONO structure to overlie the semiconductor substrate. Thereafter, a thin mask layer is formed to overlie the ONO structure to protect the ONO structure during a selective etch of a thick mask layer. The thick mask layer is formed to overlie the thin mask layer to protect the ONO structure during boron and arsenic implants. Thereafter, an etch process is performed in the ONO structure and a silicon oxide layer is formed to fill the etched area. A chemical-mechanical-polishing process is performed to planarize the silicon oxide layer and to form a planar surface continuous with an upper surface of the thick mask layer. The planarized silicon oxide layer functions as a bit-line oxide layer.
摘要翻译：用于制造具有掩埋位线的MONOS器件的工艺包括提供半导体衬底并形成ONO结构以覆盖半导体衬底。此后，形成薄的掩模层以覆盖ONO结构以在厚掩模层的选择性蚀刻期间保护ONO结构。形成厚掩模层以覆盖薄掩模层以在硼和砷注入中保护ONO结构。此后，在ONO结构中进行蚀刻处理，并且形成氧化硅层以填充蚀刻区域。进行化学机械抛光工艺以平坦化氧化硅层并形成与厚掩模层的上表面连续的平面。平坦化的氧化硅层用作位线氧化物层。

2. 发明授权

US06297143B1 Process for forming a bit-line in a MONOS device 有权
标题翻译：在MONOS设备中形成位线的过程
公开(公告)号：US06297143B1
公开(公告)日：2001-10-02
申请号：US09426743
申请日：1999-10-25
申请人： David K. Foote , Bharath Rangarajan , Fei Wang , Steven K. Park
发明人： David K. Foote , Bharath Rangarajan , Fei Wang , Steven K. Park
IPC分类号： H01L214763
CPC分类号： H01L27/11568 , H01L27/11517
摘要： A process for fabricating a MONOS device having a buried bit-line includes providing a semiconductor substrate and forming a mask layer overlying the semiconductor substrate. Thereafter, an etch process is performed to form a trench in the semiconductor substrate. Next, the mask layer is removed and the trench in the semiconductor substrate is filled with a silicon oxide layer. To form a bit-line oxide layer, a planarization process is utilized to planarize the silicon oxide layer and form a planar surface continuous with an upper surface of the semiconductor substrate.
摘要翻译：用于制造具有掩埋位线的MONOS器件的工艺包括提供半导体衬底并形成覆盖半导体衬底的掩模层。此后，进行蚀刻处理以在半导体衬底中形成沟槽。接下来，去除掩模层，并且用氧化硅层填充半导体衬底中的沟槽。为了形成位线氧化层，利用平面化工艺来平坦化氧化硅层并形成与半导体衬底的上表面连续的平面。

3. 发明授权

US06207502B1 Method of using source/drain nitride for periphery field oxide and bit-line oxide 有权
标题翻译：用于外围场氧化物和位线氧化物的源极/漏极氮化物的方法
公开(公告)号：US06207502B1
公开(公告)日：2001-03-27
申请号：US09426255
申请日：1999-10-25
申请人： Kenneth Au , David K. Foote , Steven K. Park , Fei Wang , Bharath Rangarajan
发明人： Kenneth Au , David K. Foote , Steven K. Park , Fei Wang , Bharath Rangarajan
IPC分类号： H01L218247
CPC分类号： H01L27/11568
摘要： A process for fabricating a MONOS type Flash cell device having a periphery field oxide region and a bit-line region includes providing a semiconductor substrate and growing a barrier silicon oxide layer to overlie semiconductor substrate. Thereafter, a thick silicon nitride layer is formed to overlie the barrier silicon oxide layer. A mask and etch are performed at the periphery of the MONOS type cell to form a trench in the semiconductor substrate. The periphery field oxide region is formed by depositing silicon oxide to fill the trench. Thereafter, a mask and etch are performed at the core of the MONOS cell to form a trench in the semiconductor substrate. The bit-line oxide region is formed by depositing silicon oxide to fill the trench. Thereafter, the thick silicon nitride layer is removed. Since the periphery field oxide region and bit-line region are formed before the thick nitride layer is removed, the formation of an unwanted bird's beak is reduced.
摘要翻译：一种制造具有外围场氧化物区域和位线区域的MONOS型闪存单元器件的工艺包括：提供半导体衬底并生长覆盖半导体衬底的势垒氧化硅层。此后，形成厚的氮化硅层以覆盖阻挡氧化硅层。在MONOS型电池的外围进行掩模和蚀刻，以在半导体衬底中形成沟槽。通过沉积氧化硅以填充沟槽而形成外围场氧化物区域。此后，在MONOS单元的核心处进行掩模和蚀刻，以在半导体衬底中形成沟槽。位线氧化物区域通过沉积氧化硅以填充沟槽而形成。此后，去除厚的氮化硅层。由于在去除厚氮化物层之前形成外围场氧化物区域和位线区域，所以不希望的鸟喙形成减少。

4. 发明授权

US06326268B1 Method of fabricating a MONOS flash cell using shallow trench isolation 有权
标题翻译：使用浅沟槽隔离制造MONOS闪存单元的方法
公开(公告)号：US06326268B1
公开(公告)日：2001-12-04
申请号：US09426427
申请日：1999-10-25
申请人： Steven K. Park , Fei Wang , Bharath Rangarajan
发明人： Steven K. Park , Fei Wang , Bharath Rangarajan
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L21/76229 , H01L21/76237
摘要： A process for fabricating a MONOS Flash cell device having a bit-line includes providing a semiconductor substrate and growing a pad silicon oxide layer overlying the semiconductor substrate. Thereafter, a silicon nitride layer is formed overlying the pad silicon oxide layer. A shallow trench isolation etch is performed to form a trench in the semiconductor substrate. Thereafter, a silicon oxide is deposited to fill the trench. To planarize the silicon oxide to an upper of the silicon nitride layer, a chemical-mechanical-polishing process is performed. Thereafter, the silicon nitride layer and the pad silicon oxide layer are removed, and an oxide-nitride-oxide layer is deposited to overlie the semiconductor substrate.
摘要翻译：用于制造具有位线的MONOS闪存单元器件的工艺包括提供半导体衬底并且生长覆盖半导体衬底的焊盘氧化硅层。此后，在衬垫氧化硅层上形成氮化硅层。执行浅沟槽隔离蚀刻以在半导体衬底中形成沟槽。此后，沉积氧化硅以填充沟槽。为了将氧化硅平坦化到氮化硅层的上部，进行化学机械抛光工艺。然后，去除氮化硅层和焊盘氧化硅层，并且沉积氧化物 - 氮化物 - 氧化物层以覆盖在半导体衬底上。

5. 发明授权

US06537881B1 Process for fabricating a non-volatile memory device 有权
标题翻译：用于制造非易失性存储器件的工艺
公开(公告)号：US06537881B1
公开(公告)日：2003-03-25
申请号：US09688504
申请日：2000-10-16
申请人： Bharath Rangarajan , David Foote , Fei Wang , Steven K. Park
发明人： Bharath Rangarajan , David Foote , Fei Wang , Steven K. Park
IPC分类号： H01L213105
CPC分类号： H01L27/11568 , H01L21/26586 , H01L21/28282 , H01L29/66833
摘要： A process for fabricating a non-volatile memory device in which extraneous electrical charge is removed from charge-storage layers during fabrication includes exposing a charge-storage layer to infrared radiation prior to forming additional layers of the non-volatile memory cell. For example, in a memory cell incorporating a dielectric floating-gate electrode, such as silicon nitride, the infrared radiation exposure step is carried out after forming the floating-gate electrodes and prior to formation of the control-gate electrode. By exposing the charge-storage layer to infrared radiation prior to forming additional layers, extraneous electrical charge arising from previous processing steps can be efficiently removed from the floating-gate electrodes.
摘要翻译：一种用于制造非易失性存储器件的方法，其中在制造期间从电荷存储层去除外来电荷包括在形成非易失性存储器单元的附加层之前将电荷存储层暴露于红外辐射。例如，在结合有诸如氮化硅的介质浮栅电极的存储单元中，在形成浮栅电极之后并且在形成控制栅电极之前执行红外辐射曝光步骤。通过在形成附加层之前将电荷存储层暴露于红外辐射，可以从浮栅电极有效地去除先前处理步骤产生的外来电荷。

6. 发明授权

US06218227B1 Method to generate a MONOS type flash cell using polycrystalline silicon as an ONO top layer 有权
标题翻译：使用多晶硅作为ONO顶层生成MONOS型闪存单元的方法
公开(公告)号：US06218227B1
公开(公告)日：2001-04-17
申请号：US09426239
申请日：1999-10-25
申请人： Steven K. Park , Arvind Halliyal , Hideki Komori
发明人： Steven K. Park , Arvind Halliyal , Hideki Komori
IPC分类号： H01L218238
CPC分类号： H01L27/11568 , H01L27/115
摘要： A process for fabricating an ONO structure for a MONOS type Flash cell includes growing a first silicon oxide layer over a semiconductor substrate. Thereafter, a silicon nitride layer is formed to overlie the first silicon oxide layer, and a polycrystalline silicon layer is deposited to overlie the silicon nitride layer. By utilizing the polycrystalline silicon layer as the top layer of the ONO structure, a resist layer can be cleaned more aggressively than if the top layer of the ONO structure were an oxide layer. A second silicon oxide layer overlies the polycrystalline layer, of the ONO structure. Since the second silicon oxide layer is deposited on top of polycrystalline silicon after the resist material is cleaned, some resist material can remain on the polycrystalline layer without degrading the performance of the MONOS type cell.
摘要翻译：用于制造用于MONOS型闪存单元的ONO结构的工艺包括在半导体衬底上生长第一氧化硅层。此后，形成氮化硅层以覆盖第一氧化硅层，并且沉积多晶硅层以覆盖氮化硅层。通过利用多晶硅层作为ONO结构的顶层，与ONO结构的顶层是氧化物层相比，可以更积极地清洗抗蚀剂层。第二氧化硅层覆盖ONO结构的多晶层。由于在抗蚀剂材料被清洁之后第二氧化硅层沉积在多晶硅的顶部上，所以一些抗蚀剂材料可以保留在多晶层上而不降低MONOS型电池的性能。

7. 发明授权

US06548336B2 Planarization of a polysilicon layer surface by chemical mechanical polish to improve lithography and silicide formation 失效
标题翻译：通过化学机械抛光平面化多晶硅层表面，以改善光刻和硅化物形成
公开(公告)号：US06548336B2
公开(公告)日：2003-04-15
申请号：US10067765
申请日：2002-02-08
申请人： Steven C. Avanzino , Steven K. Park
发明人： Steven C. Avanzino , Steven K. Park
IPC分类号： H01L218238
CPC分类号： H01L27/11521 , H01L21/32055 , H01L21/3212 , H01L27/115
摘要： A new device and technique to realize an improved integrated circuit device incorporates an improved polysilicon upper surface. This improvement is achieved by approximately planarizing an upper surface of the polysilicon layer. First, the polysilicon layer is preferably formed as a relatively thicker layer as compared to the layer thickness in a conventional device. Then a portion of the polysilicon layer is removed, preferably utilizing a chemical mechanical polish technique. Thus, this embodiment achieves a relatively planarized upper surface of the polysilicon layer. Then, for example, a conventional metal or silicide layer may be formed upon the relatively planarized polysilicon layer. This approximately planarized upper surface of the polysilicon layer allows for a silicide layer to be formed with a relative reduction in the amount and/or severity of the conventional word line voids and seams.
摘要翻译：实现改进的集成电路器件的新器件和技术结合了改进的多晶硅上表面。这种改进通过近似平坦化多晶硅层的上表面来实现。首先，与常规器件中的层厚相比，多晶硅层优选形成为相对较厚的层。然后，优选利用化学机械抛光技术去除多晶硅层的一部分。因此，本实施例实现了多晶硅层的相对平坦化的上表面。然后，例如，可以在相对平坦化的多晶硅层上形成常规的金属或硅化物层。多晶硅层的近似平坦化的上表面允许形成硅化物层，其中常规字线空隙和接缝的量和/或严重性相对降低。

8. 发明授权

US06180538B2 Process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device using rapid-thermal-chemical-vapor-deposition 失效
标题翻译：在使用快速热化学气相沉积的2位EEPROM器件中制造ONO浮栅电极的工艺
公开(公告)号：US06180538B2
公开(公告)日：2001-01-30
申请号：US09426240
申请日：1999-10-25
申请人： Arvind Halliyal , Robert B. Ogle , Kenneth Au , Steven K. Park
发明人： Arvind Halliyal , Robert B. Ogle , Kenneth Au , Steven K. Park
IPC分类号： H01L2131
CPC分类号： H01L29/7923 , H01L21/28282 , H01L21/3143
摘要： A process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device includes the formation of a first and second oxide layers using a high-temperature-oxide (HTO) deposition process in which the HTO process is carried out at a temperature of about 700 to about 800° C. The process further includes the sequential formation of a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer using an RTCVD process in which the silicon nitride layer is not exposed to ambient atmosphere prior to the formation of the top oxide layer. The formation of the first and second oxide layers using an RTCVD process provides an improved two-bit EEPROM memory device by reducing charge leakage in the ONO floating-gate electrode.
摘要翻译：用于在2位EEPROM器件中制造ONO浮栅电极的工艺包括使用高温氧化物（HTO）沉积工艺形成第一和第二氧化物层，其中HTO工艺在温度约700至约800℃。该方法还包括使用其中氮化硅层不暴露于环境大气的RTCVD工艺来顺序地形成第一氧化硅层，氮化硅层和第二氧化硅层在形成顶部氧化物层之前。使用RTCVD工艺形成第一和第二氧化物层通过减少ONO浮栅电极中的电荷泄漏来提供改进的两位EEPROM存储器件。

9. 发明授权

US06346466B1 Planarization of a polysilicon layer surface by chemical mechanical polish to improve lithography and silicide formation 有权
标题翻译：通过化学机械抛光平面化多晶硅层表面，以改善光刻和硅化物形成
公开(公告)号：US06346466B1
公开(公告)日：2002-02-12
申请号：US09538168
申请日：2000-03-30
申请人： Steven C. Avanzino , Steven K. Park
发明人： Steven C. Avanzino , Steven K. Park
IPC分类号： H01L2120
CPC分类号： H01L27/11521 , H01L21/32055 , H01L21/3212 , H01L27/115
摘要： An improved integrated circuit device that has an improved polysilicon upper surface. This improvement is achieved by approximately planarizing an upper surface of the polysilicon layer. First, the polysilicon layer is preferably formed as a relatively thicker layer as compared to the layer thickness in a conventional device. Then, a portion of the polysilicon layer is removed, preferably utilizing a chemical mechanical polish technique. Thus, this embodiment achieves a relatively planarized upper surface of the polysilicon layer. Then, for example, a conventional metal or silicide layer may be formed upon the relatively planarized polysilicon layer. This approximately planarized upper surface of the polysilicon layer allows for a silicide layer to be formed with a relative reduction in the amount and/or severity of the conventional word line voids and seams.
摘要翻译：一种改进的集成电路器件，其具有改进的多晶硅上表面。这种改进通过近似平坦化多晶硅层的上表面来实现。首先，与常规器件中的层厚相比，多晶硅层优选形成为相对较厚的层。然后，优选利用化学机械抛光技术去除多晶硅层的一部分。因此，本实施例实现了多晶硅层的相对平坦化的上表面。然后，例如，可以在相对平坦化的多晶硅层上形成常规的金属或硅化物层。多晶硅层的近似平坦化的上表面允许形成硅化物层，其中常规字线空隙和接缝的量和/或严重性相对降低。

10. 发明授权

US06323516B1 Flash memory device and fabrication method having a high coupling ratio 有权
标题翻译：具有高耦合比的闪存器件和制造方法
公开(公告)号：US06323516B1
公开(公告)日：2001-11-27
申请号：US09390052
申请日：1999-09-03
申请人： Larry Y. Wang , Steven K. Park
发明人： Larry Y. Wang , Steven K. Park
IPC分类号： H01L29788
CPC分类号： H01L29/42324
摘要： Embodiments of the invention comprise a new device and technique to realize an improved coupling ratio integrated circuit device. This improvement is achieved by increasing an overlap portion between the first and second polysilicon layers, so as to increase the effective coupling ratio between the layers. In the embodiments of the present invention, a relatively tall or large portion of oxide is formed over at least a portion of each of a plurality of shallow trench isolation regions. This oxide is then utilized to provide a larger first polysilicon layer surface area, but without substantially increasing the tunnel oxide layer surface area. Then, a dielectric interlayer is formed upon the surface of the first polysilicon layer, and next, a second polysilicon layer is formed upon the dielectric interlayer. This increased overlap portion thus allows for an increased coupling ratio. Further, the coupling ratio may be tailored by adjusting either or both of the first and second polysilicon layer surface areas without requiring a substantial change in the tunnel oxide layer surface area.
摘要翻译：本发明的实施例包括实现改进的耦合比集成电路器件的新器件和技术。这种改进通过增加第一和第二多晶硅层之间的重叠部分来实现，以便增加层之间的有效耦合比。在本发明的实施例中，在多个浅沟槽隔离区域的每一个的至少一部分上形成相当高或较大部分的氧化物。然后利用该氧化物提供较大的第一多晶硅层表面积，但基本不增加隧道氧化物层的表面积。然后，在第一多晶硅层的表面上形成电介质中间层，接着在电介质中间层上形成第二多晶硅层。这种增加的重叠部分因此允许增加耦合比。此外，可以通过调整第一和第二多晶硅层表面区域中的一个或两个而不需要隧道氧化物层表面积的实质变化来调整耦合比。

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