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1. 发明申请

US20050145958A1 Formation of a disposable spacer to post dope a gate conductor 失效
标题翻译：一次性间隔件的形成以喷涂一个栅极导体
公开(公告)号：US20050145958A1
公开(公告)日：2005-07-07
申请号：US10752386
申请日：2004-01-06
申请人： David Horak , Toshiharu Furukawa , Akihisa Sekiguchi
发明人： David Horak , Toshiharu Furukawa , Akihisa Sekiguchi
IPC分类号： H01L21/28 , H01L21/336 , H01L29/76 , H01L29/78
CPC分类号： H01L29/6653 , H01L21/28035 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method of forming a doped gate structure on a semiconductor device and a semiconductor structure formed in that method are provided. The method comprises the steps of providing a semiconductor device including a gate dielectric layer, and forming a gate stack on said dielectric layer. This latter step, in turn, includes the steps of forming a first gate layer on the dielectric layer, and forming a second disposable layer on top of the first gate layer. A fat spacer is formed around the first gate layer and the second layers. The second disposable layer is removed, and ions are implanted in the first gate layer to supply additional dopant into the gate above the gate dielectric layer, while the fat disposable spacer keeps the implanted ions away from the critical source and drain diffusion region.
摘要翻译：提供了在半导体器件上形成掺杂栅极结构的方法和以该方法形成的半导体结构。该方法包括以下步骤：提供包括栅极电介质层的半导体器件，以及在所述介电层上形成栅叠层。后一步骤又包括以下步骤：在电介质层上形成第一栅极层，以及在第一栅极层的顶部上形成第二一次性层。在第一栅极层和第二层周围形成脂肪间隔物。去除第二一次性层，并且将离子注入第一栅极层中以向栅极电介质层上方的栅极提供附加的掺杂剂，而脂肪一次性间隔物保持注入的离子远离临界源极和漏极扩散区域。

2. 发明申请

US20070205472A1 FORMATION OF A DISPOSABLE SPACER TO POST DOPE A GATE CONDUCTOR 审中-公开
标题翻译：形成一个可打开的间隔器以打开门盖导体
公开(公告)号：US20070205472A1
公开(公告)日：2007-09-06
申请号：US11697371
申请日：2007-04-06
申请人： David Horak , Toshiharu Furukawa , Akihisa Sekiguchi
发明人： David Horak , Toshiharu Furukawa , Akihisa Sekiguchi
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L21/28035 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method of forming a doped gate structure on a semiconductor device and a semiconductor structure formed in that method are provided. The method comprises the steps of providing a semiconductor device including a gate dielectric layer, and forming a gate stack on said dielectric layer. This latter step, in turn, includes the steps of forming a first gate layer on the dielectric layer, and forming a second disposable layer on top of the first gate layer. A fat spacer is formed around the first gate layer and the second disposable layer. The second disposable layer is removed, and ions are implanted in the first gate layer to supply additional dopant into the gate above the gate dielectric layer, while the fat disposable spacer keeps the implanted ions away from the critical source and drain diffusion region.
摘要翻译：提供了在半导体器件上形成掺杂栅极结构的方法和以该方法形成的半导体结构。该方法包括以下步骤：提供包括栅极电介质层的半导体器件，以及在所述介电层上形成栅叠层。后一步骤又包括以下步骤：在电介质层上形成第一栅极层，以及在第一栅极层的顶部上形成第二一次性层。在第一栅极层和第二一次性层周围形成脂肪间隔物。去除第二一次性层，并且将离子注入第一栅极层中以向栅极电介质层上方的栅极提供附加的掺杂剂，而脂肪一次性间隔物保持注入的离子远离临界源极和漏极扩散区域。

3. 发明申请

US20050118764A1 Forming gate oxides having multiple thicknesses 失效
标题翻译：形成具有多个厚度的栅极氧化物
公开(公告)号：US20050118764A1
公开(公告)日：2005-06-02
申请号：US10724483
申请日：2003-11-28
申请人： Anthony Chou , Michael Chudzik , Toshiharu Furukawa , Oleg Gluschenkov , Paul Kirsch , Byoung Lee , Katsunori Onishi , Heemyoung Park , Kristen Scheer , Akihisa Sekiguchi
发明人： Anthony Chou , Michael Chudzik , Toshiharu Furukawa , Oleg Gluschenkov , Paul Kirsch , Byoung Lee , Katsunori Onishi , Heemyoung Park , Kristen Scheer , Akihisa Sekiguchi
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/00 , H01L21/3205 , H01L21/336 , H01L21/84
CPC分类号： H01L21/823462 , H01L21/823857
摘要： Gate oxides having different thicknesses are formed on a semiconductor substrate by forming a first gate oxide on the top surface of the substrate, forming a sacrificial hard mask over a selected area of the first gate oxide; and then forming a second gate oxide. A first poly layer may be formed on the first gate oxide, under the hard mask. After the hard mask is removed, a second poly layer may be formed over the second gate oxide and over the first poly layer. This enables the use of high-k dielectric materials, and the first gate oxide can be thinner than the second gate oxide.
摘要翻译：通过在衬底的顶表面上形成第一栅极氧化物，在半导体衬底上形成具有不同厚度的栅极氧化物，在第一栅极氧化物的选定区域上形成牺牲性硬掩模; 然后形成第二栅极氧化物。可以在硬掩模下的第一栅极氧化物上形成第一多晶硅层。在去除硬掩模之后，可以在第二栅极氧化物之上和第一多晶硅层上形成第二多晶硅层。这使得能够使用高k电介质材料，并且第一栅极氧化物可以比第二栅极氧化物薄。

4. 发明授权

US07160771B2 Forming gate oxides having multiple thicknesses 失效
标题翻译：形成具有多个厚度的栅极氧化物
公开(公告)号：US07160771B2
公开(公告)日：2007-01-09
申请号：US10724483
申请日：2003-11-28
申请人： Anthony I-Chih Chou , Michael Patrick Chudzik , Toshiharu Furukawa , Oleg Gluschenkov , Paul Daniel Kirsch , Byoung Hun Lee , Katsunori Onishi , Heemyoung Park , Kristen Colleen Scheer , Akihisa Sekiguchi
发明人： Anthony I-Chih Chou , Michael Patrick Chudzik , Toshiharu Furukawa , Oleg Gluschenkov , Paul Daniel Kirsch , Byoung Hun Lee , Katsunori Onishi , Heemyoung Park , Kristen Colleen Scheer , Akihisa Sekiguchi
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/3205
CPC分类号： H01L21/823462 , H01L21/823857
摘要： Gate oxides having different thicknesses are formed on a semiconductor substrate by forming a first gate oxide on the top surface of the substrate, forming a sacrificial hard mask over a selected area of the first gate oxide; and then forming a second gate oxide. A first poly layer may be formed on the first gate oxide, under the hard mask. After the hard mask is removed, a second poly layer may be formed over the second gate oxide and over the first poly layer. This enables the use of high-k dielectric materials, and the first gate oxide can be thinner than the second gate oxide.
摘要翻译：通过在衬底的顶表面上形成第一栅极氧化物，在半导体衬底上形成具有不同厚度的栅极氧化物，在第一栅极氧化物的选定区域上形成牺牲性硬掩模; 然后形成第二栅极氧化物。可以在硬掩模下的第一栅极氧化物上形成第一多晶硅层。在去除硬掩模之后，可以在第二栅极氧化物之上和第一多晶硅层上形成第二多晶硅层。这使得能够使用高k电介质材料，并且第一栅极氧化物可以比第二栅极氧化物薄。

5. 发明授权

US06960510B2 Method of making sub-lithographic features 失效
标题翻译：制作亚光刻特征的方法
公开(公告)号：US06960510B2
公开(公告)日：2005-11-01
申请号：US10187579
申请日：2002-07-01
申请人： Sadanand V. Deshpande , Toshiharu Furukawa , David V. Horak , Wesley C. Natzle , Akihisa Sekiguchi , Len Y. Tsou , Qingyun Yang
发明人： Sadanand V. Deshpande , Toshiharu Furukawa , David V. Horak , Wesley C. Natzle , Akihisa Sekiguchi , Len Y. Tsou , Qingyun Yang
IPC分类号： H01L21/033 , H01L21/265 , H01L21/28 , H01L21/308 , H01L21/311 , H01L21/8238 , H01L21/336 , H01L21/8234 , H01L21/8236
CPC分类号： H01L21/26586 , H01L21/0337 , H01L21/0338 , H01L21/2815 , H01L21/3086 , H01L21/3088 , H01L21/31144
摘要： A method of forming a structure having sub-lithographic dimensions is provided. The method includes: forming a chamfered mandrel on a substrate, the mandrel having an angled surface; and performing an angled ion implantation to obtain an implanted shadow region in the substrate, the implanted shadow mask having at least one sub-lithographic dimension.
摘要翻译：提供了形成具有亚光刻尺寸的结构的方法。该方法包括：在基底上形成倒角心轴，心轴具有成角度的表面; 以及执行成角度的离子注入以在所述衬底中获得注入的阴影区域，所述植入的荫罩具有至少一个亚光刻尺寸。

6. 发明授权

US07229885B2 Formation of a disposable spacer to post dope a gate conductor 失效
标题翻译：一次性间隔件的形成以喷涂一个栅极导体
公开(公告)号：US07229885B2
公开(公告)日：2007-06-12
申请号：US10752386
申请日：2004-01-06
申请人： David V. Horak , Toshiharu Furukawa , Akihisa Sekiguchi
发明人： David V. Horak , Toshiharu Furukawa , Akihisa Sekiguchi
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L21/28035 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method of forming a doped gate structure on a semiconductor device and a semiconductor structure formed in that method are provided. The method comprises the steps of providing a semiconductor device including a gate dielectric layer, and forming a gate stack on said dielectric layer. This latter step, in turn, includes the steps of forming a first gate layer on the dielectric layer, and forming a second disposable layer on top of the first gate layer. A fat spacer is formed round the first gate layer and the second disposable layer. The second disposable layer is removed, and ions are implanted in the first gate layer to supply additional dopant into the gate above the gate dielectric layer, while the fat disposable spacer keeps the implanted ions away from the critical source and drain diffusion regions.
摘要翻译：提供了在半导体器件上形成掺杂栅极结构的方法和以该方法形成的半导体结构。该方法包括以下步骤：提供包括栅极电介质层的半导体器件，以及在所述介电层上形成栅叠层。后一步骤又包括以下步骤：在电介质层上形成第一栅极层，以及在第一栅极层的顶部上形成第二一次性层。在第一栅极层和第二一次性层周围形成脂肪间隔物。去除第二一次性层，并且将离子注入第一栅极层中以在栅极电介质层上方的栅极中提供额外的掺杂剂，而脂肪一次性间隔物保持注入的离子远离临界源极和漏极扩散区域。

7. 发明授权

US06821833B1 Method for separately optimizing thin gate dielectric of PMOS and NMOS transistors within the same semiconductor chip and device manufactured thereby 有权
标题翻译：用于分别优化同一半导体芯片内的PMOS和NMOS晶体管的薄栅极电介质及其制造的器件的方法
公开(公告)号：US06821833B1
公开(公告)日：2004-11-23
申请号：US10605110
申请日：2003-09-09
申请人： Anthony I-Chih Chou , Toshiharu Furukawa , Patrick R. Varekamp , Jeffrey W. Sleight , Akihisa Sekiguchi
发明人： Anthony I-Chih Chou , Toshiharu Furukawa , Patrick R. Varekamp , Jeffrey W. Sleight , Akihisa Sekiguchi
IPC分类号： H01L218238
CPC分类号： H01L21/28202 , H01L21/823842 , H01L21/823857
摘要： A method of forming CMOS semiconductor materials with PFET and NFET areas formed on a semiconductor substrate, covered respectively with a PFET and NFET gate dielectric layers composed of silicon oxide and different degrees of nitridation thereof. Provide a silicon substrate with a PFET area and an NFET area and form PFET and NFET gate oxide layers thereover. Provide nitridation of the PFET gate oxide layer above the PFET area to form the PFET gate dielectric layer above the PFET area with a first concentration level of nitrogen atoms in the PFET gate dielectric layer above the PFET area. Provide nitridation of the NFET gate oxide layer to form the NFET gate dielectric layer above the NFET area with a different concentration level of nitrogen atoms from the first concentration level. The NFET gate dielectric layer and the PFET gate dielectric layer can have the same thickness.
摘要翻译：一种形成在半导体衬底上的PFET和NFET区域的CMOS半导体材料的方法，分别覆盖由氧化硅和不同程度的氮化构成的PFET和NFET栅极电介质层。为硅衬底提供PFET区域和NFET区域，并在其上形成PFET和NFET栅极氧化物层。在PFET区域上方提供PFET栅极氧化物层的氮化，以在PFET区域上方形成PFET栅极电介质层上的PFET栅极电介质层，在PFET区域上方的PFET栅极电介质层中具有氮原子的第一浓度水平。提供NFET栅极氧化物层的氮化，以在NFET区域上方形成具有与第一浓度水平不同的氮原子浓度水平的NFET栅极电介质层。 NFET栅极电介质层和PFET栅极电介质层可以具有相同的厚度。

8. 发明授权

US06426305B1 Patterned plasma nitridation for selective epi and silicide formation 失效
标题翻译：用于选择性外延和硅化物形成的图案化等离子体氮化
公开(公告)号：US06426305B1
公开(公告)日：2002-07-30
申请号：US09898202
申请日：2001-07-03
申请人： Anthony I. Chou , Toshiharu Furukawa , Akihisa Sekiguchi
发明人： Anthony I. Chou , Toshiharu Furukawa , Akihisa Sekiguchi
IPC分类号： H01L2131
CPC分类号： H01L21/318 , H01L21/02378 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/28518 , H01L21/28525 , H01L21/3211
摘要： A method of selectively forming either an epi-Si-containing or a silicide layer on portions of a Si-containing substrate wherein a nitrogen-containing layer formed by a low-temperature nitridation process is employed to prevent formation of the epi-Si-containing or silicide layer in predetermined areas of the substrate. The method of the present invention includes the steps of subjecting at least one exposed surface of a Si-containing substrate to a low- temperature nitridation process so as to form a nitrogen-containing layer at or near the at least one exposed surface, wherein other surfaces of the Si-containing substrate are protected by a patterned photoresist; removing the patterned photoresist from the other surfaces of the Si-containing substrate; and forming an epi-Si-containing layer or a silicide layer on the other surfaces of the substrate which do not contain the nitrogen-containing layer. In accordance with the present invention, epi-Si-containing or silicide is not formed in areas containing the nitrogen-containing layer.
摘要翻译：在含Si衬底的部分上选择性地形成外延Si层或硅化物层的方法，其中通过低温氮化工艺形成的含氮层用于防止形成含外延Si 或硅化物层在基板的预定区域中。本发明的方法包括以下步骤：使含Si衬底的至少一个暴露表面进行低温氮化处理，以便在至少一个暴露表面处或附近形成含氮层，其中其它含Si衬底的表面被图案化的光致抗蚀剂保护; 从所述含Si衬底的其它表面去除所述图案化的光致抗蚀剂; 以及在不含有含氮层的基板的其他表面上形成外延Si层或硅化物层。根据本发明，在含有含氮层的区域中不形成含外硅或硅化物。

9. 发明申请

US20080099844A1 MULTIPLE LAYER AND CYRSTAL PLANE ORIENTATION SEMICONDUCTOR SUBSTRATE 有权
标题翻译：多层和单层平面定向半导体基板
公开(公告)号：US20080099844A1
公开(公告)日：2008-05-01
申请号：US11969320
申请日：2008-01-04
申请人： Toshiharu Furukawa , David Horak , Charles Koburger , Leathen Shi
发明人： Toshiharu Furukawa , David Horak , Charles Koburger , Leathen Shi
IPC分类号： H01L29/786
CPC分类号： H01L29/045 , H01L21/76254 , H01L21/823807 , H01L27/1203
摘要： A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction.
摘要翻译：绝缘体上半导体衬底及其制造方法。所述基板包括：第一晶体半导体层和第二晶体半导体层; 以及将所述第一晶体半导体层的底面与所述第二结晶半导体层的顶面接合的绝缘层，所述第一结晶半导体层相对于所述第二结晶半导体层的第二晶体方向排列的第一晶体方向，第一晶体方向与第二晶体方向不同。

10. 发明申请

US20080001225A1 MICROELECTRONIC STRUCTURE BY SELECTIVE DEPOSITION 有权
标题翻译：通过选择性沉积的微电子结构
公开(公告)号：US20080001225A1
公开(公告)日：2008-01-03
申请号：US11307294
申请日：2006-01-31
申请人： Toshiharu Furukawa , Steven Holmes , David Horak , Charles Koburger
发明人： Toshiharu Furukawa , Steven Holmes , David Horak , Charles Koburger
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7851 , H01L29/42384 , H01L29/66795 , H01L29/78645
摘要： A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate, so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.
摘要翻译： finFET结构包括位于衬底上的半导体鳍片。栅电极穿过半导体鳍片。栅电极具有邻接其侧壁的间隔层。间隔层不完全覆盖半导体鳍片的侧壁。栅电极和间隔层可以使用气相沉积法形成，该方法提供选择性沉积在心轴层的侧壁上而不是在基底的相邻表面上，使得间隔层不完全覆盖半导体鳍片可以使用侧向生长方法制造其它微电子结构。

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