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1. 发明授权

US07160771B2 Forming gate oxides having multiple thicknesses 失效
标题翻译：形成具有多个厚度的栅极氧化物
公开(公告)号：US07160771B2
公开(公告)日：2007-01-09
申请号：US10724483
申请日：2003-11-28
申请人： Anthony I-Chih Chou , Michael Patrick Chudzik , Toshiharu Furukawa , Oleg Gluschenkov , Paul Daniel Kirsch , Byoung Hun Lee , Katsunori Onishi , Heemyoung Park , Kristen Colleen Scheer , Akihisa Sekiguchi
发明人： Anthony I-Chih Chou , Michael Patrick Chudzik , Toshiharu Furukawa , Oleg Gluschenkov , Paul Daniel Kirsch , Byoung Hun Lee , Katsunori Onishi , Heemyoung Park , Kristen Colleen Scheer , Akihisa Sekiguchi
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/3205
CPC分类号： H01L21/823462 , H01L21/823857
摘要： Gate oxides having different thicknesses are formed on a semiconductor substrate by forming a first gate oxide on the top surface of the substrate, forming a sacrificial hard mask over a selected area of the first gate oxide; and then forming a second gate oxide. A first poly layer may be formed on the first gate oxide, under the hard mask. After the hard mask is removed, a second poly layer may be formed over the second gate oxide and over the first poly layer. This enables the use of high-k dielectric materials, and the first gate oxide can be thinner than the second gate oxide.
摘要翻译：通过在衬底的顶表面上形成第一栅极氧化物，在半导体衬底上形成具有不同厚度的栅极氧化物，在第一栅极氧化物的选定区域上形成牺牲性硬掩模; 然后形成第二栅极氧化物。可以在硬掩模下的第一栅极氧化物上形成第一多晶硅层。在去除硬掩模之后，可以在第二栅极氧化物之上和第一多晶硅层上形成第二多晶硅层。这使得能够使用高k电介质材料，并且第一栅极氧化物可以比第二栅极氧化物薄。

2. 发明申请

US20050118764A1 Forming gate oxides having multiple thicknesses 失效
标题翻译：形成具有多个厚度的栅极氧化物
公开(公告)号：US20050118764A1
公开(公告)日：2005-06-02
申请号：US10724483
申请日：2003-11-28
申请人： Anthony Chou , Michael Chudzik , Toshiharu Furukawa , Oleg Gluschenkov , Paul Kirsch , Byoung Lee , Katsunori Onishi , Heemyoung Park , Kristen Scheer , Akihisa Sekiguchi
发明人： Anthony Chou , Michael Chudzik , Toshiharu Furukawa , Oleg Gluschenkov , Paul Kirsch , Byoung Lee , Katsunori Onishi , Heemyoung Park , Kristen Scheer , Akihisa Sekiguchi
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/00 , H01L21/3205 , H01L21/336 , H01L21/84
CPC分类号： H01L21/823462 , H01L21/823857
摘要： Gate oxides having different thicknesses are formed on a semiconductor substrate by forming a first gate oxide on the top surface of the substrate, forming a sacrificial hard mask over a selected area of the first gate oxide; and then forming a second gate oxide. A first poly layer may be formed on the first gate oxide, under the hard mask. After the hard mask is removed, a second poly layer may be formed over the second gate oxide and over the first poly layer. This enables the use of high-k dielectric materials, and the first gate oxide can be thinner than the second gate oxide.
摘要翻译：通过在衬底的顶表面上形成第一栅极氧化物，在半导体衬底上形成具有不同厚度的栅极氧化物，在第一栅极氧化物的选定区域上形成牺牲性硬掩模; 然后形成第二栅极氧化物。可以在硬掩模下的第一栅极氧化物上形成第一多晶硅层。在去除硬掩模之后，可以在第二栅极氧化物之上和第一多晶硅层上形成第二多晶硅层。这使得能够使用高k电介质材料，并且第一栅极氧化物可以比第二栅极氧化物薄。

3. 发明授权

US06821833B1 Method for separately optimizing thin gate dielectric of PMOS and NMOS transistors within the same semiconductor chip and device manufactured thereby 有权
标题翻译：用于分别优化同一半导体芯片内的PMOS和NMOS晶体管的薄栅极电介质及其制造的器件的方法
公开(公告)号：US06821833B1
公开(公告)日：2004-11-23
申请号：US10605110
申请日：2003-09-09
申请人： Anthony I-Chih Chou , Toshiharu Furukawa , Patrick R. Varekamp , Jeffrey W. Sleight , Akihisa Sekiguchi
发明人： Anthony I-Chih Chou , Toshiharu Furukawa , Patrick R. Varekamp , Jeffrey W. Sleight , Akihisa Sekiguchi
IPC分类号： H01L218238
CPC分类号： H01L21/28202 , H01L21/823842 , H01L21/823857
摘要： A method of forming CMOS semiconductor materials with PFET and NFET areas formed on a semiconductor substrate, covered respectively with a PFET and NFET gate dielectric layers composed of silicon oxide and different degrees of nitridation thereof. Provide a silicon substrate with a PFET area and an NFET area and form PFET and NFET gate oxide layers thereover. Provide nitridation of the PFET gate oxide layer above the PFET area to form the PFET gate dielectric layer above the PFET area with a first concentration level of nitrogen atoms in the PFET gate dielectric layer above the PFET area. Provide nitridation of the NFET gate oxide layer to form the NFET gate dielectric layer above the NFET area with a different concentration level of nitrogen atoms from the first concentration level. The NFET gate dielectric layer and the PFET gate dielectric layer can have the same thickness.
摘要翻译：一种形成在半导体衬底上的PFET和NFET区域的CMOS半导体材料的方法，分别覆盖由氧化硅和不同程度的氮化构成的PFET和NFET栅极电介质层。为硅衬底提供PFET区域和NFET区域，并在其上形成PFET和NFET栅极氧化物层。在PFET区域上方提供PFET栅极氧化物层的氮化，以在PFET区域上方形成PFET栅极电介质层上的PFET栅极电介质层，在PFET区域上方的PFET栅极电介质层中具有氮原子的第一浓度水平。提供NFET栅极氧化物层的氮化，以在NFET区域上方形成具有与第一浓度水平不同的氮原子浓度水平的NFET栅极电介质层。 NFET栅极电介质层和PFET栅极电介质层可以具有相同的厚度。

4. 发明授权

US07932136B2 Source/drain junction for high performance MOSFET formed by selective EPI process 有权
标题翻译：通过选择性EPI工艺形成的高性能MOSFET的源极/漏极结
公开(公告)号：US07932136B2
公开(公告)日：2011-04-26
申请号：US12109025
申请日：2008-04-24
申请人： Xuefeng Hua , Johnathan E. Faltermeier , Toshiharu Furukawa , Oleg Gluschenkov
发明人： Xuefeng Hua , Johnathan E. Faltermeier , Toshiharu Furukawa , Oleg Gluschenkov
IPC分类号： H01L21/00
CPC分类号： H01L29/66636 , H01L29/1083 , H01L29/665 , H01L29/6653 , H01L29/66772 , H01L29/7848 , H01L29/78609 , H01L29/78621 , H01L29/78696
摘要： In a field effect transistor (FET), halo features may be formed by etching into the surface of a silicon layer followed by a step of growing a first epitaxial silicon (epi-Si) layer on the etched silicon layer. Source (S) and drain (D), as well as S/D extension features may similarly be formed by etching an epitaxial silicon layer, then filling with another epitaxial layer. Source and Drain, and extensions, and halo, which are normally formed by diffusion, may be formed as discrete elements by etching and filling (epi-Si). This may provide a shallow, highly activated, abrupt S/D extension, an optimally formed halo and deep S/D diffusion doping, and maximized improvement of channel mobility from the compressive or tensile stress from e-SiGe or e-SiC.
摘要翻译：在场效应晶体管（FET）中，可以通过蚀刻到硅层的表面中，随后在蚀刻的硅层上生长第一外延硅（epi-Si）层的步骤来形成晕圈特征。源极（S）和漏极（D）以及S / D延伸特征可以类似地通过蚀刻外延硅层形成，然后用另一个外延层填充。通常通过扩散形成的源极和漏极，延伸部分和光晕可以通过蚀刻和填充（epi-Si）形成为离散元件。这可以提供浅的，高活化的，突然的S / D延伸，最佳形成的光晕和深S / D扩散掺杂，并且最大限度地改善来自e-SiGe或e-SiC的压缩或拉伸应力的沟道迁移率。

5. 发明申请

US20090267149A1 SOURCE/DRAIN JUNCTION FOR HIGH PERFORMANCE MOSFET FORMED BY SELECTIVE EPI PROCESS 有权
标题翻译：通过选择性EPI工艺形成的高性能MOSFET的源极/漏极连接
公开(公告)号：US20090267149A1
公开(公告)日：2009-10-29
申请号：US12109025
申请日：2008-04-24
申请人： Xuefeng Hua , Johnathan E. Faltermeier , Toshiharu Furukawa , Oleg Gluschenkov
发明人： Xuefeng Hua , Johnathan E. Faltermeier , Toshiharu Furukawa , Oleg Gluschenkov
IPC分类号： H01L29/786 , H01L21/336 , H01L21/84
CPC分类号： H01L29/66636 , H01L29/1083 , H01L29/665 , H01L29/6653 , H01L29/66772 , H01L29/7848 , H01L29/78609 , H01L29/78621 , H01L29/78696
摘要： In a field effect transistor (FET), halo features may be formed by etching into the surface of a silicon layer followed by a step of growing a first epitaxial silicon (epi-Si) layer on the etched silicon layer. Source (S) and drain (D), as well as S/D extension features may similarly be formed by etching an epitaxial silicon layer, then filling with another epitaxial layer. Source and Drain, and extensions, and halo, which are normally formed by diffusion, may be formed as discrete elements by etching and filling (epi-Si). This may provide a shallow, highly activated, abrupt S/D extension, an optimally formed halo and deep S/D diffusion doping, and maximized improvement of channel mobility from the compressive or tensile stress from e-SiGe or e-SiC.
摘要翻译：在场效应晶体管（FET）中，可以通过蚀刻到硅层的表面中，随后在蚀刻的硅层上生长第一外延硅（epi-Si）层的步骤来形成晕圈特征。源极（S）和漏极（D）以及S / D延伸特征可以类似地通过蚀刻外延硅层形成，然后用另一个外延层填充。通常通过扩散形成的源极和漏极，延伸部分和光晕可以通过蚀刻和填充（epi-Si）形成为离散元件。这可以提供浅的，高活化的，突然的S / D延伸，最佳形成的光晕和深S / D扩散掺杂，并且最大限度地改善来自e-SiGe或e-SiC的压缩或拉伸应力的沟道迁移率。

6. 发明授权

US06930060B2 Method for forming a uniform distribution of nitrogen in silicon oxynitride gate dielectric 失效
标题翻译：在氮氧化硅栅极电介质中形成氮均匀分布的方法
公开(公告)号：US06930060B2
公开(公告)日：2005-08-16
申请号：US10250257
申请日：2003-06-18
申请人： Anthony I. Chou , Michael P. Chudzik , Toshiharu Furukawa , Oleg Gluschenkov , Paul D. Kirsch , Kristen C. Scheer , Joseph Shepard, Jr.
发明人： Anthony I. Chou , Michael P. Chudzik , Toshiharu Furukawa , Oleg Gluschenkov , Paul D. Kirsch , Kristen C. Scheer , Joseph Shepard, Jr.
IPC分类号： H01L21/28 , H01L21/314 , H01L21/316 , H01L29/51 , H01L21/31 , H01L29/76
CPC分类号： H01L21/0228 , H01L21/0214 , H01L21/02148 , H01L21/02205 , H01L21/02211 , H01L21/02299 , H01L21/28167 , H01L21/28194 , H01L21/28202 , H01L21/28282 , H01L21/3144 , H01L21/31645 , H01L29/513 , H01L29/518
摘要： Methods for preparing a silicon oxynitride layer where the silicon oxynitride layer is deposited atop a substrate and have a low concentration of nitrogen at the interface of the silicon oxynitride layer and the substrate. The silicon oxynitride layer is formed by pulsing at least one interface precursor onto a substrate, where said substrate chemisorbs a portion of said at least one interface precursor to form a monolayer of said at least one interface precursor; and pulsing a nitrogen-containing precursor onto said substrate containing said monolayer of interface precursor, where said monolayer of said at least one interface precursor chemisorbs a portion of said nitrogen-containing precursor to form a monolayer of said nitrogen-containing precursor. The interface precursor includes oxygen-containing or silicon-containing precursor gasses.
摘要翻译：制备氮氧化硅层的方法，其中氧氮化硅层沉积在基板顶部并且在氮氧化硅层和基板的界面处具有低浓度的氮。通过将至少一种界面前体脉冲至基底上形成氧氮化硅层，其中所述基底化学吸附所述至少一种界面前体的一部分以形成所述至少一种界面前体的单层; 并且将含氮前体脉冲至含有所述界面前体单层的所述基质上，其中所述至少一种界面前体的所述单层化学吸附所述含氮前体的一部分以形成所述含氮前体的单层。界面前体包括含氧或含硅的前体气体。

7. 发明授权

US06960510B2 Method of making sub-lithographic features 失效
标题翻译：制作亚光刻特征的方法
公开(公告)号：US06960510B2
公开(公告)日：2005-11-01
申请号：US10187579
申请日：2002-07-01
申请人： Sadanand V. Deshpande , Toshiharu Furukawa , David V. Horak , Wesley C. Natzle , Akihisa Sekiguchi , Len Y. Tsou , Qingyun Yang
发明人： Sadanand V. Deshpande , Toshiharu Furukawa , David V. Horak , Wesley C. Natzle , Akihisa Sekiguchi , Len Y. Tsou , Qingyun Yang
IPC分类号： H01L21/033 , H01L21/265 , H01L21/28 , H01L21/308 , H01L21/311 , H01L21/8238 , H01L21/336 , H01L21/8234 , H01L21/8236
CPC分类号： H01L21/26586 , H01L21/0337 , H01L21/0338 , H01L21/2815 , H01L21/3086 , H01L21/3088 , H01L21/31144
摘要： A method of forming a structure having sub-lithographic dimensions is provided. The method includes: forming a chamfered mandrel on a substrate, the mandrel having an angled surface; and performing an angled ion implantation to obtain an implanted shadow region in the substrate, the implanted shadow mask having at least one sub-lithographic dimension.
摘要翻译：提供了形成具有亚光刻尺寸的结构的方法。该方法包括：在基底上形成倒角心轴，心轴具有成角度的表面; 以及执行成角度的离子注入以在所述衬底中获得注入的阴影区域，所述植入的荫罩具有至少一个亚光刻尺寸。

8. 发明申请

US20050145958A1 Formation of a disposable spacer to post dope a gate conductor 失效
标题翻译：一次性间隔件的形成以喷涂一个栅极导体
公开(公告)号：US20050145958A1
公开(公告)日：2005-07-07
申请号：US10752386
申请日：2004-01-06
申请人： David Horak , Toshiharu Furukawa , Akihisa Sekiguchi
发明人： David Horak , Toshiharu Furukawa , Akihisa Sekiguchi
IPC分类号： H01L21/28 , H01L21/336 , H01L29/76 , H01L29/78
CPC分类号： H01L29/6653 , H01L21/28035 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method of forming a doped gate structure on a semiconductor device and a semiconductor structure formed in that method are provided. The method comprises the steps of providing a semiconductor device including a gate dielectric layer, and forming a gate stack on said dielectric layer. This latter step, in turn, includes the steps of forming a first gate layer on the dielectric layer, and forming a second disposable layer on top of the first gate layer. A fat spacer is formed around the first gate layer and the second layers. The second disposable layer is removed, and ions are implanted in the first gate layer to supply additional dopant into the gate above the gate dielectric layer, while the fat disposable spacer keeps the implanted ions away from the critical source and drain diffusion region.
摘要翻译：提供了在半导体器件上形成掺杂栅极结构的方法和以该方法形成的半导体结构。该方法包括以下步骤：提供包括栅极电介质层的半导体器件，以及在所述介电层上形成栅叠层。后一步骤又包括以下步骤：在电介质层上形成第一栅极层，以及在第一栅极层的顶部上形成第二一次性层。在第一栅极层和第二层周围形成脂肪间隔物。去除第二一次性层，并且将离子注入第一栅极层中以向栅极电介质层上方的栅极提供附加的掺杂剂，而脂肪一次性间隔物保持注入的离子远离临界源极和漏极扩散区域。

9. 发明申请

US20070205472A1 FORMATION OF A DISPOSABLE SPACER TO POST DOPE A GATE CONDUCTOR 审中-公开
标题翻译：形成一个可打开的间隔器以打开门盖导体
公开(公告)号：US20070205472A1
公开(公告)日：2007-09-06
申请号：US11697371
申请日：2007-04-06
申请人： David Horak , Toshiharu Furukawa , Akihisa Sekiguchi
发明人： David Horak , Toshiharu Furukawa , Akihisa Sekiguchi
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L21/28035 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method of forming a doped gate structure on a semiconductor device and a semiconductor structure formed in that method are provided. The method comprises the steps of providing a semiconductor device including a gate dielectric layer, and forming a gate stack on said dielectric layer. This latter step, in turn, includes the steps of forming a first gate layer on the dielectric layer, and forming a second disposable layer on top of the first gate layer. A fat spacer is formed around the first gate layer and the second disposable layer. The second disposable layer is removed, and ions are implanted in the first gate layer to supply additional dopant into the gate above the gate dielectric layer, while the fat disposable spacer keeps the implanted ions away from the critical source and drain diffusion region.
摘要翻译：提供了在半导体器件上形成掺杂栅极结构的方法和以该方法形成的半导体结构。该方法包括以下步骤：提供包括栅极电介质层的半导体器件，以及在所述介电层上形成栅叠层。后一步骤又包括以下步骤：在电介质层上形成第一栅极层，以及在第一栅极层的顶部上形成第二一次性层。在第一栅极层和第二一次性层周围形成脂肪间隔物。去除第二一次性层，并且将离子注入第一栅极层中以向栅极电介质层上方的栅极提供附加的掺杂剂，而脂肪一次性间隔物保持注入的离子远离临界源极和漏极扩散区域。

10. 发明授权

US07229885B2 Formation of a disposable spacer to post dope a gate conductor 失效
标题翻译：一次性间隔件的形成以喷涂一个栅极导体
公开(公告)号：US07229885B2
公开(公告)日：2007-06-12
申请号：US10752386
申请日：2004-01-06
申请人： David V. Horak , Toshiharu Furukawa , Akihisa Sekiguchi
发明人： David V. Horak , Toshiharu Furukawa , Akihisa Sekiguchi
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L21/28035 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method of forming a doped gate structure on a semiconductor device and a semiconductor structure formed in that method are provided. The method comprises the steps of providing a semiconductor device including a gate dielectric layer, and forming a gate stack on said dielectric layer. This latter step, in turn, includes the steps of forming a first gate layer on the dielectric layer, and forming a second disposable layer on top of the first gate layer. A fat spacer is formed round the first gate layer and the second disposable layer. The second disposable layer is removed, and ions are implanted in the first gate layer to supply additional dopant into the gate above the gate dielectric layer, while the fat disposable spacer keeps the implanted ions away from the critical source and drain diffusion regions.
摘要翻译：提供了在半导体器件上形成掺杂栅极结构的方法和以该方法形成的半导体结构。该方法包括以下步骤：提供包括栅极电介质层的半导体器件，以及在所述介电层上形成栅叠层。后一步骤又包括以下步骤：在电介质层上形成第一栅极层，以及在第一栅极层的顶部上形成第二一次性层。在第一栅极层和第二一次性层周围形成脂肪间隔物。去除第二一次性层，并且将离子注入第一栅极层中以在栅极电介质层上方的栅极中提供额外的掺杂剂，而脂肪一次性间隔物保持注入的离子远离临界源极和漏极扩散区域。

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