专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06654858B1 Method for reducing directory writes and latency in a high performance, directory-based, coherency protocol 失效
标题翻译：在高性能，基于目录的一致性协议中减少目录写入和延迟的方法
公开(公告)号：US06654858B1
公开(公告)日：2003-11-25
申请号：US09652324
申请日：2000-08-31
申请人： David H. Asher , Brian Lilly , Richard E. Kessler , Michael Bertone
发明人： David H. Asher , Brian Lilly , Richard E. Kessler , Michael Bertone
IPC分类号： G06F1200
CPC分类号： G06F12/0817 , G06F12/0824
摘要： A computer system has a plurality of processors wherein each processor preferably has its own cache memory. Each processor or group of processors may have a memory controller that interfaces to a main memory. Each main memory includes a “directory” that maintains the directory coherence state of each block of that memory. One or more of the processors are members of a “local” group of processors. Processors outside a local group are referred to as “remote” processors with respect to that local group. Whenever a remote processor performs a memory reference for a particular block of memory, the processor that maintains the directory for that block normally updates the directory to reflect that the remote processor now has exclusive ownership of the block. However, memory references between processors within a local group do not result in directory writes. Instead, the cache memory of the local processor that initiated the memory requests places or updates a copy of the requested data in its cache memory and also sets associated tag control bits to reflect the same or similar information as would have been written to the directory. If a subsequent request is received for that same block, the local processor that previously accessed the block examines its cache for the associated tag control bits. Using those bits, that processor will determine that it currently has the block exclusive and provides the requested data to the new processor that is requesting the data.
摘要翻译：计算机系统具有多个处理器，其中每个处理器优选地具有其自己的高速缓冲存储器。每个处理器或处理器组可以具有与主存储器接口的存储器控制器。每个主存储器包括维护该存储器的每个块的目录一致状态的“目录”。一个或多个处理器是“本地”处理器组的成员。本地组外的处理器称为“本地组”的“远程”处理器。每当远程处理器执行特定内存块的内存引用时，维护该块的目录的处理器通常会更新目录，以反映远程处理器现在拥有该块的独占所有权。但是，本地组内处理器之间的内存引用不会导致目录写入。相反，启动存储器请求的本地处理器的高速缓存存储器将所请求的数据的副本放置或更新在其高速缓冲存储器中，并且还设置相关联的标签控制位以反映与已经写入目录的相同或相似的信息。如果接收到该相同块的后续请求，则先前访问该块的本地处理器检查其相关标签控制位的高速缓存。使用这些位，该处理器将确定其当前具有块排他性，并且向请求数据的新处理器提供所请求的数据。

2. 发明授权

US06681295B1 Fast lane prefetching 有权
标题翻译：快速车道预取
公开(公告)号：US06681295B1
公开(公告)日：2004-01-20
申请号：US09652451
申请日：2000-08-31
申请人： Stephen C. Root , Richard E. Kessler , David H. Asher , Brian Lilly
发明人： Stephen C. Root , Richard E. Kessler , David H. Asher , Brian Lilly
IPC分类号： G06F1200
CPC分类号： G06F9/30047 , G06F9/383 , G06F9/3832 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F12/0862 , G06F12/0864 , G06F2212/6028
摘要： A computer system has a set-associative, multi-way cache system, in which at least one way is designated as a fast lane, and remaining way(s) are designated slow lanes. Any data that needs to be loaded into cache, but is not likely to be needed again in the future, preferably is loaded into the fast lane. Data loaded into the fast lane is earmarked for immediate replacement. Data loaded into the slow lanes preferably is data that may not needed again in the near future. Slow data is kept in cache to permit it to be reused if necessary. The high-performance mechanism of data access in a modem microprocessor is with a prefetch; data is moved, with a special prefetch instruction, into cache prior to its intended use. The prefetch instruction requires less machine resources, than carrying out the same intent with an ordinary load instruction. So, the slow-lane, fast-lane decision is accomplished by having a multiplicity of prefetch instructions. By loading “not likely to be needed again” data into the fast lane, and designating such data for immediate replacement, data in other cache blocks, in the other ways, may not be evicted, and overall system performance is increased.
摘要翻译：计算机系统具有集合关联的多路缓存系统，其中至少一种方式被指定为快速通道，并且剩余方式被指定为慢车道。任何需要加载到缓存中但不太可能再次需要的数据最好被加载到快速通道中。加载到快速通道的数据被指定用于立即更换。加载到慢车道中的数据优选地是在不久的将来可能不再需要的数据。慢数据保存在缓存中，以便在必要时重新使用它。调制解调器微处理器中数据访问的高性能机制具有预取功能; 在预期使用之前，将数据用特殊的预取指令移动到缓存中。预取指令比普通加载指令执行相同的意图要求较少的机器资源。因此，通过具有多个预取指令来实现慢通道，快速通道决定。通过将“不太可能需要再次”的数据加载到快速通道中，并且指定这样的数据以立即替换，以其他方式在其他高速缓存块中的数据可能不被驱逐，并且整体系统性能增加。

3. 发明授权

US07370151B2 Method and system for absorbing defects in high performance microprocessor with a large n-way set associative cache 有权
标题翻译：用大型n路组合关联缓存来吸收高性能微处理器缺陷的方法和系统
公开(公告)号：US07370151B2
公开(公告)日：2008-05-06
申请号：US10690137
申请日：2003-10-21
申请人： David H. Asher , Brian Lilly , Joel Grodstein , Patrick M. Fitzgerald
发明人： David H. Asher , Brian Lilly , Joel Grodstein , Patrick M. Fitzgerald
IPC分类号： G06F13/00
CPC分类号： G11C29/76 , G06F12/0864 , G11C15/00
摘要： A method and architecture for improving the usability and manufacturing yield of a microprocessor having a large on-chip n-way set associative cache. The architecture provides a method for working around defects in the portion of the die allocated to the data array of the cache. In particular, by adding a plurality of muxes to a way or ways in the data array of an associative cache having the shorter paths to the access control logic, each way in a bank can be selectively replaced or remapped to the ways with the shorter paths without adding any latency to the system. This selective remapping of separate ways in individual banks of the set associative cache provides a more efficient way to absorb defects and allows more defects to be absorbed in the data array of a set associative cache.
摘要翻译：一种用于提高具有大片上n路组相关高速缓存的微处理器的可用性和制造产量的方法和架构。该架构提供了一种用于处理分配给高速缓存的数据阵列的芯片部分中的缺陷的方法。特别地，通过向具有到访问控制逻辑的较短路径的关联高速缓存的数据阵列中的方式或方式添加多个多路复用器，可以选择性地将存储体中的每个路径替换或重新映射到具有较短路径的路径而不会对系统增加任何延迟。在集合关联高速缓存的各个组中的单独方式的这种选择性重新映射提供了一种更有效的方式来吸收缺陷，并允许在集合关联高速缓存的数据阵列中吸收更多的缺陷。

4. 发明授权

US06671822B1 Method and system for absorbing defects in high performance microprocessor with a large n-way set associative cache 有权
标题翻译：用大型n路组合关联缓存来吸收高性能微处理器缺陷的方法和系统
公开(公告)号：US06671822B1
公开(公告)日：2003-12-30
申请号：US09651948
申请日：2000-08-31
申请人： David H. Asher , Brian Lilly , Joel Grodstein , Patrick M. Fitzgerald
发明人： David H. Asher , Brian Lilly , Joel Grodstein , Patrick M. Fitzgerald
IPC分类号： G06F1100
CPC分类号： G11C29/76 , G06F12/0864 , G11C15/00
摘要： A method and architecture for improving the usability and manufacturing yield of a microprocessor having a large on-chip n-way set associative cache. The architecture provides a method for working around defects in the portion of the die allocated to the data array of the cache. In particular, by adding a plurality of muxes to a way or ways in the data array of an associative cache having the shorter paths to the access control logic, each way in a bank can be selectively replaced or remapped to the ways with the shorter paths without adding any latency to the system. This selective remapping of separate ways in individual banks of the set associative cache provides a more efficient way to absorb defects and allows more defects to be absorbed in the data array of a set associative cache.
摘要翻译：一种用于提高具有大片上n路组相关高速缓存的微处理器的可用性和制造产量的方法和架构。该架构提供了一种用于处理分配给高速缓存的数据阵列的芯片部分中的缺陷的方法。特别地，通过向具有到访问控制逻辑的较短路径的关联高速缓存的数据阵列中的方式或方式添加多个多路复用器，可以选择性地将存储体中的每个路径替换或重新映射到具有较短路径的路径而不会对系统增加任何延迟。在集合关联高速缓存的各个组中的单独方式的这种选择性重新映射提供了一种更有效的方式来吸收缺陷，并允许在集合关联高速缓存的数据阵列中吸收更多的缺陷。

5. 发明申请

US20100130334A1 OFFSET WEIGHT BARS 审中-公开
标题翻译：偏心杆
公开(公告)号：US20100130334A1
公开(公告)日：2010-05-27
申请号：US12565563
申请日：2009-09-23
申请人： Chris Roney , Brian Lilly
发明人： Chris Roney , Brian Lilly
IPC分类号： A63B21/06
CPC分类号： B25G1/00 , A63B21/0617 , A63B21/0724 , A63B21/4017 , A63B21/4049 , A63B23/14 , B25G3/00 , B62K21/12 , B62K21/125 , B62K21/16 , B62K21/18 , Y10T16/466 , Y10T16/476
摘要： An offset weight bar is provided which operates with the lifter's neuro-fascial connections to increase muscle activation and recruitment of muscle groups. The offset weight bar includes a grip portion that is shaped in accordance with the meuro-fascial connections in the lifter's hands and arms. The offset weight bar also offsets the weight of the bar from the lifter's palm to a point out along the lifter's unfolded fingers. The shape of the offset weight bar operates with the offset of the weight from the palm to increase the lifter's muscle activation and muscle group recruitment in accordance with the lifter's neuro-fascial physiology.
摘要翻译：提供偏移重量条，其与升降器的神经筋膜连接一起运动，以增加肌肉活动和肌肉群的招募。偏移重量杆包括根据提升器的手和臂中的红外 - 筋膜连接成形的抓握部分。偏移重量杆还可以将升降器的手掌的重量从升降机的展开的手指上移除。偏移重量条的形状与手掌的重量偏移一起运行，以根据升降器的神经筋膜生理增加升降器的肌肉活动和肌肉群体的招募。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式