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1. 发明申请

US20060125517A1 Techniques for optimizing design of a hard intellectual property block for data transmission 有权
标题翻译：用于优化硬件知识产权块设计数据传输的技术
公开(公告)号：US20060125517A1
公开(公告)日：2006-06-15
申请号：US11011543
申请日：2004-12-13
申请人： Darren van Wageningen , Curt Wortman , Boon-Jin Ang , Thow-Pang Chong , Dan Mansur , Ali Burney
发明人： Darren van Wageningen , Curt Wortman , Boon-Jin Ang , Thow-Pang Chong , Dan Mansur , Ali Burney
IPC分类号： H03K19/173 , G06F17/50 , H03K19/00 , G06F7/38
CPC分类号： H04L25/14
摘要： Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.
摘要翻译：提供了用于为可编程逻辑集成电路上的HIP块中的数据传输接口实现信道对准的技术。 HIP块信道对准逻辑可以使用减少数量的并行数据路径来运行，这消耗了相当少的逻辑资源。此外，HIP块通道对准逻辑电路可以以较高的HIP内核时钟速率串行处理，减少锁定延迟时间。提供了用于在可编程逻辑电路中实现发送数据的错误处理的技术。可编程逻辑电路可以配置为实现为任何应用定制的错误生成和错误监视功能。或者，可以将逻辑元件配置为对不需要错误处理的应用执行其他功能。通过将时钟信号与数据信号一起路由到每个电路块来减少集成电路上的数据和时钟信号之间的相位偏移。

2. 发明授权

US07434192B2 Techniques for optimizing design of a hard intellectual property block for data transmission 有权
标题翻译：用于优化硬件知识产权块设计数据传输的技术
公开(公告)号：US07434192B2
公开(公告)日：2008-10-07
申请号：US11011543
申请日：2004-12-13
申请人： Darren van Wageningen , Curt Wortman , Boon-Jin Ang , Thow-Pang Chong , Dan Mansur , Ali Burney
发明人： Darren van Wageningen , Curt Wortman , Boon-Jin Ang , Thow-Pang Chong , Dan Mansur , Ali Burney
IPC分类号： G06F17/50 , G06F3/00 , G06F13/14 , H03K19/0175 , H03K19/177 , H01L25/00 , H04L12/46 , H04J3/06
CPC分类号： H04L25/14
摘要： Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.
摘要翻译：提供了用于为可编程逻辑集成电路上的HIP块中的数据传输接口实现信道对准的技术。 HIP块信道对准逻辑可以使用减少数量的并行数据路径来运行，这消耗了相当少的逻辑资源。此外，HIP块通道对准逻辑电路可以以较高的HIP内核时钟速率串行处理，减少锁定延迟时间。提供了用于在可编程逻辑电路中实现发送数据的错误处理的技术。可编程逻辑电路可以配置为实现针对任何应用定制的错误生成和错误监视功能。或者，可以将逻辑元件配置为对不需要错误处理的应用执行其他功能。通过将时钟信号与数据信号一起路由到每个电路块来减少集成电路上的数据和时钟信号之间的相位偏移。

3. 发明授权

US07843216B2 Techniques for optimizing design of a hard intellectual property block for data transmission 有权
标题翻译：用于优化硬件知识产权块设计数据传输的技术
公开(公告)号：US07843216B2
公开(公告)日：2010-11-30
申请号：US12193532
申请日：2008-08-18
申请人： Darren van Wageningen , Curt Wortman , Boon-Jin Ang , Thow-Pang Chong , Dan Mansur , Ali Burney
发明人： Darren van Wageningen , Curt Wortman , Boon-Jin Ang , Thow-Pang Chong , Dan Mansur , Ali Burney
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H04L25/14
摘要： Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.
摘要翻译：提供了用于为可编程逻辑集成电路上的HIP块中的数据传输接口实现信道对准的技术。 HIP块信道对准逻辑可以使用减少数量的并行数据路径来运行，这消耗了相当少的逻辑资源。此外，HIP块通道对准逻辑电路可以以较高的HIP内核时钟速率串行处理，减少锁定延迟时间。提供了用于在可编程逻辑电路中实现发送数据的错误处理的技术。可编程逻辑电路可以配置为实现为任何应用定制的错误生成和错误监视功能。或者，可以将逻辑元件配置为对不需要错误处理的应用执行其他功能。通过将时钟信号与数据信号一起路由到每个电路块来减少集成电路上的数据和时钟信号之间的相位偏移。

4. 发明授权

US06981206B1 Method and apparatus for generating parity values 失效
标题翻译：用于产生奇偶校验值的方法和装置
公开(公告)号：US06981206B1
公开(公告)日：2005-12-27
申请号：US10315501
申请日：2002-12-10
申请人： Ali Burney , Nitin Prasad
发明人： Ali Burney , Nitin Prasad
IPC分类号： G06F11/00 , H04L1/00
CPC分类号： H04L1/0045
摘要： A circuit for computing parity values is disclosed. The circuit includes a control decode unit. The control decode unit determines whether words received during a cycle correspond to more than one packet of data. The circuit includes a first parity processor. The first parity processor computes first parity sum values from first words associated with a first packet of data received during the cycle. The circuit includes a second parity processor. The second parity processor is capable of computing second parity sum values from second words associated with a second packet of data received during the cycle when the control decode unit determines that the data words correspond to more than one packet of data.
摘要翻译：公开了一种用于计算奇偶校验值的电路。电路包括控制解码单元。控制解码单元确定在一周期期间接收到的字是否对应于多于一个数据包。电路包括第一奇偶校验处理器。第一奇偶校验处理器从与在该周期期间接收到的第一数据包相关联的第一字计算第一奇偶校验和值。该电路包括第二奇偶校验处理器。第二奇偶校验处理器能够在控制解码单元确定数据字对应于多于一个数据包的周期期间从与在该周期期间接收的第二数据包相关联的第二字计算第二奇偶校验和值。

5. 发明授权

US07715467B1 Programmable logic device integrated circuit with dynamic phase alignment capabilities 有权
标题翻译：具有动态相位对准功能的可编程逻辑器件集成电路
公开(公告)号：US07715467B1
公开(公告)日：2010-05-11
申请号：US11488434
申请日：2006-07-17
申请人： Ali Burney
发明人： Ali Burney
IPC分类号： H04B1/38
CPC分类号： H04J3/0685 , H03M9/00 , H04L7/0337
摘要： Adjustable transceiver circuitry is provided for programmable integrated circuits such as programmable logic device integrated circuits. The transceiver circuitry has a dynamic phase alignment circuit that can be used for aligning clock and data signals. The dynamic phase alignment circuit contains a bypassable synchronizer. Four modes of operation are supported by the transceiver circuitry including a normal source synchronous mode, a normal dynamic phase alignment mode, a soft clock data recovery mode, and a phase-locked-loop source synchronous mode. In normal source synchronous mode, the dynamic phase alignment circuit performs no phase alignment or clock rate matching. In normal dynamic phase alignment mode, the dynamic phase alignment circuit performs only phase alignment operations. In soft clock data recovery mode, programmable logic on the programmable integrated circuit is configured to perform rate matching and phase alignment. In phase-locked-loop source synchronous mode, phase alignment and board level deskewing operations are performed.
摘要翻译：为可编程集成电路（如可编程逻辑器件集成电路）提供可调收发器电路。收发器电路具有可用于对准时钟和数据信号的动态相位对准电路。动态相位对准电路包含可旁路同步器。包括正常源同步模式，正常动态相位对准模式，软时钟数据恢复模式和锁相环源同步模式的收发器电路支持四种操作模式。在正常的源同步模式下，动态相位对准电路不执行相位对准或时钟频率匹配。在正常动态相位对准模式中，动态相位对准电路仅执行相位对准操作。在软时钟数据恢复模式下，可编程集成电路上的可编程逻辑被配置为执行速率匹配和相位对准。在锁相环源同步模式下，执行相位对准和电路板级的偏移校正操作。

6. 发明授权

US07639054B1 Techniques for generating programmable delays 有权
标题翻译：用于生成可编程延迟的技术
公开(公告)号：US07639054B1
公开(公告)日：2009-12-29
申请号：US12015223
申请日：2008-01-16
申请人： Ali Burney
发明人： Ali Burney
IPC分类号： H03L7/00
CPC分类号： H03L7/0814
摘要： A circuit includes a sensing circuit, a control circuit, and a programmable delay circuit. The sensing circuit generates delay compensation signals that change in response to variations in at least one of a process and a temperature of the circuit. The control circuit generates dynamic control signals in response to the delay compensation signals. The programmable delay circuit is configurable to delay a signal transmitted through an external terminal of the circuit by a delay that is selected by the dynamic control signals.
摘要翻译：电路包括感测电路，控制电路和可编程延迟电路。感测电路产生响应于电路的过程和温度中的至少一个的变化而变化的延迟补偿信号。控制电路根据延迟补偿信号产生动态控制信号。可编程延迟电路可配置为通过由动态控制信号选择的延迟来延迟通过电路的外部端子发送的信号。

7. 发明授权

US07555667B1 Programmable logic device integrated circuit with dynamic phase alignment capabilities and shared phase-locked-loop circuitry 有权
标题翻译：具有动态相位对准功能和共享锁相环电路的可编程逻辑器件集成电路
公开(公告)号：US07555667B1
公开(公告)日：2009-06-30
申请号：US11488365
申请日：2006-07-17
申请人： Ali Burney , Yu Xu , Leon Zheng , Sanjay K. Charagulla
发明人： Ali Burney , Yu Xu , Leon Zheng , Sanjay K. Charagulla
IPC分类号： G06F1/04 , G06F1/06
CPC分类号： H03K19/17716 , G06F1/12
摘要： Adjustable transceiver circuitry is provided for programmable integrated circuits. The transceiver circuitry has a dynamic phase alignment circuit that can be used for aligning clock and data signals. The transceiver circuitry supports a phase-locked-loop source synchronous mode that can be used to receive data from transmitting integrated circuits that are clocked with a common clock. Each transmitting integrated circuit transmits a clock and associated data signals over a bus. The transceiver circuitry uses a master-slave architecture. A master dynamic phase alignment circuit in each transceiver receives the clock for that bus and selects a corresponding optimal clock phase to use in receiving input data for the bus from a multiphase clock. The master dynamic phase alignment circuit in each transceiver distributes the optimal clock phase to associated slave dynamic phase alignment circuits. Only a single phase-locked loop circuit is need to generate the multiphase clock.
摘要翻译：为可编程集成电路提供可调收发器电路。收发器电路具有可用于对准时钟和数据信号的动态相位对准电路。收发器电路支持锁相环源同步模式，该模式可用于从通过公共时钟计时的集成电路的发送接收数据。每个发送集成电路通过总线发送时钟和相关联的数据信号。收发器电路使用主从架构。每个收发器中的主动态相位对准电路接收该总线的时钟，并选择相应的最佳时钟相位，用于从多相时钟接收总线的输入数据。每个收发器中的主动态相位对准电路将最佳时钟相位分配给相关的从动态相位对准电路。只需要单个锁相环电路来产生多相时钟。

8. 发明授权

US07378868B2 Modular I/O bank architecture 有权
标题翻译：模块化I / O银行架构
公开(公告)号：US07378868B2
公开(公告)日：2008-05-27
申请号：US11558363
申请日：2006-11-09
申请人： Jeffrey Tyhach , Chiakang Sung , Khai Nguyen , Sanjay K. Charagulla , Ali Burney
发明人： Jeffrey Tyhach , Chiakang Sung , Khai Nguyen , Sanjay K. Charagulla , Ali Burney
IPC分类号： H03K19/173
CPC分类号： H03K19/17744
摘要： A programmable device I/O architecture allows for a variable number of I/O banks. Each I/O bank is of an I/O bank type. Each I/O bank type has a fixed number of I/O pins. I/O banks of the same I/O bank type are compatible within the same programmable device and between different types of programmable devices. The largest size I/O bank type and intermediate size I/O bank types are adapted to be a compatible supersets of every smaller I/O bank type. Support pins are regularly distributed between data pins in each I/O bank type. Multiple instances of the same or compatible I/O banks are arranged to be accessible from different sides of the programmable device. To facilitate circuit board layout, each I/O bank is arranged as a mirror and/or rotation of other I/O banks on the device.
摘要翻译：可编程器件I / O架构允许可变数量的I / O bank。每个I / O bank都是I / O bank类型。每个I / O bank类型都有固定数量的I / O引脚。相同I / O bank类型的I / O组在同一可编程器件内和不同类型的可编程器件之间兼容。最大尺寸的I / O库类型和中等大小的I / O库类型适合于每个更小的I / O bank类型的兼容超集。支持引脚定期分布在每个I / O bank类型的数据引脚之间。相同或兼容的I / O组的多个实例被布置为可从可编程设备的不同侧面访问。为了便于电路板布局，每个I / O组被布置为设备上的其他I / O组的镜像和/或旋转。

9. 发明申请

US20070240012A1 Memory interface circuitry with phase detection 失效
标题翻译：具有相位检测功能的存储器接口电路
公开(公告)号：US20070240012A1
公开(公告)日：2007-10-11
申请号：US11488199
申请日：2006-07-17
申请人： Ali Burney , Sanjay Charagulla
发明人： Ali Burney , Sanjay Charagulla
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： Integrated circuits such as programmable logic device integrated circuits with memory interface circuitry are provided. The memory interface circuitry measures the timing characteristics of an associated memory during a series of dummy read operations. A multiplexer and phase detector are used to measure phase shifts of memory group clock signals compared to a system clock signal. The memory interface circuitry uses these measurements to adjust a delay-locked-loop circuit. The delay-locked-loop circuit produces a capture clock that is used to read data from the memory.
摘要翻译：提供了诸如具有存储器接口电路的可编程逻辑器件集成电路的集成电路。存储器接口电路在一系列虚拟读取操作期间测量相关存储器的定时特性。与系统时钟信号相比，多路复用器和相位检测器用于测量存储器组时钟信号的相移。存储器接口电路使用这些测量来调整延迟锁定环路电路。延迟锁定环电路产生用于从存储器读取数据的捕获时钟。

10. 发明授权

US07664978B2 Memory interface circuitry with phase detection 失效
标题翻译：具有相位检测功能的存储器接口电路
公开(公告)号：US07664978B2
公开(公告)日：2010-02-16
申请号：US11488199
申请日：2006-07-17
申请人： Ali Burney , Sanjay K. Charagulla
发明人： Ali Burney , Sanjay K. Charagulla
IPC分类号： G06F1/00 , G06F1/04 , G06F1/12 , G06F13/00 , H04L7/00
CPC分类号： G06F1/10
摘要： Integrated circuits such as programmable logic device integrated circuits with memory interface circuitry are provided. The memory interface circuitry measures the timing characteristics of an associated memory during a series of dummy read operations. A multiplexer and phase detector are used to measure phase shifts of memory group clock signals compared to a system clock signal. The memory interface circuitry uses these measurements to adjust a delay-locked-loop circuit. The delay-locked-loop circuit produces a capture clock that is used to read data from the memory.
摘要翻译：提供了诸如具有存储器接口电路的可编程逻辑器件集成电路的集成电路。存储器接口电路在一系列虚拟读取操作期间测量相关存储器的定时特性。与系统时钟信号相比，多路复用器和相位检测器用于测量存储器组时钟信号的相移。存储器接口电路使用这些测量来调整延迟锁定环路电路。延迟锁定环电路产生用于从存储器读取数据的捕获时钟。

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