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1. 发明授权

US07555667B1 Programmable logic device integrated circuit with dynamic phase alignment capabilities and shared phase-locked-loop circuitry 有权
标题翻译：具有动态相位对准功能和共享锁相环电路的可编程逻辑器件集成电路
公开(公告)号：US07555667B1
公开(公告)日：2009-06-30
申请号：US11488365
申请日：2006-07-17
申请人： Ali Burney , Yu Xu , Leon Zheng , Sanjay K. Charagulla
发明人： Ali Burney , Yu Xu , Leon Zheng , Sanjay K. Charagulla
IPC分类号： G06F1/04 , G06F1/06
CPC分类号： H03K19/17716 , G06F1/12
摘要： Adjustable transceiver circuitry is provided for programmable integrated circuits. The transceiver circuitry has a dynamic phase alignment circuit that can be used for aligning clock and data signals. The transceiver circuitry supports a phase-locked-loop source synchronous mode that can be used to receive data from transmitting integrated circuits that are clocked with a common clock. Each transmitting integrated circuit transmits a clock and associated data signals over a bus. The transceiver circuitry uses a master-slave architecture. A master dynamic phase alignment circuit in each transceiver receives the clock for that bus and selects a corresponding optimal clock phase to use in receiving input data for the bus from a multiphase clock. The master dynamic phase alignment circuit in each transceiver distributes the optimal clock phase to associated slave dynamic phase alignment circuits. Only a single phase-locked loop circuit is need to generate the multiphase clock.
摘要翻译：为可编程集成电路提供可调收发器电路。收发器电路具有可用于对准时钟和数据信号的动态相位对准电路。收发器电路支持锁相环源同步模式，该模式可用于从通过公共时钟计时的集成电路的发送接收数据。每个发送集成电路通过总线发送时钟和相关联的数据信号。收发器电路使用主从架构。每个收发器中的主动态相位对准电路接收该总线的时钟，并选择相应的最佳时钟相位，用于从多相时钟接收总线的输入数据。每个收发器中的主动态相位对准电路将最佳时钟相位分配给相关的从动态相位对准电路。只需要单个锁相环电路来产生多相时钟。

2. 发明申请

US20070165478A1 MODULAR I/O BANK ARCHITECTURE 有权
标题翻译：模块化I / O银行架构
公开(公告)号：US20070165478A1
公开(公告)日：2007-07-19
申请号：US11558363
申请日：2006-11-09
申请人： Jeffrey Tyhach , Chiakang Sung , Khai Nguyen , Sanjay K. Charagulla , Ali Burney
发明人： Jeffrey Tyhach , Chiakang Sung , Khai Nguyen , Sanjay K. Charagulla , Ali Burney
IPC分类号： G11C8/00
CPC分类号： H03K19/17744
摘要： A programmable device I/O architecture allows for a variable number of I/O banks. Each I/O bank is of an I/O bank type. Each I/O bank type has a fixed number of I/O pins. I/O banks of the same I/O bank type are compatible within the same programmable device and between different types of programmable devices. The largest size I/O bank type and intermediate size I/O bank types are adapted to be a compatible supersets of every smaller I/O bank type. Support pins are regularly distributed between data pins in each I/O bank type. Multiple instances of the same or compatible I/O banks are arranged to be accessible from different sides of the programmable device. To facilitate circuit board layout, each I/O bank is arranged as a mirror and/or rotation of other I/O banks on the device.
摘要翻译：可编程器件I / O架构允许可变数量的I / O bank。每个I / O bank都是I / O bank类型。每个I / O bank类型都有固定数量的I / O引脚。相同I / O bank类型的I / O组在同一可编程器件内和不同类型的可编程器件之间兼容。最大尺寸的I / O库类型和中等大小的I / O库类型适合于每个更小的I / O bank类型的兼容超集。支持引脚定期分布在每个I / O bank类型的数据引脚之间。相同或兼容的I / O组的多个实例被布置为可从可编程设备的不同侧面访问。为了便于电路板布局，每个I / O组被布置为设备上的其他I / O组的镜像和/或旋转。

3. 发明授权

US07664978B2 Memory interface circuitry with phase detection 失效
标题翻译：具有相位检测功能的存储器接口电路
公开(公告)号：US07664978B2
公开(公告)日：2010-02-16
申请号：US11488199
申请日：2006-07-17
申请人： Ali Burney , Sanjay K. Charagulla
发明人： Ali Burney , Sanjay K. Charagulla
IPC分类号： G06F1/00 , G06F1/04 , G06F1/12 , G06F13/00 , H04L7/00
CPC分类号： G06F1/10
摘要： Integrated circuits such as programmable logic device integrated circuits with memory interface circuitry are provided. The memory interface circuitry measures the timing characteristics of an associated memory during a series of dummy read operations. A multiplexer and phase detector are used to measure phase shifts of memory group clock signals compared to a system clock signal. The memory interface circuitry uses these measurements to adjust a delay-locked-loop circuit. The delay-locked-loop circuit produces a capture clock that is used to read data from the memory.
摘要翻译：提供了诸如具有存储器接口电路的可编程逻辑器件集成电路的集成电路。存储器接口电路在一系列虚拟读取操作期间测量相关存储器的定时特性。与系统时钟信号相比，多路复用器和相位检测器用于测量存储器组时钟信号的相移。存储器接口电路使用这些测量来调整延迟锁定环路电路。延迟锁定环电路产生用于从存储器读取数据的捕获时钟。

4. 发明授权

US07378868B2 Modular I/O bank architecture 有权
标题翻译：模块化I / O银行架构
公开(公告)号：US07378868B2
公开(公告)日：2008-05-27
申请号：US11558363
申请日：2006-11-09
申请人： Jeffrey Tyhach , Chiakang Sung , Khai Nguyen , Sanjay K. Charagulla , Ali Burney
发明人： Jeffrey Tyhach , Chiakang Sung , Khai Nguyen , Sanjay K. Charagulla , Ali Burney
IPC分类号： H03K19/173
CPC分类号： H03K19/17744
摘要： A programmable device I/O architecture allows for a variable number of I/O banks. Each I/O bank is of an I/O bank type. Each I/O bank type has a fixed number of I/O pins. I/O banks of the same I/O bank type are compatible within the same programmable device and between different types of programmable devices. The largest size I/O bank type and intermediate size I/O bank types are adapted to be a compatible supersets of every smaller I/O bank type. Support pins are regularly distributed between data pins in each I/O bank type. Multiple instances of the same or compatible I/O banks are arranged to be accessible from different sides of the programmable device. To facilitate circuit board layout, each I/O bank is arranged as a mirror and/or rotation of other I/O banks on the device.
摘要翻译：可编程器件I / O架构允许可变数量的I / O bank。每个I / O bank都是I / O bank类型。每个I / O bank类型都有固定数量的I / O引脚。相同I / O bank类型的I / O组在同一可编程器件内和不同类型的可编程器件之间兼容。最大尺寸的I / O库类型和中等大小的I / O库类型适合于每个更小的I / O bank类型的兼容超集。支持引脚定期分布在每个I / O bank类型的数据引脚之间。相同或兼容的I / O组的多个实例被布置为可从可编程设备的不同侧面访问。为了便于电路板布局，每个I / O组被布置为设备上的其他I / O组的镜像和/或旋转。

5. 发明授权

US07417452B1 Techniques for providing adjustable on-chip termination impedance 有权
标题翻译：提供可调节片上终端阻抗的技术
公开(公告)号：US07417452B1
公开(公告)日：2008-08-26
申请号：US11462702
申请日：2006-08-05
申请人： Xiaobao Wang , Chiakang Sung , Khai Q. Nguyen , Sanjay K. Charagulla
发明人： Xiaobao Wang , Chiakang Sung , Khai Q. Nguyen , Sanjay K. Charagulla
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/0005 , H03K17/005 , H03K17/145 , H03K17/6871 , H03K17/6872 , H03K17/693
摘要： Techniques are provided for individually adjusting the on-chip termination impedance that is generated by input and output (IO) buffers in an input/output (IO) bank on an integrated circuit. The IO buffers in an IO bank can generate different on-chip termination impedances. And as a result, an IO bank can support more than one class of memory interfaces. An OCT calibration block generates a digital on-chip termination (OCT) calibration code. In some embodiments, circuitry in the IO banks can be configured to shift the OCT calibration code by one or more bits to adjust the series and/or parallel on-chip termination impedance in one or more IO buffers.
摘要翻译：提供了用于单独调整由集成电路中的输入/输出（IO）组中的输入和输出（IO）缓冲器产生的片上终端阻抗的技术。 IO bank中的IO缓冲区可以产生不同的片上终端阻抗。因此，IO bank可以支持多个类别的内存接口。 OCT校准块产生数字片上终端（OCT）校准码。在一些实施例中，IO组中的电路可被配置为将OCT校准码移位一个或多个位以调整一个或多个IO缓冲器中的串联和/或并行片上终端阻抗。

6. 发明授权

US07490209B1 Fully buffered DIMM system and method with hard-IP memory controller and soft-IP frequency controller 有权
标题翻译：全缓冲DIMM系统和方法与硬IP内存控制器和软IP频率控制器
公开(公告)号：US07490209B1
公开(公告)日：2009-02-10
申请号：US11300812
申请日：2005-12-14
申请人： Sanjay K. Charagulla
发明人： Sanjay K. Charagulla
IPC分类号： G06F13/00
CPC分类号： G06F13/4031 , G06F13/1668 , Y02D10/14 , Y02D10/151
摘要： A system and method for memory control. The system includes a hard-IP memory controller, a soft-IP frequency conversion system, and an interface system. The soft-IP frequency conversion system is coupled to the hard-IP memory controller, and is capable of being programmed to convert data signals between a first frequency and a second frequency.
摘要翻译：一种用于存储器控制的系统和方法。该系统包括硬IP存储器控制器，软IP变频系统和接口系统。软IP频率转换系统耦合到硬IP存储器控制器，并且能够被编程为在第一频率和第二频率之间转换数据信号。

7. 发明授权

US07825682B1 Techniques for providing adjustable on-chip termination impedance 有权
标题翻译：提供可调节片上终端阻抗的技术
公开(公告)号：US07825682B1
公开(公告)日：2010-11-02
申请号：US12147403
申请日：2008-06-26
申请人： Xiaobao Wang , Chiakang Sung , Khai Q. Nguyen , Sanjay K. Charagulla
发明人： Xiaobao Wang , Chiakang Sung , Khai Q. Nguyen , Sanjay K. Charagulla
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/0005 , H03K17/005 , H03K17/145 , H03K17/6871 , H03K17/6872 , H03K17/693
摘要： Techniques are provided for individually adjusting the on-chip termination impedance that is generated by input and output (IO) buffers in an input/output (IO) bank on an integrated circuit. The IO buffers in an IO bank can generate different on-chip termination impedances. And as a result, an IO bank can support more than one class of memory interfaces. An OCT calibration block generates a digital on-chip termination (OCT) calibration code. In some embodiments, circuitry in the IO banks can be configured to shift the OCT calibration code by one or more bits to adjust the series and/or parallel on-chip termination impedance in one or more IO buffers.
摘要翻译：提供了用于单独调整由集成电路中的输入/输出（IO）组中的输入和输出（IO）缓冲器产生的片上终端阻抗的技术。 IO bank中的IO缓冲区可以产生不同的片上终端阻抗。因此，IO bank可以支持多个类别的内存接口。 OCT校准块产生数字片上终端（OCT）校准码。在一些实施例中，IO组中的电路可被配置为将OCT校准码移位一个或多个位以调整一个或多个IO缓冲器中的串联和/或并行片上终端阻抗。

8. 发明授权

US07031222B1 DQS postamble filtering 失效
标题翻译： DQS后同步码过滤
公开(公告)号：US07031222B1
公开(公告)日：2006-04-18
申请号：US11046007
申请日：2005-01-28
申请人： Sanjay K. Charagulla , Chiakang Sung , Joseph Huang , Bonnie I. Wang , Yan Chong
发明人： Sanjay K. Charagulla , Chiakang Sung , Joseph Huang , Bonnie I. Wang , Yan Chong
IPC分类号： G11C8/00
CPC分类号： H03K5/135 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/22 , H03M9/00
摘要： Circuits, methods, and apparatus for filtering signals at a high-speed data interface. One exemplary embodiment is particularly configured to filter a clock signal at the end of a data burst received by a double-data rate memory interface. A clock input port is either connected or disconnected to an input cell. When a data burst is to be received, the clock input port is connected to the input cell. When the data burst concludes, the clock input port is disconnected from the input cell. In a specific embodiment, a signal is received indicating that a data burst is about to begin and the clock input port is connected to the input cell. The signal later changes state indicating that the last data bit is being received. When the last clock edge corresponding to the last data bit is received, the clock input port is disconnected from the input cell.
摘要翻译：用于在高速数据接口处过滤信号的电路，方法和装置。一个示例性实施例被特别地配置为在由双数据速率存储器接口接收的数据突发结束时对时钟信号进行滤波。时钟输入端口与输入单元连接或断开。当接收到数据脉冲串时，时钟输入端口连接到输入单元。当数据突发结束时，时钟输入端口与输入单元断开连接。在具体实施例中，接收到指示数据脉冲串即将开始并且时钟输入端口连接到输入单元的信号。该信号随后改变指示正在接收最后一个数据位的状态。当接收到与最后一个数据位相对应的最后一个时钟沿时，时钟输入端口与输入单元断开。

9. 发明授权

US07324405B1 DQS postamble filtering 有权
标题翻译： DQS后同步码过滤
公开(公告)号：US07324405B1
公开(公告)日：2008-01-29
申请号：US11368369
申请日：2006-03-03
申请人： Sanjay K. Charagulla , Chiakang Sung , Joseph Huang , Bonnie I. Wang , Yan Chong
发明人： Sanjay K. Charagulla , Chiakang Sung , Joseph Huang , Bonnie I. Wang , Yan Chong
IPC分类号： G11C8/00
CPC分类号： H03K5/135 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/22 , H03M9/00
摘要： Circuits, methods, and apparatus for filtering signals at a high-speed data interface. One exemplary embodiment is particularly configured to filter a clock signal at the end of a data burst received by a double-data rate memory interface. A clock input port is either connected or disconnected to an input cell. When a data burst is to be received, the clock input port is connected to the input cell. When the data burst concludes, the clock input port is disconnected from the input cell. In a specific embodiment, a signal is received indicating that a data burst is about to begin and the clock input port is connected to the input cell. The signal later changes state indicating that the last data bit is being received. When the last clock edge corresponding to the last data bit is received, the clock input port is disconnected from the input cell.
摘要翻译：用于在高速数据接口处过滤信号的电路，方法和装置。一个示例性实施例被特别地配置为在由双数据速率存储器接口接收的数据突发结束时对时钟信号进行滤波。时钟输入端口与输入单元连接或断开。当接收到数据脉冲串时，时钟输入端口连接到输入单元。当数据突发结束时，时钟输入端口与输入单元断开连接。在具体实施例中，接收到指示数据脉冲串即将开始并且时钟输入端口连接到输入单元的信号。该信号随后改变指示正在接收最后一个数据位的状态。当接收到与最后一个数据位相对应的最后一个时钟沿时，时钟输入端口与输入单元断开。

10. 发明授权

US07282973B1 Enhanced DLL phase output scheme 有权
标题翻译：增强的DLL相输出方案
公开(公告)号：US07282973B1
公开(公告)日：2007-10-16
申请号：US11297040
申请日：2005-12-07
申请人： Sanjay K. Charagulla , Ali H. Burney
发明人： Sanjay K. Charagulla , Ali H. Burney
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/0814 , H03L7/0818
摘要： A method and system using a delay-locked loop (DLL) to provide multiple phase locked outputs in discrete phase intervals is disclosed. In one embodiment, a reference clock signal is transmitted through a delay chain having a plurality of delay elements. The delay chain is capable of generating a plurality of output clock signals from the reference clock signal. Each of the output clock signals are delayed in discrete phase shift intervals with respect the delay elements. A first of the output clock signals and the reference clock signal are coupled to a first phase comparator capable of forming a first DLL with the delay chain. A second of the output clock signals and the reference clock signal are coupled to a second phase comparator capable of forming a second DLL with the delay chain. The output clock signal from the first DLL or the second DLL may be programmatically selected.
摘要翻译：公开了一种使用延迟锁定环（DLL）以离散相位间隔提供多个锁相输出的方法和系统。在一个实施例中，参考时钟信号通过具有多个延迟元件的延迟链传输。延迟链能够从参考时钟信号产生多个输出时钟信号。每个输出时钟信号相对于延迟元件以离散相移间隔被延迟。输出时钟信号和参考时钟信号中的第一个耦合到能够与延迟链形成第一DLL的第一相位比较器。输出时钟信号和参考时钟信号中的第二个耦合到能够与延迟链形成第二DLL的第二相位比较器。可以以编程方式选择来自第一DLL或第二DLL的输出时钟信号。

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