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1. 发明授权

US08156464B2 Method and system for automatic generation of processor datapaths 有权
标题翻译：用于自动生成处理器数据路径的方法和系统
公开(公告)号：US08156464B2
公开(公告)日：2012-04-10
申请号：US12111153
申请日：2008-04-28
申请人： Darin Stamenov Petkov , David William Goodwin , Dror Eliezer Maydan
发明人： Darin Stamenov Petkov , David William Goodwin , Dror Eliezer Maydan
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/68
摘要： Systems and method for automatically generating a set of shared processor datapaths from the description of the behavior of one or more ISA operations is presented. The operations may include, for example, the standard operations of a processor necessary to support an application language such as C or C++ on the ISA. Such operations, for example, may represent a configurable processor ISA. The operations may also include one or more extension operations defined by one or more designers. Thus, a description of the behaviors of the various standard and/or extension operations that compose the ISA of an instance of a standard or configurable processor is used to automatically generate a set of shared processor datapaths that implement the behavior of those operations. In addition, certain aspects may take one or more operations as well as one or more input semantics and either re-implement the input semantics automatically, or combine the input semantics with each other or with one or more other operations to automatically generate a new set of shared processor datapaths.
摘要翻译：提出了从一个或多个ISA操作的行为的描述中自动生成一组共享处理器数据路径的系统和方法。操作可以包括例如在ISA上支持诸如C或C ++的应用程序语言所必需的处理器的标准操作。例如，这样的操作可以表示可配置处理器ISA。这些操作还可以包括由一个或多个设计者定义的一个或多个扩展操作。因此，使用构成标准或可配置处理器的实例的ISA的各种标准和/或扩展操作的行为的描述来自动生成实现这些操作的行为的一组共享处理器数据路径。此外，某些方面可以采取一个或多个操作以及一个或多个输入语义，并且自动地重新实现输入语义，或者将输入语义彼此组合或者与一个或多个其他操作组合以自动生成新集合的共享处理器数据路径。

2. 发明授权

US09104827B2 Method and system for automatic generation of processor datapaths 有权
标题翻译：用于自动生成处理器数据路径的方法和系统
公开(公告)号：US09104827B2
公开(公告)日：2015-08-11
申请号：US13430629
申请日：2012-03-26
申请人： Darin Stamenov Petkov , David William Goodwin , Dror Eliezer Maydan
发明人： Darin Stamenov Petkov , David William Goodwin , Dror Eliezer Maydan
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/68
摘要： Systems and method for automatically generating a set of shared processor datapaths from the description of the behavior of one or more ISA operations is presented. The operations may include, for example, the standard operations of a processor necessary to support an application language such as C or C++ on the ISA. Such operations, for example, may represent a configurable processor ISA. The operations may also include one or more extension operations defined by one or more designers. Thus, a description of the behaviors of the various standard and/or extension operations that compose the ISA of an instance of a standard or configurable processor is used to automatically generate a set of shared processor datapaths that implement the behavior of those operations.
摘要翻译：提出了从一个或多个ISA操作的行为的描述中自动生成一组共享处理器数据路径的系统和方法。操作可以包括例如在ISA上支持诸如C或C ++的应用程序语言所必需的处理器的标准操作。例如，这样的操作可以表示可配置处理器ISA。这些操作还可以包括由一个或多个设计者定义的一个或多个扩展操作。因此，使用构成标准或可配置处理器的实例的ISA的各种标准和/或扩展操作的行为的描述来自动生成实现这些操作的行为的一组共享处理器数据路径。

3. 发明申请

US20120185808A1 Method and System for Automatic Generation of Processor Datapaths 有权
标题翻译：自动生成处理器数据路径的方法和系统
公开(公告)号：US20120185808A1
公开(公告)日：2012-07-19
申请号：US13430629
申请日：2012-03-26
申请人： Darin Stamenov Petkov , David William Goodwin , Dror Eliezer Maydan
发明人： Darin Stamenov Petkov , David William Goodwin , Dror Eliezer Maydan
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/68
摘要： Systems and method for automatically generating a set of shared processor datapaths from the description of the behavior of one or more ISA operations is presented. The operations may include, for example, the standard operations of a processor necessary to support an application language such as C or C++ on the ISA. Such operations, for example, may represent a configurable processor ISA. The operations may also include one or more extension operations defined by one or more designers. Thus, a description of the behaviors of the various standard and/or extension operations that compose the ISA of an instance of a standard or configurable processor is used to automatically generate a set of shared processor datapaths that implement the behavior of those operations.
摘要翻译：提出了从一个或多个ISA操作的行为的描述中自动生成一组共享处理器数据路径的系统和方法。操作可以包括例如在ISA上支持诸如C或C ++的应用程序语言所必需的处理器的标准操作。例如，这样的操作可以表示可配置处理器ISA。这些操作还可以包括由一个或多个设计者定义的一个或多个扩展操作。因此，使用构成标准或可配置处理器的实例的ISA的各种标准和/或扩展操作的行为的描述来自动生成实现这些操作的行为的一组共享处理器数据路径。

4. 发明授权

US06941548B2 Automatic instruction set architecture generation 有权
标题翻译：自动指令集架构生成
公开(公告)号：US06941548B2
公开(公告)日：2005-09-06
申请号：US09981291
申请日：2001-10-16
申请人： David William Goodwin , Dror Maydan , Ding-Kai Chen , Darin Stamenov Petkov , Steven Weng-Kiang Tjiang , Peng Tu , Christopher Rowen
发明人： David William Goodwin , Dror Maydan , Ding-Kai Chen , Darin Stamenov Petkov , Steven Weng-Kiang Tjiang , Peng Tu , Christopher Rowen
IPC分类号： G06F9/30 , G06F9/45 , G06F17/50
CPC分类号： G06F8/447 , G06F8/443
摘要： A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operations, fused operations, and specialized operations with the goal of increasing the performance of a set of applications while keeping hardware cost below a designer specified limit, or with the goal of minimizing hardware cost given a required level of performance.
摘要翻译：数字计算机系统自动创建可能利用VLIW指令，向量操作，融合操作和专门操作的指令集体系结构（ISA），目的是提高一组应用程序的性能，同时保持硬件成本低于设计者指定的限制，或者为了降低硬件成本，为达到所需的性能水平。

5. 发明授权

US07971197B2 Automatic instruction set architecture generation 有权
标题翻译：自动指令集架构生成
公开(公告)号：US07971197B2
公开(公告)日：2011-06-28
申请号：US11208239
申请日：2005-08-18
申请人： David William Goodwin , Dror Maydan , Ding-Kai Chen , Darin Stamenov Petkov , Steven Weng-Kiang Tjiang , Peng Tu , Christopher Rowen
发明人： David William Goodwin , Dror Maydan , Ding-Kai Chen , Darin Stamenov Petkov , Steven Weng-Kiang Tjiang , Peng Tu , Christopher Rowen
IPC分类号： G06F9/45 , G06F15/00 , G06F15/76
CPC分类号： G06F8/447 , G06F8/443
摘要： A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operations, fused operations, and specialized operations with the goal of increasing the performance of a set of applications while keeping hardware cost below a designer specified limit, or with the goal of minimizing hardware cost given a required level of performance.
摘要翻译：数字计算机系统自动创建可能利用VLIW指令，向量操作，融合操作和专门操作的指令集体系结构（ISA），目的是提高一组应用程序的性能，同时保持硬件成本低于设计者指定的限制，或者为了降低硬件成本，为达到所需的性能水平。

6. 发明授权

US07590964B1 Method and system for automatic generation of processor datapaths using instruction set architecture implementing means 有权
标题翻译：使用指令集架构实现手段自动生成处理器数据路径的方法和系统
公开(公告)号：US07590964B1
公开(公告)日：2009-09-15
申请号：US11313231
申请日：2005-12-19
申请人： Darin Stemenov Petkov , David William Goodwin , Dror Eliezer Maydan
发明人： Darin Stemenov Petkov , David William Goodwin , Dror Eliezer Maydan
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/68
摘要： Systems and method for automatically generating a set of shared processor datapaths from the description of the behavior of one or more ISA operations is presented. The operations may include, for example, the standard operations of a processor necessary to support an application language such as C or C++ on the ISA. Such operations, for example, may represent a configurable processor ISA. The operations may also include one or more extension operations defined by one or more designers. Thus, a description of the behaviors of the various standard and/or extension operations that compose the ISA of an instance of a standard or configurable processor is used to automatically generate a set of shared processor datapaths that implement the behavior of those operations. In addition, certain aspects may take one or more operations as well as one or more input semantics and either re-implement the input semantics automatically, or combine the input semantics with each other or with one or more other operations to automatically generate a new set of shared processor datapaths.
摘要翻译：提出了从一个或多个ISA操作的行为的描述中自动生成一组共享处理器数据路径的系统和方法。操作可以包括例如在ISA上支持诸如C或C ++的应用程序语言所必需的处理器的标准操作。例如，这样的操作可以表示可配置处理器ISA。这些操作还可以包括由一个或多个设计者定义的一个或多个扩展操作。因此，使用构成标准或可配置处理器的实例的ISA的各种标准和/或扩展操作的行为的描述来自动生成实现这些操作的行为的一组共享处理器数据路径。此外，某些方面可以采取一个或多个操作以及一个或多个输入语义，并且自动地重新实现输入语义，或者将输入语义彼此组合或者与一个或多个其他操作组合以自动生成新集合的共享处理器数据路径。

7. 发明授权

US06324689B1 Mechanism for re-writing an executable having mixed code and data 有权
标题翻译：重写具有混合代码和数据的可执行文件的机制
公开(公告)号：US06324689B1
公开(公告)日：2001-11-27
申请号：US09164255
申请日：1998-09-30
申请人： Paul Geoffrey Lowney , David William Goodwin , Robert Cohn
发明人： Paul Geoffrey Lowney , David William Goodwin , Robert Cohn
IPC分类号： G06F945
CPC分类号： G06F8/4442
摘要： A method for permitting software optimization tools, software instrumenting tools and other analysis tools to re-write executables having mixed instructions and data uses a data structure having an entry for each multi-bit word in an executable file. Each entry of the data structure includes a number of flags that are set to identify the type of the multi-bit word in the associated line of the executable file. The types include instruction, data and unclassified. Each entry also includes a flag that indicates that the multi-bit word should not be optimized and a flag indicating that the multi-bit word is a problem branch. The no-optimize and problem branch flags may be used to identify multi-bit words that may be either branch instructions or data, and to ensure that such multi-bit words are not affected by optimization or other rewriting of the executable. In addition, a problem fall through flag is provided to maintain program flow for possible fall through code segments.
摘要翻译：允许软件优化工具，软件测试工具和其他分析工具来重写具有混合指令和数据的可执行程序的方法使用具有可执行文件中的每个多位字的条目的数据结构。数据结构的每个条目包括多个标志，其被设置为标识可执行文件的相关行中的多位字的类型。类型包括指令，数据和未分类。每个条目还包括一个标志，表示多位字不应该被优化，一个标志指示多位字是一个问题分支。不优化和问题分支标志可以用于识别可以是分支指令或数据的多位字，并且确保这样的多位字不受可执行文件的优化或其他重写的影响。此外，提供了一个问题跌倒标志，以保持程序流程，以便可能落后于代码段。

8. 发明授权

US08161432B2 Automated processor generation system and method for designing a configurable processor 有权
标题翻译：用于设计可配置处理器的自动处理器生成系统和方法
公开(公告)号：US08161432B2
公开(公告)日：2012-04-17
申请号：US12248890
申请日：2008-10-09
申请人： Albert Ren-Rui Wang , Richard Ruddell , David William Goodwin , Earl A. Killian , Nupur Bhattacharyya , Marines Puig Medina , Walter David Lichtenstein , Pavlos Konas , Rangarajan Srinivasan , Christopher Mark Songer , Akilesh Parameswar , Dror E. Maydan , Ricardo E. Gonzalez
发明人： Albert Ren-Rui Wang , Richard Ruddell , David William Goodwin , Earl A. Killian , Nupur Bhattacharyya , Marines Puig Medina , Walter David Lichtenstein , Pavlos Konas , Rangarajan Srinivasan , Christopher Mark Songer , Akilesh Parameswar , Dror E. Maydan , Ricardo E. Gonzalez
IPC分类号： G06F17/50
CPC分类号： G06F9/30167 , G06F9/30145 , G06F17/5045
摘要： A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.
摘要翻译：用于生成处理器硬件的系统支持用于处理器指令集的显着扩展的语言，其中设计者仅指定新指令的语义，并且系统生成其他逻辑。扩展语言提供了添加处理器状态，包括寄存器文件和在该状态下操作的指令。该语言还提供了要添加到编译器中以表示添加的状态的新数据类型。它允许单独指定参考语义和指令实现，并使用它自动进行设计验证。另外，系统从语言规范生成格式化指令集文档。

9. 发明授权

US07437700B2 Automated processor generation system and method for designing a configurable processor 失效
标题翻译：用于设计可配置处理器的自动处理器生成系统和方法
公开(公告)号：US07437700B2
公开(公告)日：2008-10-14
申请号：US11281217
申请日：2005-11-16
申请人： Albert Ren-Rui Wang , Richard Ruddell , David William Goodwin , Earl A. Killian , Nupur Bhattacharyya , Marines Puig Medina , Walter David Lichtenstein , Pavlos Konas , Rangarajan Srinivasan , Christopher Mark Songer , Akilesh Parameswar , Dror E. Maydan , Ricardo E. Gonzalez
发明人： Albert Ren-Rui Wang , Richard Ruddell , David William Goodwin , Earl A. Killian , Nupur Bhattacharyya , Marines Puig Medina , Walter David Lichtenstein , Pavlos Konas , Rangarajan Srinivasan , Christopher Mark Songer , Akilesh Parameswar , Dror E. Maydan , Ricardo E. Gonzalez
IPC分类号： G06F17/50
CPC分类号： G06F9/30167 , G06F9/30145 , G06F17/5045
摘要： A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.
摘要翻译：用于生成处理器硬件的系统支持用于处理器指令集的显着扩展的语言，其中设计者仅指定新指令的语义，并且系统生成其他逻辑。扩展语言提供了添加处理器状态，包括寄存器文件和在该状态下操作的指令。该语言还提供了要添加到编译器中以表示添加的状态的新数据类型。它允许单独指定参考语义和指令实现，并使用它自动进行设计验证。另外，系统从语言规范生成格式化指令集文档。

10. 发明授权

US09582278B2 Automated processor generation system and method for designing a configurable processor 有权
标题翻译：用于设计可配置处理器的自动处理器生成系统和方法
公开(公告)号：US09582278B2
公开(公告)日：2017-02-28
申请号：US12248883
申请日：2008-10-09
申请人： Albert Ren-Rui Wang , Richard Ruddell , David William Goodwin , Earl A. Killian , Nupur Bhattacharyya , Marines Puig Medina , Walter David Lichtenstein , Pavlos Konas , Rangarajan Srinivasan , Christopher Mark Songer , Akilesh Parameswar , Dror E. Maydan , Ricardo E. Gonzalez
发明人： Albert Ren-Rui Wang , Richard Ruddell , David William Goodwin , Earl A. Killian , Nupur Bhattacharyya , Marines Puig Medina , Walter David Lichtenstein , Pavlos Konas , Rangarajan Srinivasan , Christopher Mark Songer , Akilesh Parameswar , Dror E. Maydan , Ricardo E. Gonzalez
IPC分类号： G06F17/50 , G06F9/30
CPC分类号： G06F9/30167 , G06F9/30145 , G06F17/5045
摘要： A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.
摘要翻译：用于生成处理器硬件的系统支持用于处理器指令集的显着扩展的语言，其中设计者仅指定新指令的语义，并且系统生成其他逻辑。扩展语言提供了添加处理器状态，包括寄存器文件和在该状态下操作的指令。该语言还提供了要添加到编译器中以表示添加的状态的新数据类型。它允许单独指定参考语义和指令实现，并使用它自动进行设计验证。另外，系统从语言规范生成格式化指令集文档。

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