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1. 发明授权

US08924898B2 System and method of designing instruction extensions to supplement an existing processor instruction set architecture 有权
标题翻译：设计指令扩展以补充现有处理器指令集架构的系统和方法
公开(公告)号：US08924898B2
公开(公告)日：2014-12-30
申请号：US12135502
申请日：2008-06-09
申请人： Earl A. Killian , Ricardo E. Gonzalez , Ashish B. Dixit , Monica Lam , Walter D. Lichtenstein , Christopher Rowen , John C. Ruttenberg , Robert P. Wilson , Albert Ren-Rui Wang , Dror Eliezer Maydan
发明人： Earl A. Killian , Ricardo E. Gonzalez , Ashish B. Dixit , Monica Lam , Walter D. Lichtenstein , Christopher Rowen , John C. Ruttenberg , Robert P. Wilson , Albert Ren-Rui Wang , Dror Eliezer Maydan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F8/20 , G06F8/41 , G06F8/53 , G06F2217/04 , G06F2217/68
摘要： An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.
摘要翻译：自动处理器设计工具使用标准化语言对定制的处理器指令集扩展进行描述，以开发目标指令集的可配置定义，实现指令集所需的电路的硬件描述语言描述，以及开发工具，如编译器，汇编器，调试器和模拟器，可用于开发处理器的应用程序并进行验证。处理器电路的实现可针对诸如面积，功耗，速度等的各种标准进行优化。一旦开发了处理器配置，就可以对其进行测试，并修改系统的输入以迭代地优化处理器实现。通过提供扩展和优化的限制域，该过程可以高度自动化，从而促进快速可靠的开发。

2. 发明申请

US20050278713A1 Automatic instruction set architecture generation 有权
公开(公告)号：US20050278713A1
公开(公告)日：2005-12-15
申请号：US11208239
申请日：2005-08-18
申请人： David Goodwin , Dror Maydan , Ding-Kai Chen , Darin Petkov , Steven Tjiang , Peng Tu , Christopher Rowen
发明人： David Goodwin , Dror Maydan , Ding-Kai Chen , Darin Petkov , Steven Tjiang , Peng Tu , Christopher Rowen
IPC分类号： G06F9/30 , G06F9/45 , G06F17/50
CPC分类号： G06F8/447 , G06F8/443
摘要： A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operations, fused operations, and specialized operations with the goal of increasing the performance of a set of applications while keeping hardware cost below a designer specified limit, or with the goal of minimizing hardware cost given a required level of performance.

3. 发明申请

US20050166038A1 High-performance hybrid processor with configurable execution units 有权
标题翻译：具有可配置执行单元的高性能混合处理器
公开(公告)号：US20050166038A1
公开(公告)日：2005-07-28
申请号：US10120849
申请日：2002-04-10
申请人： Albert Wang , Christopher Rowen , Bernard Rosenthal
发明人： Albert Wang , Christopher Rowen , Bernard Rosenthal
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F15/78 , G06F17/50 , H03K19/173 , G06F9/44
CPC分类号： G06F9/30145 , G06F9/30181 , G06F9/3824 , G06F9/3826 , G06F9/3867 , G06F9/3897 , G06F15/7867
摘要： A new general method for building hybrid processors achieves higher performance in applications by allowing more powerful, tightly-coupled instruction set extensions to be implemented in reconfigurable logic. New instructions set configurations can be discovered and designed by automatic and semi-automatic methods. Improved reconfigurable execution units support deep pipelining, addition of additional registers and register files, compound instructions with many source and destination registers and wide data paths. New interface methods allow lower latency, higher bandwidth connections between hybrid processors and other logic.
摘要翻译：用于构建混合处理器的新一般方法通过允许在可重配置逻辑中实现更强大，紧密耦合的指令集扩展来实现应用中的更高性能。可以通过自动和半自动方法发现和设计新的指令集配置。改进的可重配置执行单元支持深度流水线，添加附加寄存器和寄存器文件，具有许多源和目标寄存器的复合指令以及宽数据路径。新的接口方法允许混合处理器和其他逻辑之间的较低延迟，更高带宽连接。

4. 发明授权

US5325507A Translation lookaside buffer shutdown scheme 失效
标题翻译：翻译后备缓冲区关机方案
公开(公告)号：US5325507A
公开(公告)日：1994-06-28
申请号：US19541
申请日：1993-02-18
申请人： Danny L. Freitas , Craig C. Hansen , Christopher Rowen
发明人： Danny L. Freitas , Craig C. Hansen , Christopher Rowen
IPC分类号： G06F11/00 , G06F11/07 , G06F12/10 , G06F12/16
CPC分类号： G06F11/073 , G06F11/004 , G06F11/0751 , G06F12/1045 , G06F11/076
摘要： An apparatus for temporarily disabling a translation lookaside buffer in a computer system upon the occurrence of certain predefined system conditions. Such conditions may be of a first type which have been predetermined to indicate a greater risk that two or more virtual addresses stored in the TLB will simultaneously match the incoming virtual address, and/or of a second type in which access to the TLB is not needed. An example of the first type is a reference to an unmapped segment of memory. An example of the second type is the processing of a non-memory-access instruction. The apparatus may further include failsafe circuitry to shut down the TLB if at least a given number of matches occur at any time and for any reason, the given number being greater than 1. The apparatus prevents loss of data or damage to the chip where match comparisons are performed in parallel.
摘要翻译：一种用于在发生某些预定义的系统条件时暂时禁用计算机系统中的翻译后备缓冲器的装置。这样的条件可以是已经被预先确定的第一类型，以表示存储在TLB中的两个或更多个虚拟地址将同时匹配进入的虚拟地址，和/或其中对TLB的访问不是的第二类型的更大的风险需要的第一种类型的示例是对未映射的内存段的引用。第二种类型的示例是非存储器访问指令的处理。如果至少给定数量的匹配发生在任何时间，并且出于任何原因，给定数量大于1，则该装置还可以包括故障安全电路来关闭TLB。该装置防止丢失数据或损坏芯片，其中匹配并行执行比较。

5. 发明申请

US20080244471A1 SYSTEM AND METHOD OF CUSTOMIZING AN EXISTING PROCESSOR DESIGN HAVING AN EXISTING PROCESSOR INSTRUCTION SET ARCHITECTURE WITH INSTRUCTION EXTENSIONS 有权
标题翻译：现有处理器设计的系统和方法，具有指令扩展的现有处理器指令集架构
公开(公告)号：US20080244471A1
公开(公告)日：2008-10-02
申请号：US12135563
申请日：2008-06-09
申请人： Earl A. Killian , Ricardo E. Gonzalez , Ashish B. Dixit , Monica Lam , Walter D. Lichtenstein , Christopher Rowen , John C. Ruttenberg , Robert P. Wilson , Albert Ren-Rui Wang , Dror Eliezer Maydan
发明人： Earl A. Killian , Ricardo E. Gonzalez , Ashish B. Dixit , Monica Lam , Walter D. Lichtenstein , Christopher Rowen , John C. Ruttenberg , Robert P. Wilson , Albert Ren-Rui Wang , Dror Eliezer Maydan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F8/20 , G06F8/41 , G06F8/53 , G06F2217/04 , G06F2217/68
摘要： An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.
摘要翻译：自动处理器设计工具使用标准化语言对定制的处理器指令集扩展进行描述，以开发目标指令集的可配置定义，实现指令集所需的电路的硬件描述语言描述，以及开发工具，如编译器，汇编器，调试器和模拟器，可用于开发处理器的应用程序并进行验证。处理器电路的实现可针对诸如面积，功耗，速度等的各种标准进行优化。一旦开发了处理器配置，就可以对其进行测试，并修改系统的输入以迭代地优化处理器实现。通过提供扩展和优化的限制域，该过程可以高度自动化，从而促进快速可靠的开发。

6. 发明申请

US20070038584A1 Method for delivering free gift and advertising 审中-公开
标题翻译：提供免费礼品和广告的方法
公开(公告)号：US20070038584A1
公开(公告)日：2007-02-15
申请号：US11201808
申请日：2005-08-12
申请人： Christopher Faris , Eric McNiff , Christopher Rowen
发明人： Christopher Faris , Eric McNiff , Christopher Rowen
IPC分类号： G06Q30/00
CPC分类号： G06Q30/02 , G06Q99/00
摘要： Sanitary free gifts are delivered in a sealed container to children located at points of giving frequented by children. The container contains collateral material such as advertisements, coupons or free samples directed to appeal and educate the children, parents or guardians of the children. The delivery system is designed to provide the provider of the collateral material experiences an increase in amounts of business in providing goods and/or services to the children, patents and/or guardians of the child for the supplier of the gifts and a benefit to the suppliers of the collateral material.
摘要翻译：卫生免费礼品通过密封的容器运送到儿童经常出门的儿童身上。该容器包含诸如广告，优惠券或免费样品等辅助材料，用于上诉，并教育孩子的孩子，家长或监护人。交付系统的设计是为了提供担保材料的提供者，为儿童供应商的孩子，专利和/或监护人提供货物和/或服务的业务量增加，并为其提供益处供应商的辅助材料。

7. 发明授权

US06477683B1 Automated processor generation system for designing a configurable processor and method for the same 有权
标题翻译：用于设计可配置处理器的自动处理器生成系统及其方法
公开(公告)号：US06477683B1
公开(公告)日：2002-11-05
申请号：US09246047
申请日：1999-02-05
申请人： Earl A. Killian , Ricardo E. Gonzalez , Ashish B. Dixit , Monica Lam , Walter D. Lichtenstein , Christopher Rowen , John C. Ruttenberg , Robert P. Wilson , Albert Ren-Rui Wang , Dror Eliezer Maydan
发明人： Earl A. Killian , Ricardo E. Gonzalez , Ashish B. Dixit , Monica Lam , Walter D. Lichtenstein , Christopher Rowen , John C. Ruttenberg , Robert P. Wilson , Albert Ren-Rui Wang , Dror Eliezer Maydan
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F8/20 , G06F8/41 , G06F8/53 , G06F2217/04 , G06F2217/68
摘要： An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.
摘要翻译：自动处理器设计工具使用标准化语言对定制的处理器指令集扩展进行描述，以开发目标指令集的可配置定义，实现指令集所需的电路的硬件描述语言描述，以及开发工具，如编译器，汇编器，调试器和模拟器，可用于开发处理器的应用程序并进行验证。处理器电路的实现可针对诸如面积，功耗，速度等的各种标准进行优化。一旦开发了处理器配置，就可以对其进行测试，并修改系统的输入以迭代地优化处理器实现。通过提供扩展和优化的限制域，该过程可以高度自动化，从而促进快速可靠的开发。

8. 发明授权

US06282633B1 High data density RISC processor 有权
标题翻译：高数据密度RISC处理器
公开(公告)号：US06282633B1
公开(公告)日：2001-08-28
申请号：US09192395
申请日：1998-11-13
申请人： Earl A. Killian , Ricardo E. Gonzalez , Ashish B. Dixit , Monica Lam , Walter D. Lichtenstein , Christopher Rowen , John C. Ruttenberg , Robert P. Wilson
发明人： Earl A. Killian , Ricardo E. Gonzalez , Ashish B. Dixit , Monica Lam , Walter D. Lichtenstein , Christopher Rowen , John C. Ruttenberg , Robert P. Wilson
IPC分类号： G06K930
CPC分类号： G06F9/30178 , G06F9/30145 , G06F9/30167
摘要： A RISC processor implements an instruction set which, in addition to optimizing a relationship between the number of instructions required for execution of a program, clock period and average number of clocks per instruction, also is designed to optimize the equation S=IS * BI, where S is the size of program instructions in bits, IS is the static number of instructions required to represent the program (not the number required by an execution) and BI is the average number of bits per instruction. Compared to conventional RISC architectures, this processor lowers both BI and IS with minimal increases in clock period and average number of clocks per instruction. The processor provides good code density in a fixed-length high-performance encoding based on RISC principles, including a general register with load/store architecture. Further, the processor implements a simple variable-length encoding that maintains high performance.
摘要翻译： RISC处理器实现指令集，除了优化执行程序所需的指令数，时钟周期和每个指令的平均时钟数之间的关系外，还设计用于优化方程S = IS * BI，其中S是以位为单位的程序指令的大小，IS是表示程序所需的指令的静态数量（而不是执行所需的数目），BI是每个指令的平均位数。与传统的RISC体系结构相比，该处理器降低了BI和IS，时钟周期和每个指令的平均时钟周期几乎没有增加。处理器在基于RISC原理的固定长度高性能编码中提供了良好的代码密度，包括具有加载/存储架构的通用寄存器。此外，处理器实现了保持高性能的简单可变长度编码。

9. 发明授权

US08006204B2 Automated processor generation system for designing a configurable processor and method for the same 有权
标题翻译：用于设计可配置处理器的自动处理器生成系统及其方法
公开(公告)号：US08006204B2
公开(公告)日：2011-08-23
申请号：US11391773
申请日：2006-03-27
申请人： Earl A. Killian , Ricardo E. Gonzalez , Ashish B. Dixit , Monica Lam , Walter D. Lichtenstein , Christopher Rowen , John C. Ruttenberg , Robert P. Wilson , Albert Ren-Rui Wang , Dror Eliezer Maydan
发明人： Earl A. Killian , Ricardo E. Gonzalez , Ashish B. Dixit , Monica Lam , Walter D. Lichtenstein , Christopher Rowen , John C. Ruttenberg , Robert P. Wilson , Albert Ren-Rui Wang , Dror Eliezer Maydan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F8/20 , G06F8/41 , G06F8/53 , G06F2217/04 , G06F2217/68
摘要： An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.
摘要翻译：自动处理器设计工具使用标准化语言对定制的处理器指令集扩展进行描述，以开发目标指令集的可配置定义，实现指令集所需的电路的硬件描述语言描述，以及开发工具，如编译器，汇编器，调试器和模拟器，可用于开发处理器的应用程序并进行验证。处理器电路的实现可针对诸如面积，功耗，速度等的各种标准进行优化。一旦开发了处理器配置，就可以对其进行测试，并修改系统的输入以迭代地优化处理器实现。通过提供扩展和优化的限制域，该过程可以高度自动化，从而促进快速可靠的开发。

10. 发明授权

US07200735B2 High-performance hybrid processor with configurable execution units 有权
标题翻译：具有可配置执行单元的高性能混合处理器
公开(公告)号：US07200735B2
公开(公告)日：2007-04-03
申请号：US10120849
申请日：2002-04-10
申请人： Albert Wang , Christopher Rowen , Bernard Rosenthal
发明人： Albert Wang , Christopher Rowen , Bernard Rosenthal
IPC分类号： G06F15/80 , G06F9/44
CPC分类号： G06F9/30145 , G06F9/30181 , G06F9/3824 , G06F9/3826 , G06F9/3867 , G06F9/3897 , G06F15/7867
摘要： A new general method for building hybrid processors achieves higher performance in applications by allowing more powerful, tightly-coupled instruction set extensions to be implemented in reconfigurable logic. New instructions set configurations can be discovered and designed by automatic and semi-automatic methods. Improved reconfigurable execution units support deep pipelining, addition of additional registers and register files, compound instructions with many source and destination registers and wide data paths. New interface methods allow lower latency, higher bandwidth connections between hybrid processors and other logic.
摘要翻译：用于构建混合处理器的新一般方法通过允许在可重配置逻辑中实现更强大，紧密耦合的指令集扩展来实现应用中的更高性能。可以通过自动和半自动方法发现和设计新的指令集配置。改进的可重配置执行单元支持深度流水线，添加附加寄存器和寄存器文件，具有许多源和目标寄存器的复合指令以及宽数据路径。新的接口方法允许混合处理器和其他逻辑之间的较低延迟，更高带宽连接。

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