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1. 发明授权

US06586886B1 Gas distribution plate electrode for a plasma reactor 有权
标题翻译：用于等离子体反应器的气体分布板电极
公开(公告)号：US06586886B1
公开(公告)日：2003-07-01
申请号：US10027732
申请日：2001-12-19
申请人： Dan Katz , Douglas A. Buchberger, Jr. , Yan Ye , Robert B. Hagen , Xiaoye Zhao , Ananda H. Kumar , Kang-Lie Chiang , Hamid Noorbakhsh , Shiang-Bau Wang
发明人： Dan Katz , Douglas A. Buchberger, Jr. , Yan Ye , Robert B. Hagen , Xiaoye Zhao , Ananda H. Kumar , Kang-Lie Chiang , Hamid Noorbakhsh , Shiang-Bau Wang
IPC分类号： H01J724
CPC分类号： H01J37/3244
摘要： The invention is embodied in a plasma reactor for processing a semiconductor wafer, the reactor having a gas distribution plate including a front plate in the chamber and a back plate on an external side of the front plate, the gas distribution plate comprising a gas manifold adjacent the back plate, the back and front plates bonded together and forming an assembly. The assembly includes an array of holes through the front plate and communicating with the chamber, at least one gas flow-controlling orifice through the back plate and communicating between the manifold and at least one of the holes, the orifice having a diameter that determines gas flow rate to the at least one hole. In addition, an array of pucks is at least generally congruent with the array of holes and disposed within respective ones of the holes to define annular gas passages for gas flow through the front plate into the chamber, each of the annular gas passages being non-aligned with the orifice.
摘要翻译：本发明体现在用于处理半导体晶片的等离子体反应器中，该反应器具有气体分配板，该气体分配板包括在该腔室中的前板和在前板的外侧上的后板，该气体分配板包括邻近的气体歧管背板，后板和前板结合在一起并形成组件。组件包括穿过前板并与腔室连通的孔阵列，至少一个通过后板的气体流量控制孔，并在歧管和至少一个孔之间连通，孔口具有确定气体的直径至少一个孔的流速。此外，一组圆盘至少大体上与孔阵列一致，并且设置在孔的相应孔内，以限定用于气体流过前板进入腔室的环形气体通道，每个环形气体通道是非限制性的，与孔对齐。

2. 发明授权

US06677712B2 Gas distribution plate electrode for a plasma receptor 有权
标题翻译：用于等离子体受体的气体分布板电极
公开(公告)号：US06677712B2
公开(公告)日：2004-01-13
申请号：US10442386
申请日：2003-05-20
申请人： Dan Katz , Douglas A. Buchberger, Jr. , Yan Ye , Robert B. Hagen , Xiaoye Zhao , Ananda H. Kumar , Kang-Lie Chiang , Hamid Noorbakhsh , Shiang-Bau Wang
发明人： Dan Katz , Douglas A. Buchberger, Jr. , Yan Ye , Robert B. Hagen , Xiaoye Zhao , Ananda H. Kumar , Kang-Lie Chiang , Hamid Noorbakhsh , Shiang-Bau Wang
IPC分类号： H01J724
CPC分类号： H01J37/3244
摘要： The invention is embodied in a plasma reactor for processing a semiconductor wafer, the reactor having a gas distribution plate including a front plate in the chamber and a back plate on an external side of the front plate, the gas distribution plate comprising a gas manifold adjacent the back plate, the back and front plates bonded together and forming an assembly. The assembly includes an array of holes through the front plate and communicating with the chamber, at least one gas flow-controlling orifice through the back plate and communicating between the manifold and at least one of the holes, the orifice having a diameter that determines gas flow rate to the at least one hole. In addition, an array of pucks is at least generally congruent with the array of holes and disposed within respective ones of the holes to define annular gas passages for gas flow through the front plate into the chamber, each of the annular gas passages being non-aligned with the orifice.
摘要翻译：本发明体现在用于处理半导体晶片的等离子体反应器中，该反应器具有气体分配板，该气体分配板包括在该腔室中的前板和在前板的外侧上的后板，该气体分配板包括邻近的气体歧管背板，后板和前板结合在一起并形成组件。组件包括穿过前板并与腔室连通的孔阵列，至少一个通过后板的气体流量控制孔，并在歧管和至少一个孔之间连通，孔口具有确定气体的直径至少一个孔的流速。此外，一组圆盘至少大体上与孔阵列一致，并且设置在孔的相应孔内，以限定用于气体流过前板进入腔室的环形气体通道，每个环形气体通道是非限制性的，与孔对齐。

3. 发明授权

US06667577B2 Plasma reactor with spoke antenna having a VHF mode with the spokes in phase 失效
标题翻译：具有辐射天线的等离子体反应器具有VHF模式，辐条处于同相状态
公开(公告)号：US06667577B2
公开(公告)日：2003-12-23
申请号：US10025408
申请日：2001-12-18
申请人： Steven Shannon , Daniel Hoffman , Chunshi Cui , Yan Ye , Gerardo Delgadino , Douglas A. Buchberger, Jr. , Shiang-Bau Wang , Robert B. Hagen , Matthew L Miller , Stephen Thai
发明人： Steven Shannon , Daniel Hoffman , Chunshi Cui , Yan Ye , Gerardo Delgadino , Douglas A. Buchberger, Jr. , Shiang-Bau Wang , Robert B. Hagen , Matthew L Miller , Stephen Thai
IPC分类号： H01J724
CPC分类号： H01J37/321
摘要： An RF power applicator of the reactor includes inner and outer conductive radial spokes. The set of inner conductive spokes extends radially outwardly from and is electrically connected to the conductive post toward the conductive side wall. The set of outer conductive spokes extends radially inwardly toward the conductive post from and is electrically connected to the conductive side wall. In this way, the inner and outer sets of conductive spokes are electrically connected together, the combination of the inner and outer set of spokes with the conductive enclosure having a fundamental resonant frequency inversely proportional to the height of the conductive enclosure and the lengths of the inner and outer set of conductive spokes. An RF source power generator is coupled across the RF power applicator and has an RF frequency corresponding to the fundamental resonant frequency.
摘要翻译：反应器的RF功率施加器包括内部和外部导电的径向辐条。一组内导电轮辐径向向外延伸并且与导电柱电连接到导电侧壁。一组外导电轮辐径向向内延伸到导电柱，并与导电侧壁电连接。以这种方式，导电辐条的内部和外部组电连接在一起，内部和外部组的辐条与导电外壳的组合具有与导电外壳的高度成反比的基本谐振频率和内外套导电辐条。 RF源功率发生器耦合在RF功率施加器上并且具有对应于基本谐振频率的RF频率。

4. 发明授权

US06652712B2 Inductive antenna for a plasma reactor producing reduced fluorine dissociation 失效
标题翻译：用于等离子体反应器的感应天线，其产生降低的氟解离
公开(公告)号：US06652712B2
公开(公告)日：2003-11-25
申请号：US10028646
申请日：2001-12-19
申请人： Shiang-Bau Wang , Daniel J. Hoffman , Chunshi Cui , Yan Ye , Gerardo Delgadino , David McParland , Matthew L. Miller , Douglas A. Buchberger, Jr. , Steven C. Shannon
发明人： Shiang-Bau Wang , Daniel J. Hoffman , Chunshi Cui , Yan Ye , Gerardo Delgadino , David McParland , Matthew L. Miller , Douglas A. Buchberger, Jr. , Steven C. Shannon
IPC分类号： C23C1600
CPC分类号： H01J37/321
摘要： An inductive antenna of a plasma reactor for processing a semiconductor wafer is connected to a radio frequency (RF) power source, and consists of a conductor arranged in successive loops that wind in opposing directions, adjacent pairs of the successive loops having facing portions in which current flow is parallel, the facing portions being sufficiently close to at least nearly share a common current path, whereby to form transitions across the facing portions between opposing magnetic polarizations.
摘要翻译：用于处理半导体晶片的等离子体反应器的感应天线连接到射频（RF）电源，并且由布置在相反方向上的连续回路中的导体组成，相邻的一对连续的回路具有面对部分电流流动是平行的，面对部分足够接近至少几乎共享公共电流路径，从而在相对的磁极化之间跨越相对部分形成过渡。

5. 发明授权

US09945048B2 Semiconductor structure and method 有权
公开(公告)号：US09945048B2
公开(公告)日：2018-04-17
申请号：US13525041
申请日：2012-06-15
申请人： Sen-Hong Syue , Pu-Fang Chen , Shiang-Bau Wang
发明人： Sen-Hong Syue , Pu-Fang Chen , Shiang-Bau Wang
IPC分类号： C30B15/04 , H01L21/02 , C30B15/20 , C30B31/02 , C30B31/04 , H01L21/311 , C30B15/22 , H01L29/36 , H01L21/762 , C30B31/16 , H01L21/3105 , C30B29/06 , H01L21/322 , C30B15/00 , C30B33/00 , H01L29/78
CPC分类号： C30B15/04 , C30B15/00 , C30B15/203 , C30B15/206 , C30B15/22 , C30B29/06 , C30B31/02 , C30B31/04 , C30B31/165 , C30B33/00 , H01L21/0201 , H01L21/31053 , H01L21/311 , H01L21/3225 , H01L21/76224 , H01L29/365 , H01L29/78
摘要： A system and method for providing support to semiconductor wafer is provided. An embodiment comprises introducing a vacancy enhancing material during the formation of a semiconductor ingot prior to the semiconductor wafer being separated from the semiconductor ingot. The vacancy enhancing material forms vacancies at a high density within the semiconductor ingot, and the vacancies form bulk micro defects within the semiconductor wafer during high temperature processes such as annealing. These bulk micro defects help to provide support and strengthen the semiconductor wafer during subsequent processing and helps to reduce or eliminate a fingerprint overlay that may otherwise occur.

6. 发明授权

US08604562B2 Post CMP planarization by cluster ion beam etch 有权
标题翻译：通过簇离子束蚀刻后CMP平坦化
公开(公告)号：US08604562B2
公开(公告)日：2013-12-10
申请号：US13466569
申请日：2012-05-08
申请人： Shiang-Bau Wang
发明人： Shiang-Bau Wang
IPC分类号： H01L29/00
CPC分类号： H01L21/31055 , H01L21/3065 , H01L21/31116 , H01L21/32115 , H01L21/32136 , H01L21/76229 , H01L21/76819 , H01L22/12 , H01L22/20
摘要： The embodiments of mechanisms described enables improved planarity of substrates, which is crucial for patterning and device yield improvement. Chemical-mechanical polishing (CMP) is used to remove film to planarize the substrate before the final thickness is reached or before all removal film is polished. The substrate is then measured for its topography and film thickness. The topography and thickness data are used by the gas cluster ion beam (GCIB) etch tool to determine how much film to remove on a particular location. GCIB etch enables removal of final layer to meet the requirements of substrate uniformity and thickness target. The mechanisms enable improved planarity to meet the requirement of advanced processing technologies.
摘要翻译：所描述的机构的实施例使得能够改善衬底的平面性，这对于图案化和器件产量提高至关重要。在达到最终厚度之前或在所有去除膜被抛光之前，使用化学机械抛光（CMP）去除膜以使基板平坦化。然后测量衬底的形貌和膜厚度。气体簇离子束（GCIB）蚀刻工具使用地形和厚度数据来确定在特定位置上要移除多少胶片。 GCIB蚀刻可以去除最终层，以满足基板均匀性和厚度目标的要求。这些机制可以提高平面性，以满足先进的处理技术的要求。

7. 发明授权

US08361338B2 Hard mask removal method 有权
标题翻译：硬掩模去除方法
公开(公告)号：US08361338B2
公开(公告)日：2013-01-29
申请号：US12704032
申请日：2010-02-11
申请人： Shiang-Bau Wang
发明人： Shiang-Bau Wang
IPC分类号： C23F1/00 , B44C1/22
CPC分类号： H01L21/02107 , H01L21/02071 , H01L21/02697 , H01L21/31055 , H01L21/31111 , H01L21/31116 , H01L21/32139
摘要： The embodiments of methods described in this disclosure for removing a hard mask layer(s) over a polysilicon layer of a gate stack after the gate stack is etched allows the complete removal of the hard mask layer without the assistance of photolithography. A dielectric material is deposited over the substrate with the gate stacks. The topography of the substrate is removed by chemical mechanical polishing first. Afterwards, an etching gas (or vapor) is used to etch a portion of the remaining dielectric layer and the hard mask layer. The etching gas forms an etch byproduct that deposits on the substrate surface and can be subsequently removed by heating. The etching and heating to remove etch byproduct are repeated until the hard mask layer is completed removed. Afterwards, the remaining dielectric layer is removed by wet etch. The methods described are simpler and cheaper to use than conventional methods for hard mask removal.
摘要翻译：在本公开中描述的用于在蚀刻栅极叠层之后去除栅极堆叠的多晶硅层上的硬掩模层的方法的实施例允许在没有光刻的帮助下完全去除硬掩模层。电介质材料沉积在衬底上，栅极叠层。首先通过化学机械抛光去除衬底的形貌。之后，使用蚀刻气体（或蒸汽）来蚀刻剩余介电层和硬掩模层的一部分。蚀刻气体形成沉积在衬底表面上的蚀刻副产物，随后可通过加热除去。重复蚀刻和加热去除蚀刻副产物，直到硬掩模层完成去除。之后，通过湿蚀刻除去剩余的介电层。与常规的硬掩模去除方法相比，所描述的方法更简单并且更便宜。

8. 发明申请

US20120205746A1 END-TO-END GAP FILL USING DIELECTRIC FILM 有权
标题翻译：使用电介质膜的端到端胶带填充
公开(公告)号：US20120205746A1
公开(公告)日：2012-08-16
申请号：US13025414
申请日：2011-02-11
申请人： Shiang-Bau Wang
发明人： Shiang-Bau Wang
IPC分类号： H01L27/088 , H01L21/28
CPC分类号： H01L27/088 , H01L21/28 , H01L21/76837
摘要： A method for fabricating a semiconductor device includes forming a plurality of gate structures on a semiconductor substrate. The plurality of gate structures are arranged in a plurality of lines, wherein an end-to-end spacing between the lines is smaller than a line-to-line spacing between the lines. The method further includes forming an etch stop layer over the gate structures, forming an interlayer dielectric over the gate structures, and forming a dielectric film over the gate structures before the interlayer dielectric is formed. The dielectric film merges in end-to-end gaps formed in the end-to-end spacing between the gate structures.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底上形成多个栅极结构。多个栅极结构被布置成多条线，其中线之间的端对端间隔小于线之间的线间间隔。该方法还包括在栅极结构上形成蚀刻停止层，在栅极结构之上形成层间电介质，以及在形成层间电介质之前在栅极结构上形成电介质膜。电介质膜在形成在门结构之间的端到端间隔中的端到端间隙中融合。

9. 发明授权

US08193094B2 Post CMP planarization by cluster ION beam etch 有权
标题翻译：通过簇ION光束蚀刻后CMP平坦化
公开(公告)号：US08193094B2
公开(公告)日：2012-06-05
申请号：US12819743
申请日：2010-06-21
申请人： Shiang-Bau Wang
发明人： Shiang-Bau Wang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/31055 , H01L21/3065 , H01L21/31116 , H01L21/32115 , H01L21/32136 , H01L21/76229 , H01L21/76819 , H01L22/12 , H01L22/20
摘要： The embodiments of mechanisms described enables improved planarity of substrates, which is crucial for patterning and device yield improvement. Chemical-mechanical polishing (CMP) is used to remove film to planarize the substrate before the final thickness is reached or before all removal film is polished. The substrate is then measured for its topography and film thickness. The topography and thickness data are used by the gas cluster ion beam (GCIB) etch tool to determine how much film to remove on a particular location. GCIB etch enables removal of final layer to meet the requirements of substrate uniformity and thickness target. The mechanisms enable improved planarity to meet the requirement of advanced processing technologies.
摘要翻译：所描述的机构的实施例使得能够改善衬底的平面性，这对于图案化和器件产量提高至关重要。在达到最终厚度之前或在所有去除膜被抛光之前，使用化学机械抛光（CMP）去除膜以使基板平坦化。然后测量衬底的形貌和膜厚度。气体簇离子束（GCIB）蚀刻工具使用地形和厚度数据来确定在特定位置上要移除多少胶片。 GCIB蚀刻可以去除最终层，以满足基板均匀性和厚度目标的要求。这些机制可以提高平面性，以满足先进的处理技术的要求。

10. 发明授权

US07947551B1 Method of forming a shallow trench isolation structure 有权
标题翻译：形成浅沟槽隔离结构的方法
公开(公告)号：US07947551B1
公开(公告)日：2011-05-24
申请号：US12892331
申请日：2010-09-28
申请人： Sen-Hong Syue , Bor Chiuan Hsieh , Shiang-Bau Wang
发明人： Sen-Hong Syue , Bor Chiuan Hsieh , Shiang-Bau Wang
IPC分类号： H01L21/00
CPC分类号： H01L21/02337 , H01L21/02274 , H01L21/02282 , H01L21/02356 , H01L21/76224
摘要： An embodiment of the disclosure includes a method of forming a shallow trench isolation structure. A substrate is provided. The substrate includes a top surface. A trench is formed to extend from the top surface into the substrate. The trench has sidewalls and a bottom surface. A silicon liner layer is formed on the sidewalls and the bottom surface. A flowable dielectric material is filled in the trench. An anneal process is performed to densify the flowable dielectric material and convert the silicon liner layer into a silicon oxide layer simultaneously.
摘要翻译：本公开的实施例包括形成浅沟槽隔离结构的方法。提供基板。衬底包括顶表面。形成沟槽以从顶表面延伸到衬底中。沟槽具有侧壁和底面。在侧壁和底表面上形成硅衬层。可流动介电材料填充在沟槽中。进行退火处理以使可流动电介质材料致密化并同时将硅衬层转化为氧化硅层。

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