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1. 发明授权

US07006110B2 Determining a coverage mask for a pixel 有权
标题翻译：确定像素的覆盖掩码
公开(公告)号：US07006110B2
公开(公告)日：2006-02-28
申请号：US10414462
申请日：2003-04-15
申请人： Dan Crisu , Sorin Cotofana , Stamatis Vassiliadis , Petri Liuha
发明人： Dan Crisu , Sorin Cotofana , Stamatis Vassiliadis , Petri Liuha
IPC分类号： G09G5/00
CPC分类号： G06T11/40 , G06T11/203 , G06T2200/12
摘要： The invention relates to a method, a device, a system and a software program product for determining for a pixel a coverage mask reflecting an orientation and possibly a distance from the pixel center of an original edge vector. The pixel is to be employed for displaying at least a part of a geometric primitive on a display, and the original edge vector represents an oriented edge of the geometric primitive. The method comprises as a first step determining one of four quadrants of a Cartesian coordinate system to which the original edge vector belongs due to its orientation. The original edge vector is then transposed into a predetermined one of the four quadrants. Next, a stored coverage mask is fetched, which is associated at least indirectly to the transposed edge vector. Finally, the fetched coverage mask is transformed to the quadrant to which the original edge vector belongs.
摘要翻译：本发明涉及一种方法，装置，系统和软件程序产品，用于为像素确定反映来自原始边缘向量的像素中心的取向和可能距离的覆盖掩模。该像素用于在显示器上显示几何图元的至少一部分，并且原始边缘矢量表示几何图元的定向边缘。该方法包括作为第一步骤，由于其定向，确定原始边缘矢量所属的笛卡尔坐标系的四个象限之一。然后将原始边缘向量转置到四个象限中的预定的一个。接下来，获取存储的覆盖掩码，其至少间接地与转置的边缘向量相关联。最后，将获取的覆盖掩码转换为原始边缘向量所属的象限。

2. 发明授权

US06980138B2 Method and a system for variable-length decoding, and a device for the localization of codewords 有权
标题翻译：用于可变长度解码的方法和系统，以及用于定位码字的装置
公开(公告)号：US06980138B2
公开(公告)日：2005-12-27
申请号：US10465033
申请日：2003-06-18
申请人： Stamatis Vassiliadis , Jari Nikara , Jarmo Takala , Petri Liuha
发明人： Stamatis Vassiliadis , Jari Nikara , Jarmo Takala , Petri Liuha
IPC分类号： H03M7/42 , H03M7/40
CPC分类号： H03M7/42
摘要： A method and associated decoder, system, device and storage means for decoding codewords of variable length from a bit stream, in which minimum and maximum lengths are defined for the codewords, wherein the bit stream is processed in parts, each part being subjected to a search for codewords, and where found codewords are decoded. At least partly overlapping fields are extracted from the bit stream part in such a way that the starting point of at least two fields is a possible starting point of a codeword in that part. In at least one field, the end of the codeword is searched, and the data related to the codeword is determined on the basis of the end point of the codeword. Data relating to at least one codeword is used to determine the occurrence of the codeword intended to be decoded in a field, and the found codeword is decoded.
摘要翻译：一种用于从比特流解码可变长度的码字的方法和相关联的解码器，系统，设备和存储装置，其中为码字定义最小和最大长度，其中，位部分被部分地处理，每个部分经受搜索码字，以及在哪里找到码字被解码。从比特流部分提取至少部分重叠的字段，使得至少两个字段的起始点是该部分中码字的可能的起始点。在至少一个字段中，搜索码字的结尾，并且基于码字的终点确定与码字有关的数据。与至少一个码字相关的数据用于确定在字段中要解码的码字的出现，并且找到的码字被解码。

3. 发明授权

US5784632A Parallel diagonal-fold array processor 失效
标题翻译：平行对角线阵列处理器
公开(公告)号：US5784632A
公开(公告)日：1998-07-21
申请号：US415775
申请日：1995-03-30
申请人： Gerald George Pechanek , Stamatis Vassiliadis , Jose Guadalupe Delgado-Frias
发明人： Gerald George Pechanek , Stamatis Vassiliadis , Jose Guadalupe Delgado-Frias
IPC分类号： G06F15/16 , G06F15/173 , G06F15/18 , G06F15/80 , G06N3/04 , G06F15/00
CPC分类号： G06F15/8023
摘要： A massively parallel processor apparatus having an instruction set architecture for each of the N.sup.2 the PEs of the structure. The apparatus which we prefer will have a PE structure consisting of PEs that contain instruction and data storage units, receive instructions and data, and execute instructions. The N.sup.2 structure should contain "N" communicating ALU trees, "N" programmable root tree processor units, and an arrangement for communicating both instructions, data, and the root tree processor outputs back to the input processing elements by means of the communicating ALU trees. The apparatus can be structured as a bit-serial or word parallel system. The preferred structure contains N.sup.2 PEs, identified as PE.sub.column,row, in a N root tree processor system, placed in the form of a N by N processor array that has been folded along the diagonal and made up of diagonal cells and general cells. The Diagonal-Cells are comprised of a single processing element identified as PE.sub.i,i of the folded N by N processor array and the General-Cells are comprised of two PEs merged together, identified as PE.sub.i,j and PE.sub.j,i of the folded N by N processor array. Matrix processing algorithms are discussed followed by a presentation of the Diagonal-Fold Tree Array Processor architecture. The Massively Parallel Diagonal-Fold Tree Array Processor supports completely connected root tree processors through the use of the array of PEs that are interconnected by folded communication ALU trees.
摘要翻译：一种大规模并行处理器装置，具有用于结构的每个N 2的指令集架构。我们喜欢的设备将具有由包含指令和数据存储单元，接收指令和数据以及执行指令的PE组成的PE结构。 N2结构应包含“N”个通信ALU树，“N”个可编程根树处理器单元，以及用于通过通信ALU树将指令，数据和根树处理器输出两者传送回输入处理单元的布置。该装置可以被构造为比特串行或字并行系统。优选的结构包含N型PE，在N根树处理器系统中被标识为PE列，行，以N×N处理器阵列的形式放置，该处理器阵列沿对角线折叠并由对角线单元和通用单元构成。对角线单元由标识为由N处理器阵列折叠的N i的单个处理元件组成，并且通用单元由合并在一起的两个PE组成，标识为折叠N的PEi，j和PEj，i 由N处理器阵列。讨论矩阵处理算法，然后介绍对角折叠树阵列处理器架构。大型平行对角折叠树阵列处理器通过使用通过折叠通信ALU树互连的PE阵列来支持完全连接的根树处理器。

4. 发明授权

US5682544A Massively parallel diagonal-fold tree array processor 失效
标题翻译：大型平行对角折叠树阵列处理器
公开(公告)号：US5682544A
公开(公告)日：1997-10-28
申请号：US359250
申请日：1994-12-19
申请人： Gerald George Pechanek , Stamatis Vassiliadis , Jose Guadalupe Delgado-Frias
发明人： Gerald George Pechanek , Stamatis Vassiliadis , Jose Guadalupe Delgado-Frias
IPC分类号： G06F15/16 , G06F15/173 , G06F15/18 , G06F15/80 , G06N3/04
CPC分类号： G06F15/8023
摘要： A massively parallel processor apparatus having an instruction set architecture for each of the N.sup.2 the PEs of the structure. The apparatus which we prefer will have a PE structure consisting of PEs that contain instruction and data storage units, receive instructions and data, and execute instructions. The N.sup.2 structure should contain "N" communicating ALU trees, "N" programmable root tree processor units, and an arrangement for communicating both instructions, data, and the root tree processor outputs back to the input processing elements by means of the communicating ALU trees. The apparatus can be structured as a bit-serial or word parallel system. The preferred structure contains N.sup.2 PEs, identified as PE.sub.column,row, in a N root tree processor system, placed in the form of a N by N processor array that has been folded along the diagonal and made up of diagonal cells and general cells. The Diagonal-Cells are comprised of a single processing element identified as PE.sub.i,j of the folded N by N processor array and the General-Cells are comprised of two PEs merged together, identified as PE.sub.i,j and PE.sub.j,i of the folded N by N processor array. Matrix processing algorithms are discussed followed by a presentation of the Diagonal-Fold Tree Array Processor architecture. The Massively Parallel Diagonal-Fold Tree Array Processor supports completely connected root tree processors through the use of the array of PEs that are interconnected by folded communication ALU trees.
摘要翻译：一种大规模并行处理器装置，具有用于结构的每个N 2的指令集架构。我们喜欢的设备将具有由包含指令和数据存储单元，接收指令和数据以及执行指令的PE组成的PE结构。 N2结构应包含“N”个通信ALU树，“N”个可编程根树处理器单元，以及用于通过通信ALU树将指令，数据和根树处理器输出两者传送回输入处理单元的布置。该装置可以被构造为比特串行或字并行系统。优选的结构包含N型PE，在N根树处理器系统中被标识为PE列，行，以N×N处理器阵列的形式放置，该处理器阵列沿对角线折叠并由对角线单元和通用单元构成。对角线电池由单个处理元件组成，标识为折叠N乘N处理器阵列的PEi，j，通用单元由合并在一起的两个PE组成，标识为折叠N的PEi，j和PEj，i 由N处理器阵列。讨论矩阵处理算法，然后介绍对角折叠树阵列处理器架构。大型平行对角折叠树阵列处理器通过使用通过折叠通信ALU树互连的PE阵列来支持完全连接的根树处理器。

5. 发明授权

US5617512A Triangular scalable neural array processor 失效
标题翻译：三角缩放神经阵列处理器
公开(公告)号：US5617512A
公开(公告)日：1997-04-01
申请号：US459191
申请日：1995-06-02
申请人： Gerald G. Pechanek , Stamatis Vassiliadis
发明人： Gerald G. Pechanek , Stamatis Vassiliadis
IPC分类号： G06F15/18 , G06G7/60 , G06N3/04 , G06N3/063 , G06N3/10 , G06N99/00
CPC分类号： G06N3/063 , G06N3/10
摘要： A neural array processor computing structure with a plurality of processing units which have orthogonal sets of neurons and communicating adder trees which provide a reverse communication path. Each processing unit has a weight storage unit. The processing units are arranged so that they are connected to the weight storage units in symmetric pairs. General processing cells share communication paths so that a reduced number of communicating adder trees is used.
摘要翻译：具有多个处理单元的神经阵列处理器计算结构，所述多个处理单元具有提供反向通信路径的正交神经元集合和通信加法器树。每个处理单元具有一个重量存储单元。处理单元被布置成使得它们以对称的对连接到重量存储单元。通用处理单元共享通信路径，从而使用减少数量的通信加法器树。

6. 发明授权

US5613044A Learning machine synapse processor system apparatus 失效
标题翻译：学习机突触处理器系统设备
公开(公告)号：US5613044A
公开(公告)日：1997-03-18
申请号：US459199
申请日：1995-06-02
申请人： Gerald G. Pechanek , Stamatis Vassiliadis , Jose G. Delgado-Frias
发明人： Gerald G. Pechanek , Stamatis Vassiliadis , Jose G. Delgado-Frias
IPC分类号： G06F15/18
CPC分类号： G06N3/063
摘要： A Neural synapse processor apparatus having a neuron architecture for the synapse processing elements of the apparatus. The apparatus which we prefer will have a N neuron structure having synapse processing units that contain instruction and data storage units, receive instructions and data, and execute instructions. The N neuron structure should contain communicating adder trees, neuron activation function units, and an arrangement for communicating both instructions, data, and the outputs of neuron activation function units back to the input synapse processing units by means of the communicating adder trees. The apparatus can be structured as a bit-serial or word parallel system. The preferred structure contains N.sup.2 synapse processing units, each associated with a connection weight in the N neural network to be emulated, placed in the form of a N by N matrix that has been folded along the diagonal and made up of diagonal cells and general cells. Diagonal cells, each utilizing a single synapse processing unit, are associated with the diagonal connection weights of the folded N by N connection weight matrix and general cells, each of which has two synapse processing units merged together, and which are associated with the symmetric connection weights of the folded N by N connection weight matrix. The back-propagation learning algorithm is first discussed followed by a presentation of the learning machine synapse processor architecture. An example implementation of the back-propagation learning algorithm is then presented. This is followed by a Boltzmann like machine example and data parallel examples mapped onto the architecture.
摘要翻译：一种具有用于装置的突触处理元件的神经元结构的神经突触处理器装置。我们喜欢的装置将具有具有包含指令和数据存储单元，接收指令和数据以及执行指令的突触处理单元的N个神经元结构。 N神经元结构应包含通信加法器树，神经激活功能单元和用于通过通信加法器树将神经元激活功能单元的指令，数据和输出传送回输入突触处理单元的布置。该装置可以被构造为比特串行或字并行系统。优选结构包含N 2个突触处理单元，每个N突触处理单元与N个仿真网络中的连接权重相关联，以N×N矩阵的形式放置，该矩阵已经沿对角线折叠并由对角线单元和通用单元组成。每个使用单个突触处理单元的对角线单元与折叠的N乘N连接权重矩阵和通用单元的对角连接权重相关联，每个单元具有合并在一起的两个突触处理单元，并且与对称连接相关联折叠N乘以N连接权重矩阵的权重。首先讨论反向传播学习算法，然后介绍学习机器突触处理器架构。然后呈现反向传播学习算法的示例实现。接下来是一个Boltzmann的机器示例，并将数据并行示例映射到架构上。

7. 发明授权

US5517596A Learning machine synapse processor system apparatus 失效
标题翻译：学习机突触处理器系统设备
公开(公告)号：US5517596A
公开(公告)日：1996-05-14
申请号：US161839
申请日：1993-12-01
申请人： Gerald G. Pechanek , Stamatis Vassiliadis , Jose G. Delgado-Frias
发明人： Gerald G. Pechanek , Stamatis Vassiliadis , Jose G. Delgado-Frias
IPC分类号： G06F15/18
CPC分类号： G06N3/063
摘要： A Neural synapse processor apparatus having a neuron architecture for the synapse processing elements of the apparatus. The apparatus which we prefer will have a N neuron structure having synapse processing units that contain instruction and data storage units, receive instructions and data, and execute instructions. The N neuron structure should contain communicating adder trees, neuron activation function units, and an arrangement for communicating both instructions, data, and the outputs of neuron activation function units back to the input synapse processing units by means of the communicating adder trees. The apparatus can be structured as a bit-serial or word parallel system. The preferred structure contains N.sup.2 synapse processing units, each associated with a connection weight in the N neural network to be emulated, placed in the form of a N by N matrix that has been folded along the diagonal and made up of diagonal cells and general cells. Diagonal cells, each utilizing a single synapse processing unit, are associated with the diagonal connection weights of the folded N by N connection weight matrix and general cells, each of which has two synapse processing units merged together, and which are associated with the symmetric connection weights of the folded N by N connection weight matrix. The back-propagation learning algorithm is first discussed followed by a presentation of the learning machine synapse processor architecture. An example implementation of the back-propagation learning algorithm is then presented. This is followed by a Boltzmann like machine example and data parallel examples mapped onto the architecture.
摘要翻译：一种具有用于装置的突触处理元件的神经元结构的神经突触处理器装置。我们喜欢的装置将具有具有包含指令和数据存储单元，接收指令和数据以及执行指令的突触处理单元的N个神经元结构。 N神经元结构应包含通信加法器树，神经激活功能单元和用于通过通信加法器树将神经元激活功能单元的指令，数据和输出传送回输入突触处理单元的布置。该装置可以被构造为比特串行或字并行系统。优选结构包含N 2个突触处理单元，每个N突触处理单元与N个仿真网络中的连接权重相关联，以N×N矩阵的形式放置，该矩阵已经沿对角线折叠并由对角线单元和通用单元组成。每个使用单个突触处理单元的对角线单元与折叠的N乘N连接权重矩阵和通用单元的对角连接权重相关联，每个单元具有合并在一起的两个突触处理单元，并且与对称连接相关联折叠N乘以N连接权重矩阵的权重。首先讨论反向传播学习算法，然后介绍学习机器突触处理器架构。然后呈现反向传播学习算法的示例实现。接下来是一个Boltzmann的机器示例，并将数据并行示例映射到架构上。

8. 发明授权

US5504932A System for executing scalar instructions in parallel based on control bits appended by compounding decoder 失效
标题翻译：基于由复合解码器附加的控制位并行执行标量指令的系统
公开(公告)号：US5504932A
公开(公告)日：1996-04-02
申请号：US488464
申请日：1995-06-07
申请人： Stamatis Vassiliadis , Bartholomew Blaner , Thomas L. Jeremiah
发明人： Stamatis Vassiliadis , Bartholomew Blaner , Thomas L. Jeremiah
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38
CPC分类号： G06F9/382 , G06F9/30149 , G06F9/3017 , G06F9/3808 , G06F9/3812 , G06F9/3853 , G06F9/3885
摘要： An instruction processor system for decoding compound instructions created from a series of base instructions of a scalar machine, the processor generating a series of compound instructions with an instruction format text having appended control bits in the instruction format text enabling the execution of the compound instruction format text in said instruction processor with a compounding facility which fetches and decodes compound instructions which can be executed as compounded and single instructions by the arithmetic and logic units of the instruction processor while preserving intact the scalar execution of the base instructions of a scalar machine which were originally in storage. The system nullifies any execution of a member instruction unit of a compound instruction upon occurrence of possible conditions, such as branch, which would affect the correctness of recording results of execution of the member instruction unit portion based upon the interrelationship of member units of the compound instruction with other instructions. The resultant series of compounded instructions generally executes in a faster manner than the original format which is preserved due to the parallel nature of the compounded instruction stream which is executed.
摘要翻译：一种指令处理器系统，用于对由标量机的一系列基本指令产生的复合指令进行解码，该处理器产生具有指令格式文本的指令格式文本的一系列复合指令，该指令格式文本具有能够执行复合指令格式的指令格式文本中的附加控制位所述指令处理器中的文本具有复合设备，该复合设备提取和解码可由指令处理器的算术和逻辑单元作为复合指令和单个指令执行的复合指令，同时完整地保持标量机的基本指令的标量执行，最初在存储。该系统在发生可能的条件（例如分支）时，使复合指令的成员指令单元的任何执行无效，这将基于化合物的成员单元的相互关系而影响成员指令单元部分执行的记录结果的正确性指令与其他指令。所得到的一系列复合指令通常比由被执行的复合指令流的并行特性而保留的原始格式更快地执行。

9. 发明授权

US5500942A Method of indicating parallel execution compoundability of scalar instructions based on analysis of presumed instructions 失效
标题翻译：基于假设指令分析指示标量指令的并行执行复合性的方法
公开(公告)号：US5500942A
公开(公告)日：1996-03-19
申请号：US457765
申请日：1995-06-01
申请人： Richard J. Eickemeyer , Stamatis Vassiliadis
发明人： Richard J. Eickemeyer , Stamatis Vassiliadis
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3808 , G06F9/30149 , G06F9/30152 , G06F9/3816 , G06F9/3842 , G06F9/3853
摘要： This is a method of compounding two or more instructions from an instruction stream without knowing the starting point or length of each individual instruction. All instructions include one OP Code at a predetermined field location which identifies the instruction and its length. Those instructions which qualify need to have appropriate tags to indicate they are candidates for compounding. In System 370 where instructions are either 2, 4 or 6 bytes in length, the field positions for the OP Code are presumed based on an estimated instruction length code. The value of each tag based on a presumed OP Code is recorded, and the instruction length code in the presumed OP Code is used to locate a complete sequence of possible instructions. Once an actual instruction boundary is found, the corresponding correct tag values are used to identify the commencement of a compound instruction, and other incorrectly generated tags are ignored.
摘要翻译：这是一种从指令流中复合两个或多个指令而不知道每个单独指令的起始点或长度的方法。所有指令在预定字段位置包括一个OP代码，用于标识指令及其长度。那些符合条件的指令需要有适当的标签来表明它们是复合的候选者。在系统370中，其中指令长度为2,4或6字节，则基于估计的指令长度代码来推定OP代码的字段位置。记录基于假设的OP代码的每个标签的值，并且使用推定的OP代码中的指令长度代码来定位可能的指令的完整序列。一旦发现了实际的指令边界，则使用相应的正确标签值来识别复合指令的开始，并忽略其他错误生成的标签。

10. 发明授权

US5488707A Apparatus for predicting overlapped storage operands for move character 失效
标题翻译：用于预测用于移动角色的重叠存储操作数的装置
公开(公告)号：US5488707A
公开(公告)日：1996-01-30
申请号：US920941
申请日：1992-07-28
申请人： James E. Phillips , Stamatis Vassiliadis
发明人： James E. Phillips , Stamatis Vassiliadis
IPC分类号： G06F9/30 , G06F9/315 , G06F9/34 , G06F12/02 , G06F12/06
CPC分类号： G06F9/30032
摘要： An apparatus is presented and proved for detecting storage operand overlap for instructions having identical overlap detection requirements as the move character (MVC) instruction. The apparatus is applicable to all Enterprise Systems Architecture (ESA)/390 addressing modes encompassing access register addressing for either 24 bit or 31 bit addressing. S/370 addressing in 24 bit and 31 bit modes are also supported by the proposed apparatus and treated as special cases of access register addressing. In addition, the apparatus is extended to support other addressing modes with an example provided to include a 64 bit addressing mode. A fast parallel implementation of the apparatus is also presented. The apparatus results in a one cycle savings for all invocations of the MVC instruction which comprises approximately 2% of the dynamic instruction stream of a representative instruction mix. The one cycle savings results in a 21 percent improvement in the performance of the execution of the MVC instruction for the frequent case (84%) when the operand length is less than or equal to eight bytes and a 9 percent improvement in performance for the less frequent case (16%) in which the operand length is greater than eight bytes.
摘要翻译：提出并证明了用于检测与移动字符（MVC）指令具有相同重叠检测要求的指令的存储操作数重叠的装置。该设备适用于包含24位或31位寻址的访问寄存器寻址的所有企业系统架构（ESA）/ 390寻址模式。所提出的装置也支持24位和31位模式下的S / 370寻址，并被视为访问寄存器寻址的特殊情况。此外，该设备被扩展以支持其他寻址模式，其中提供了示例以包括64位寻址模式。还提出了该装置的快速并行实现。该装置导致MVC指令的所有调用的一个周期节省，其包括代表性指令组合的大约2％的动态指令流。一个周期的节省导致当操作数长度小于或等于八个字节时，针对频繁情况（84％）执行MVC指令的性能提高了21％，性能提高了9％频繁的情况（16％），其中操作数长度大于8字节。

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