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1. 发明授权

US5640586A Scalable parallel group partitioned diagonal-fold switching tree computing apparatus 失效
标题翻译：可扩展并行组分割对角线交换树计算装置
公开(公告)号：US5640586A
公开(公告)日：1997-06-17
申请号：US496826
申请日：1995-06-29
申请人： Gerald George Pechanek , Stamatis Vassiliadis , Jose Guadalupe Delgado-Frias
发明人： Gerald George Pechanek , Stamatis Vassiliadis , Jose Guadalupe Delgado-Frias
IPC分类号： G06F15/16 , G06F15/173 , G06F15/18 , G06F15/80 , G06N3/04 , G06N3/063 , G06N3/10 , G06F17/00
CPC分类号： G06N3/10 , G06F15/8023 , G06N3/063
摘要： A parallel computer architecture supporting neural networks utilizing a novel method of separating a triangular array containing N processing elements on each edge into multiple smaller triangular arrays, each of dimension X and each representing a common building block processor group chip that can be interconnected for various size parallel processing implementations. The group chips are interconnected by a unique switching tree mechanism that maintains the complete connectivity capability and functionality possessed by the original triangular array of dimension N. For a given size K and X, K divisible by X, a triangular array containing K processor elements located on each edge of an equilateral triangular array is partitioned into K/X triangular arrays of dimension X and K(K-X)/2X.sup.2 square processor arrays of dimension X. An algorithm partitions a square array into two triangular arrays, each of dimension X. Assuming K=N and the chosen technology supports the placement of a triangular processor group chip of dimension X on a single chip, the final scalable parallel computing structure for N root tree processors utilizes N.sup.2 /X.sup.2 triangular processor group chips. The partitioning methodology creates a scalable organization of processor elements. An interconnection mechanism preserves the functionality of the original triangular array of dimension N in the implemented structure constructed of multiple triangular arrays of dimension X.
摘要翻译：一种支持神经网络的并行计算机体系结构，其利用将每个边缘上包含N个处理元素的三角形阵列分离成多个较小的三角形阵列的新颖方法，每个维度X和每个代表可以互相连接各种尺寸的公共构建块处理器组芯片并行处理实现。集团芯片通过独特的交换树机制相互连接，维护完整的连接能力和维度N的原始三角形阵列拥有的功能。对于给定的大小K和X，K可由X整除，包含K个处理器元素的三角形阵列在等边三角形阵列的每个边缘上划分为X维和K（KX）/ 2X2个维数X的平方处理器阵列的K / X三角形阵列。一个算法将一个正方形阵列分成两个三角形阵列，每个维数为X。假定 K = N，所选择的技术支持在单个芯片上放置尺寸为X的三角形处理器组芯片，N根树处理器的最终可扩展并行计算结构利用N2 / X2三角形处理器组芯片。分区方法创建一个可扩展的处理器组件。互连机制保留了由尺寸为X的多个三角形阵列构成的实现结构中的尺寸为N的原始三角形阵列的功能。

2. 发明授权

US06405185B1 Massively parallel array processor 失效
标题翻译：大容量并行阵列处理器
公开(公告)号：US06405185B1
公开(公告)日：2002-06-11
申请号：US09551144
申请日：1995-03-23
申请人： Gerald George Pechanek , Stamatis Vassiliadis , Jose Guadalupe Delgado-Frias
发明人： Gerald George Pechanek , Stamatis Vassiliadis , Jose Guadalupe Delgado-Frias
IPC分类号： G06F1518
CPC分类号： G06F15/8023
摘要： Image processing for multimedia workstations is a computationally intensive task requiring special purpose hardware to meet the high speed requirements associated with the task. One type of specialized hardware that meets the computation high speed requirements is the mesh connected computer. Such a computer becomes a massively parallel machine when an array of computers interconnected by a network are replicated in a machine. The nearest neighbor mesh computer consists of an N×N square array of Processor Elements(PEs) where each PE is connected to the North, South, East and West PEs only. The diagonal folded mesh array processor, which is called Oracle, allows the matrix transformation operation to be accomplished in one cycle by simple interchange of the data elements in the dual symmetric processor elements. The use of Oracle for a parallel 2-D convolution mechanish for image processing and multimedia applications and for a finite difference method of solving differential equations is presented, concentrating on the computational aspects of the algorithm.
摘要翻译：多媒体工作站的图像处理是一项计算密集型任务，需要专用硬件来满足与任务相关的高速度要求。一种满足计算高速要求的专用硬件是网状计算机。当通过网络互连的计算机阵列在机器中复制时，这样的计算机成为大规模并行机器。最近的相邻网格计算机由处理器元素（PE）的N×N正方形阵列组成，其中每个PE仅连接到北，南，东和西PE。称为Oracle的对角折叠网格阵列处理器允许通过简单交换双对称处理器元件中的数据元素在一个周期内完成矩阵变换操作。提出了使用Oracle进行图像处理和多媒体应用的并行2-D卷积机制，并提出了一种求解微分方程的有限差分方法，集中在算法的计算方面。

3. 发明授权

US6041398A Massively parallel multiple-folded clustered processor mesh array 失效
标题翻译：大容量并行多折叠集群处理器网格阵列
公开(公告)号：US6041398A
公开(公告)日：2000-03-21
申请号：US904916
申请日：1992-06-26
申请人： Gerald George Pechanek , Stamatis Vassiliadis , Jose Guadalupe Delgado-Frias
发明人： Gerald George Pechanek , Stamatis Vassiliadis , Jose Guadalupe Delgado-Frias
IPC分类号： G06F15/16 , A21B1/24 , A21B1/48 , F24C15/32 , G06F15/173 , G06F15/80
CPC分类号： A21B1/245 , A21B1/48
摘要： A massively parallel diagonal-fold mesh array processor provides a triangular diagonally folded mesh computer with the same functionality as a square mesh computer but with half the number of connection wires. The diagonal-fold mesh array processor is modified in this invention to provide a more general purpose processor node and to enhance the connectivity between the processing nodes while still providing the image processing and finite difference capabilities of the original structure. By repeatedly folding the triangular diagonal-fold array structure, processing elements are placed together which, with additional connections, allows the improvement in connectivity. This enhancement would be difficult to achieve in a standard mesh organization. The resultant folded structure maintains the functionality of the original mesh while expanding its capabilities. A bitonic sort example is presented which demonstrates the utility of the enhanced connectivity. The multiple folded array concept is applied to a six neighborhood hexagonal array demonstrating the general nature of the concept.
摘要翻译：大量平行的对角线网格阵列处理器提供具有与方形网孔计算机相同功能的三角形对角折叠网状计算机，但具有一半数量的连接线。在本发明中修改了对角线网格阵列处理器以提供更通用的处理器节点并且在仍然提供图像处理和原始结构的有限差分能力的同时增强处理节点之间的连接性。通过反复折叠三角形对角线阵列结构，将处理元件放置在一起，通过附加连接允许连接性的提高。这种增强将难以在标准网格组织中实现。所产生的折叠结构在扩展其能力的同时保持原始网格的功能。提出了一个排序示例，显示了增强连接的实用性。将多重折叠阵列概念应用于六邻域六边形阵列，展示了概念的一般性质。

4. 发明授权

US5784632A Parallel diagonal-fold array processor 失效
标题翻译：平行对角线阵列处理器
公开(公告)号：US5784632A
公开(公告)日：1998-07-21
申请号：US415775
申请日：1995-03-30
申请人： Gerald George Pechanek , Stamatis Vassiliadis , Jose Guadalupe Delgado-Frias
发明人： Gerald George Pechanek , Stamatis Vassiliadis , Jose Guadalupe Delgado-Frias
IPC分类号： G06F15/16 , G06F15/173 , G06F15/18 , G06F15/80 , G06N3/04 , G06F15/00
CPC分类号： G06F15/8023
摘要： A massively parallel processor apparatus having an instruction set architecture for each of the N.sup.2 the PEs of the structure. The apparatus which we prefer will have a PE structure consisting of PEs that contain instruction and data storage units, receive instructions and data, and execute instructions. The N.sup.2 structure should contain "N" communicating ALU trees, "N" programmable root tree processor units, and an arrangement for communicating both instructions, data, and the root tree processor outputs back to the input processing elements by means of the communicating ALU trees. The apparatus can be structured as a bit-serial or word parallel system. The preferred structure contains N.sup.2 PEs, identified as PE.sub.column,row, in a N root tree processor system, placed in the form of a N by N processor array that has been folded along the diagonal and made up of diagonal cells and general cells. The Diagonal-Cells are comprised of a single processing element identified as PE.sub.i,i of the folded N by N processor array and the General-Cells are comprised of two PEs merged together, identified as PE.sub.i,j and PE.sub.j,i of the folded N by N processor array. Matrix processing algorithms are discussed followed by a presentation of the Diagonal-Fold Tree Array Processor architecture. The Massively Parallel Diagonal-Fold Tree Array Processor supports completely connected root tree processors through the use of the array of PEs that are interconnected by folded communication ALU trees.
摘要翻译：一种大规模并行处理器装置，具有用于结构的每个N 2的指令集架构。我们喜欢的设备将具有由包含指令和数据存储单元，接收指令和数据以及执行指令的PE组成的PE结构。 N2结构应包含“N”个通信ALU树，“N”个可编程根树处理器单元，以及用于通过通信ALU树将指令，数据和根树处理器输出两者传送回输入处理单元的布置。该装置可以被构造为比特串行或字并行系统。优选的结构包含N型PE，在N根树处理器系统中被标识为PE列，行，以N×N处理器阵列的形式放置，该处理器阵列沿对角线折叠并由对角线单元和通用单元构成。对角线单元由标识为由N处理器阵列折叠的N i的单个处理元件组成，并且通用单元由合并在一起的两个PE组成，标识为折叠N的PEi，j和PEj，i 由N处理器阵列。讨论矩阵处理算法，然后介绍对角折叠树阵列处理器架构。大型平行对角折叠树阵列处理器通过使用通过折叠通信ALU树互连的PE阵列来支持完全连接的根树处理器。

5. 发明授权

US5682544A Massively parallel diagonal-fold tree array processor 失效
标题翻译：大型平行对角折叠树阵列处理器
公开(公告)号：US5682544A
公开(公告)日：1997-10-28
申请号：US359250
申请日：1994-12-19
申请人： Gerald George Pechanek , Stamatis Vassiliadis , Jose Guadalupe Delgado-Frias
发明人： Gerald George Pechanek , Stamatis Vassiliadis , Jose Guadalupe Delgado-Frias
IPC分类号： G06F15/16 , G06F15/173 , G06F15/18 , G06F15/80 , G06N3/04
CPC分类号： G06F15/8023
摘要： A massively parallel processor apparatus having an instruction set architecture for each of the N.sup.2 the PEs of the structure. The apparatus which we prefer will have a PE structure consisting of PEs that contain instruction and data storage units, receive instructions and data, and execute instructions. The N.sup.2 structure should contain "N" communicating ALU trees, "N" programmable root tree processor units, and an arrangement for communicating both instructions, data, and the root tree processor outputs back to the input processing elements by means of the communicating ALU trees. The apparatus can be structured as a bit-serial or word parallel system. The preferred structure contains N.sup.2 PEs, identified as PE.sub.column,row, in a N root tree processor system, placed in the form of a N by N processor array that has been folded along the diagonal and made up of diagonal cells and general cells. The Diagonal-Cells are comprised of a single processing element identified as PE.sub.i,j of the folded N by N processor array and the General-Cells are comprised of two PEs merged together, identified as PE.sub.i,j and PE.sub.j,i of the folded N by N processor array. Matrix processing algorithms are discussed followed by a presentation of the Diagonal-Fold Tree Array Processor architecture. The Massively Parallel Diagonal-Fold Tree Array Processor supports completely connected root tree processors through the use of the array of PEs that are interconnected by folded communication ALU trees.
摘要翻译：一种大规模并行处理器装置，具有用于结构的每个N 2的指令集架构。我们喜欢的设备将具有由包含指令和数据存储单元，接收指令和数据以及执行指令的PE组成的PE结构。 N2结构应包含“N”个通信ALU树，“N”个可编程根树处理器单元，以及用于通过通信ALU树将指令，数据和根树处理器输出两者传送回输入处理单元的布置。该装置可以被构造为比特串行或字并行系统。优选的结构包含N型PE，在N根树处理器系统中被标识为PE列，行，以N×N处理器阵列的形式放置，该处理器阵列沿对角线折叠并由对角线单元和通用单元构成。对角线电池由单个处理元件组成，标识为折叠N乘N处理器阵列的PEi，j，通用单元由合并在一起的两个PE组成，标识为折叠N的PEi，j和PEj，i 由N处理器阵列。讨论矩阵处理算法，然后介绍对角折叠树阵列处理器架构。大型平行对角折叠树阵列处理器通过使用通过折叠通信ALU树互连的PE阵列来支持完全连接的根树处理器。

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