专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5509106A Triangular scalable neural array processor 失效
标题翻译：三角缩放神经阵列处理器
公开(公告)号：US5509106A
公开(公告)日：1996-04-16
申请号：US231853
申请日：1994-04-22
申请人： Gerald G. Pechanek , Stamatis Vassiliadis
发明人： Gerald G. Pechanek , Stamatis Vassiliadis
IPC分类号： G06F15/18 , G06G7/60 , G06N3/04 , G06N3/063 , G06N3/10 , G06N99/00
CPC分类号： G06N3/063 , G06N3/10
摘要： A triangular scalable neural array processor unit for use in a neural network and having multipliers, communicating adder trees, sigmoid generators, and a reverse feedback loop for communicating the output of a sigmoid generator back to input multipliers of selected neurons.
摘要翻译：一种用于神经网络并具有乘法器，通信加法器树，S形发生器和反向反馈回路的三角形可扩展神经阵列处理器单元，用于将S型输出端的输出反馈到选定神经元的输入乘法器。

2. 发明授权

US4924422A Method and apparatus for modified carry-save determination of arithmetic/logic zero results 失效
标题翻译：用于修改进位保存确定算术/逻辑零结果的方法和装置
公开(公告)号：US4924422A
公开(公告)日：1990-05-08
申请号：US157500
申请日：1988-02-17
申请人： Stamatis Vassiliadis , Michael Putrino , Ann E. Huffman , Brice J. Feal , Gerald G. Pechanek
发明人： Stamatis Vassiliadis , Michael Putrino , Ann E. Huffman , Brice J. Feal , Gerald G. Pechanek
IPC分类号： G06F7/02 , G06F7/50 , G06F7/507 , G06F7/508 , G06F7/57 , G06F9/32
CPC分类号： G06F7/57 , G06F7/026 , G06F7/505 , G06F9/30094 , G06F7/49905
摘要： The invention determines when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from half sum to carry and transmit operators derived from the input operands. These operands are used in some known types of adders and, thus may be provided from a parallel adder to the condition prediction circuitry. In another embodiment, the equations for a carry-save-adder are modified to provide a circuit specifically designed for the determination of the condition when the sum of the operands is equal to zero. This sum is equal to zero circuit greatly reduces the gate delay and gate count thus allowing the central processing unit to determine the condition prior to the actual sum of two operands. This allows the CPU to react to the condition more quickly, thus increasing overall system speed.

3. 发明授权

US5617512A Triangular scalable neural array processor 失效
标题翻译：三角缩放神经阵列处理器
公开(公告)号：US5617512A
公开(公告)日：1997-04-01
申请号：US459191
申请日：1995-06-02
申请人： Gerald G. Pechanek , Stamatis Vassiliadis
发明人： Gerald G. Pechanek , Stamatis Vassiliadis
IPC分类号： G06F15/18 , G06G7/60 , G06N3/04 , G06N3/063 , G06N3/10 , G06N99/00
CPC分类号： G06N3/063 , G06N3/10
摘要： A neural array processor computing structure with a plurality of processing units which have orthogonal sets of neurons and communicating adder trees which provide a reverse communication path. Each processing unit has a weight storage unit. The processing units are arranged so that they are connected to the weight storage units in symmetric pairs. General processing cells share communication paths so that a reduced number of communicating adder trees is used.
摘要翻译：具有多个处理单元的神经阵列处理器计算结构，所述多个处理单元具有提供反向通信路径的正交神经元集合和通信加法器树。每个处理单元具有一个重量存储单元。处理单元被布置成使得它们以对称的对连接到重量存储单元。通用处理单元共享通信路径，从而使用减少数量的通信加法器树。

4. 发明授权

US5613044A Learning machine synapse processor system apparatus 失效
标题翻译：学习机突触处理器系统设备
公开(公告)号：US5613044A
公开(公告)日：1997-03-18
申请号：US459199
申请日：1995-06-02
申请人： Gerald G. Pechanek , Stamatis Vassiliadis , Jose G. Delgado-Frias
发明人： Gerald G. Pechanek , Stamatis Vassiliadis , Jose G. Delgado-Frias
IPC分类号： G06F15/18
CPC分类号： G06N3/063
摘要： A Neural synapse processor apparatus having a neuron architecture for the synapse processing elements of the apparatus. The apparatus which we prefer will have a N neuron structure having synapse processing units that contain instruction and data storage units, receive instructions and data, and execute instructions. The N neuron structure should contain communicating adder trees, neuron activation function units, and an arrangement for communicating both instructions, data, and the outputs of neuron activation function units back to the input synapse processing units by means of the communicating adder trees. The apparatus can be structured as a bit-serial or word parallel system. The preferred structure contains N.sup.2 synapse processing units, each associated with a connection weight in the N neural network to be emulated, placed in the form of a N by N matrix that has been folded along the diagonal and made up of diagonal cells and general cells. Diagonal cells, each utilizing a single synapse processing unit, are associated with the diagonal connection weights of the folded N by N connection weight matrix and general cells, each of which has two synapse processing units merged together, and which are associated with the symmetric connection weights of the folded N by N connection weight matrix. The back-propagation learning algorithm is first discussed followed by a presentation of the learning machine synapse processor architecture. An example implementation of the back-propagation learning algorithm is then presented. This is followed by a Boltzmann like machine example and data parallel examples mapped onto the architecture.
摘要翻译：一种具有用于装置的突触处理元件的神经元结构的神经突触处理器装置。我们喜欢的装置将具有具有包含指令和数据存储单元，接收指令和数据以及执行指令的突触处理单元的N个神经元结构。 N神经元结构应包含通信加法器树，神经激活功能单元和用于通过通信加法器树将神经元激活功能单元的指令，数据和输出传送回输入突触处理单元的布置。该装置可以被构造为比特串行或字并行系统。优选结构包含N 2个突触处理单元，每个N突触处理单元与N个仿真网络中的连接权重相关联，以N×N矩阵的形式放置，该矩阵已经沿对角线折叠并由对角线单元和通用单元组成。每个使用单个突触处理单元的对角线单元与折叠的N乘N连接权重矩阵和通用单元的对角连接权重相关联，每个单元具有合并在一起的两个突触处理单元，并且与对称连接相关联折叠N乘以N连接权重矩阵的权重。首先讨论反向传播学习算法，然后介绍学习机器突触处理器架构。然后呈现反向传播学习算法的示例实现。接下来是一个Boltzmann的机器示例，并将数据并行示例映射到架构上。

5. 发明授权

US5517596A Learning machine synapse processor system apparatus 失效
标题翻译：学习机突触处理器系统设备
公开(公告)号：US5517596A
公开(公告)日：1996-05-14
申请号：US161839
申请日：1993-12-01
申请人： Gerald G. Pechanek , Stamatis Vassiliadis , Jose G. Delgado-Frias
发明人： Gerald G. Pechanek , Stamatis Vassiliadis , Jose G. Delgado-Frias
IPC分类号： G06F15/18
CPC分类号： G06N3/063
摘要： A Neural synapse processor apparatus having a neuron architecture for the synapse processing elements of the apparatus. The apparatus which we prefer will have a N neuron structure having synapse processing units that contain instruction and data storage units, receive instructions and data, and execute instructions. The N neuron structure should contain communicating adder trees, neuron activation function units, and an arrangement for communicating both instructions, data, and the outputs of neuron activation function units back to the input synapse processing units by means of the communicating adder trees. The apparatus can be structured as a bit-serial or word parallel system. The preferred structure contains N.sup.2 synapse processing units, each associated with a connection weight in the N neural network to be emulated, placed in the form of a N by N matrix that has been folded along the diagonal and made up of diagonal cells and general cells. Diagonal cells, each utilizing a single synapse processing unit, are associated with the diagonal connection weights of the folded N by N connection weight matrix and general cells, each of which has two synapse processing units merged together, and which are associated with the symmetric connection weights of the folded N by N connection weight matrix. The back-propagation learning algorithm is first discussed followed by a presentation of the learning machine synapse processor architecture. An example implementation of the back-propagation learning algorithm is then presented. This is followed by a Boltzmann like machine example and data parallel examples mapped onto the architecture.
摘要翻译：一种具有用于装置的突触处理元件的神经元结构的神经突触处理器装置。我们喜欢的装置将具有具有包含指令和数据存储单元，接收指令和数据以及执行指令的突触处理单元的N个神经元结构。 N神经元结构应包含通信加法器树，神经激活功能单元和用于通过通信加法器树将神经元激活功能单元的指令，数据和输出传送回输入突触处理单元的布置。该装置可以被构造为比特串行或字并行系统。优选结构包含N 2个突触处理单元，每个N突触处理单元与N个仿真网络中的连接权重相关联，以N×N矩阵的形式放置，该矩阵已经沿对角线折叠并由对角线单元和通用单元组成。每个使用单个突触处理单元的对角线单元与折叠的N乘N连接权重矩阵和通用单元的对角连接权重相关联，每个单元具有合并在一起的两个突触处理单元，并且与对称连接相关联折叠N乘以N连接权重矩阵的权重。首先讨论反向传播学习算法，然后介绍学习机器突触处理器架构。然后呈现反向传播学习算法的示例实现。接下来是一个Boltzmann的机器示例，并将数据并行示例映射到架构上。

6. 发明授权

US5065339A Orthogonal row-column neural processor 失效
标题翻译：正交圆柱神经处理器
公开(公告)号：US5065339A
公开(公告)日：1991-11-12
申请号：US526866
申请日：1990-05-22
申请人： Stamatis Vassiliadis , Gerald G. Pechanek
发明人： Stamatis Vassiliadis , Gerald G. Pechanek
IPC分类号： G06F15/18 , G06G7/60 , G06N3/04 , G06N3/063 , G06N3/10 , G06N99/00
CPC分类号： G06N3/063 , G06N3/10
摘要： The neural computing paradigm is characterized as a dynamic and highly parallel computationally intensive system typically consisting of input weight multiplications, product summation, neural state calculations, and complete connectivity among the neurons. Herein is described neural network architecture called SNAP which uses a unique intercommunication scheme within an array structure that provides high performance for completely connected network models such as the Hopfield model. SNAP's packaging and expansion capabilities are addressed, demonstrating SNAP's scalability to larger networks. Each neuron generating a neuron value from a selected set of input function elements and communicating said neuron value back to said set of input function elements. The total connectivity of each neuron to all neurons is accomplished by an orthogonal row-column relationship of neurons where a given multiplier element operates during a first cycle as a row element within an input function to a column neuron, and during a second cycle as a column element within an input function to a row neuron.

7. 发明授权

US5649135A Parallel processing system and method using surrogate instructions 失效
标题翻译：并行处理系统和使用代理指令的方法
公开(公告)号：US5649135A
公开(公告)日：1997-07-15
申请号：US373128
申请日：1995-01-17
申请人： Gerald G. Pechanek , Clair John Glossner , Larry D. Larsen , Stamatis Vassiliadis
发明人： Gerald G. Pechanek , Clair John Glossner , Larry D. Larsen , Stamatis Vassiliadis
IPC分类号： G06F9/318 , G06F9/38 , G06F15/16 , G06F15/80 , G06F9/355
CPC分类号： G06F9/3885 , G06F17/142 , G06F9/30072 , G06F9/30181
摘要： A parallel processing system and method is disclosed, which provides an improved instruction distribution mechanism for a parallel processing array. The invention broadcasts a basic instruction to each of a plurality of processor elements. Each processor element decodes the same instruction by combining it with a unique offset value stored in each respective processor element, to produce a derived instruction that is unique to the processor element. A first type of basic instruction results in the processor element performing a logical or control operation. A second type of basic instruction results in the generation of a pointer address. The pointer address has a unique address value because it results from combining the basic instruction with the unique offset value stored at the processor element. The pointer address is used to access an alternative instruction from an alternative instruction storage, for execution in the processor element. The alternative instruction is a very long instruction word, whose length is, for example, an integral multiple of the length of the basic instruction and contains much more information than can be represented by the basic instruction. A very long instruction word such as this is useful for providing parallel control of a plurality of primitive execution units that reside within the processor element. In this manner, a high degree of flexibility and versatility is attained in the operation of processor elements of a parallel processing array.
摘要翻译：公开了一种并行处理系统和方法，其提供了用于并行处理阵列的改进的指令分配机制。本发明向多个处理器元件中的每一个广播基本指令。每个处理器元件通过将其与存储在每个相应处理器元件中的唯一偏移值组合来解码相同的指令，以产生对于处理器元件唯一的导出指令。第一类基本指令导致处理器元件执行逻辑或控制操作。第二种类型的基本指令导致生成指针地址。指针地址具有唯一的地址值，因为它是将基本指令与存储在处理器元件中的唯一偏移值组合而产生的。指针地址用于从替代指令存储器访问替代指令，以在处理器元件中执行。替代指令是非常长的指令字，其长度例如是基本指令的长度的整数倍，并且包含比基本指令可以表示的更多的信息。诸如此类的非常长的指令字对于提供驻留在处理器元件内的多个基本执行单元的并行控制是有用的。以这种方式，在并行处理阵列的处理器元件的操作中获得高度的灵活性和多功能性。

8. 发明授权

US5251287A Apparatus and method for neural processing 失效
标题翻译：用于神经处理的装置和方法
公开(公告)号：US5251287A
公开(公告)日：1993-10-05
申请号：US915
申请日：1993-01-06
申请人： Stamatis Vassiliadis , Gerald G. Pechanek
发明人： Stamatis Vassiliadis , Gerald G. Pechanek
IPC分类号： G06N3/063 , G06N3/10 , G06F15/18
CPC分类号： G06N3/10 , G06N3/063
摘要： The neural computing paradigm is characterized as a dynamic and highly computationally intensive system typically consisting of input weight multiplications, product summation, neural state calculations, and complete connectivity among the neurons. Herein is described neural network architecture for a Scalable Neural Array Process (SNAP) which uses a unique interconnection and communication scheme within an array structure that provides high performance for completely connected network models such as the Hopfield model. SNAP's packaging and expansion capabilities are addressed, demonstrating SNAP's scalability to larger networks. The array processor is made up of multiple sets of orthogonal interconnections and activity generators. Each activity generator is responsive to an output signal in order to generate a neuron value. The interconnection structure also uses special adder trees which respond in a first state to generate an output signal and in a second state to communicate a neuron value back to the input of the array processor.
摘要翻译：神经计算范式被表征为动态和高度计算密集型系统，通常由输入权重乘积，乘积求和，神经状态计算以及神经元之间的完全连通性组成。这里描述了用于可扩展神经阵列过程（SNAP）的神经网络架构，其使用阵列结构内的唯一的互连和通信方案，其为诸如Hopfield模型的完全连接的网络模型提供高性能。 SNAP的封装和扩展功能得到了解决，展示了SNAP对较大网络的可扩展性。阵列处理器由多组正交互连和活动发生器组成。每个活动发生器响应于输出信号以产生神经元值。互连结构还使用特殊加法器树，其在第一状态下响应以产生输出信号，并且处于第二状态以将神经元值传送回阵列处理器的输入。

9. 发明授权

US4947359A Apparatus and method for prediction of zero arithmetic/logic results 失效
标题翻译：用于预测零运算/逻辑结果的装置和方法
公开(公告)号：US4947359A
公开(公告)日：1990-08-07
申请号：US346147
申请日：1989-05-01
申请人： Stamatis Vassiliadis , Michael Putrino , Ann E. Huffman , Brice J. Feal , Gerald G. Pechanek
发明人： Stamatis Vassiliadis , Michael Putrino , Ann E. Huffman , Brice J. Feal , Gerald G. Pechanek
IPC分类号： G06F7/02 , G06F7/50 , G06F7/57 , G06F9/32
CPC分类号： G06F7/57 , G06F7/026 , G06F7/505 , G06F9/30094 , G06F7/49905
摘要： The invention determines when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from half sum to carry and transmit operators derived from the input operands. These operands are used in some known types of adders and, thus may be provided from a parallel adder to the condition prediction circuitry. In another embodiment, the equations for a carry-save-adder are modified to provide a circuit specifically designed for the determination of the condition when the sum of the operands is equal to zero. This sum is equal to zero circuit greatly reduces the gate delay and gate count thus allowing the central processing unit to determine the condition prior to the actual sum of two operands. This allows the CPU to react to the condition more quickly, thus increasing overall system speed.
摘要翻译：本发明确定何时两个操作数在不使用加法器的情况下直接等效于操作数。在一个实施例中，等于零的和的条件由半数确定以携带和发送从输入操作数导出的运算符。这些操作数用于一些已知类型的加法器，并且因此可以从并行加法器提供给条件预测电路。在另一个实施例中，用于进位保存加法器的等式被修改以提供专门设计用于当操作数之和等于零时确定条件的电路。该和等于零电路大大减少了门延迟和门数，从而允许中央处理单元确定两个操作数的实际总和之前的状态。这样就可以使CPU更快地对条件作出反应，从而提高整体系统的速度。

10. 发明授权

US5577262A Parallel array processor interconnections 失效
标题翻译：并行阵列处理器互连
公开(公告)号：US5577262A
公开(公告)日：1996-11-19
申请号：US522163
申请日：1995-07-13
申请人： Gerald G. Pechanek , Stamatis Vassiliadis , Jose G. Delgado-Fnias
发明人： Gerald G. Pechanek , Stamatis Vassiliadis , Jose G. Delgado-Fnias
IPC分类号： G06F15/80 , G06N3/063 , G06N3/10 , G06F15/00
CPC分类号： G06N3/063 , G06F15/8023 , G06N3/10
摘要： Image processing for multimedia workstations is a computationally intensive task requiring special purpose hardware to meet the high speed requirements associated with the task. One type of specialized hardware that meets the computation high speed requirements is the mesh connected computer. Such a computer becomes a massively parallel machine when an array of computers interconnected by a network are replicated in a machine. The nearest neighbor mesh computer consists of an N.times.N square array of Processor Elements(PEs) where each PE is connected to the North, South, East and West PEs only. Assuming a single wire interface between PEs, there are a total of 2N.sup.2 wires in the mesh structure. Under the assumtion of SIMD operation with uni-directional message and data transfers between the processing elements in the meah, for example all PES transferring data North, it is possible to reconfigure the array by placing the symmetric processing elements together and sharing the north-south wires with the east-west wires, thereby reducing the wiring complexity in half, i.e. N.sup.2 without affecting performance. The resulting diagonal folded mesh array processor, which is called Oracle, allows the matrix transformation operation to be accomplished in one cycle by simple interchange of the data elements in the dual symmetric processor elements. The use of Oracle for a parallel 2-D convolution mechanish for image processing and multimedia applications and for a finite difference method of solving differential equations is presented, concentrating on the computational aspects of the algorithm.
摘要翻译：多媒体工作站的图像处理是一项计算密集型任务，需要专用硬件来满足与任务相关的高速度要求。一种满足计算高速要求的专用硬件是网状计算机。当通过网络互连的计算机阵列在机器中复制时，这样的计算机成为大规模并行机器。最近的相邻网格计算机由处理器元素（PE）的N×N正方形阵列组成，其中每个PE仅连接到北，南，东和西PE。假设PE之间的单线接口，网格结构中总共有2N2条线。在SIMD操作的假设下，单向消息和数据传输在meah中的处理元素之间，例如所有PES传输数据北部，可以通过将对称处理元素放置在一起并共享南北部来重新配置阵列电线与东西电线，从而将布线复杂度降低一半，即N2不影响性能。所得到的对称折叠网格阵列处理器（称为Oracle）允许通过简单地交换双对称处理器元件中的数据元素在一个周期内完成矩阵变换操作。提出了使用Oracle进行图像处理和多媒体应用的并行2-D卷积机制，并提出了一种求解微分方程的有限差分方法，集中在算法的计算方面。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式