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    • 5. 发明申请
    • Semiconductor Integrated Circuit
    • 半导体集成电路
    • US20080308945A1
    • 2008-12-18
    • US12137623
    • 2008-06-12
    • Takeshi IshigakiNoriaki Matsunaga
    • Takeshi IshigakiNoriaki Matsunaga
    • H01L23/48
    • H01L21/76816H01L23/5226H01L2924/0002H01L2924/00
    • A semiconductor integrated circuit according to an example of the present invention includes a first interconnect extending in a first direction, a second interconnect arranged over the first interconnect and extending in a second direction intersecting the first direction, a first via for connecting a first contact part of the first interconnect and a second contact part of the second interconnect, and a second via for connecting a third contact part of the first interconnect and a fourth contact part of the second interconnect. The first and third contact parts are arranged by being aligned in the first direction, and the second and fourth contact parts are arranged by being aligned in the second direction.
    • 根据本发明的示例的半导体集成电路包括:沿第一方向延伸的第一互连,布置在第一互连上并沿与第一方向相交的第二方向延伸的第二互连;第一通孔,用于连接第一接触部分 和第二互连的第二接触部分,以及用于连接第一互连的第三接触部分和第二互连的第四接触部分的第二通孔。 第一接触部和第三接触部通过沿第一方向排列配置,第二接触部和第四接触部通过沿第二方向对准而配置。
    • 9. 发明申请
    • Method for designing a semiconductor integrated circuit and a semiconductor integrated circuit
    • 半导体集成电路和半导体集成电路的设计方法
    • US20050155001A1
    • 2005-07-14
    • US10988658
    • 2004-11-16
    • Koichi KinoshitaTakeshi IshigakiYukihiro Urakawa
    • Koichi KinoshitaTakeshi IshigakiYukihiro Urakawa
    • G06F17/50H01L21/82
    • G06F17/5045
    • A method for designing a semiconductor integrated circuit, includes placing first, second and third cells, respectively including first stage synchronous circuit having signal propagation time, second stage synchronous circuit having a signal propagation time almost equal to the first stage synchronous circuit, and logic circuit; routing wirings so as to electrically connect the first to third cells; verifying signal propagation timing of the semiconductor integrated circuit having the first to third cells; adjusting the signal propagation timing based on critical path of the signal propagation timing of the semiconductor integrated circuit; and extracting the critical path to replace the second stage synchronous circuit by synchronous circuit of different synchronous type from the first stage synchronous circuit so as to provide a shorter signal propagation time than the first stage synchronous circuit.
    • 一种用于设计半导体集成电路的方法,包括分别包括具有信号传播时间的第一级同步电路的第一,第二和第三单元,具有几乎等于第一级同步电路的信号传播时间的第二级同步电路和逻辑电路 ; 路由布线以便电连接第一至第三单元; 验证具有第一至第三小区的半导体集成电路的信号传播定时; 基于半导体集成电路的信号传播定时的关键路径调整信号传播定时; 并通过与第一级同步电路不同同步型的同步电路提取替代第二级同步电路的关键路径,以提供比第一级同步电路更短的信号传播时间。
    • 10. 发明授权
    • Semiconductor integrated circuit
    • 半导体集成电路
    • US07999390B2
    • 2011-08-16
    • US12137623
    • 2008-06-12
    • Takeshi IshigakiNoriaki Matsunaga
    • Takeshi IshigakiNoriaki Matsunaga
    • H01L23/48
    • H01L21/76816H01L23/5226H01L2924/0002H01L2924/00
    • A semiconductor integrated circuit according to an example of the present invention includes a first interconnect extending in a first direction, a second interconnect arranged over the first interconnect and extending in a second direction intersecting the first direction, a first via for connecting a first contact part of the first interconnect and a second contact part of the second interconnect, and a second via for connecting a third contact part of the first interconnect and a fourth contact part of the second interconnect. The first and third contact parts are arranged by being aligned in the first direction, and the second and fourth contact parts are arranged by being aligned in the second direction.
    • 根据本发明的示例的半导体集成电路包括:沿第一方向延伸的第一互连,布置在第一互连上并沿与第一方向相交的第二方向延伸的第二互连;第一通孔,用于连接第一接触部分 和第二互连的第二接触部分,以及用于连接第一互连的第三接触部分和第二互连的第四接触部分的第二通孔。 第一接触部和第三接触部通过沿第一方向排列配置,第二接触部和第四接触部通过沿第二方向对准而配置。