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1. 发明申请

US20110163367A1 Semiconductor Devices Comprising a Plurality of Gate Structures 有权
标题翻译：包含多个栅极结构的半导体器件
公开(公告)号：US20110163367A1
公开(公告)日：2011-07-07
申请号：US13050335
申请日：2011-03-17
申请人： Dae-Woong Kang , Sung-Nam Chang , Jin-Joo Kim , Kyong-Joo Lee , Eun-Jung Lee
发明人： Dae-Woong Kang , Sung-Nam Chang , Jin-Joo Kim , Kyong-Joo Lee , Eun-Jung Lee
IPC分类号： H01L29/788
CPC分类号： H01L21/764 , H01L21/823456 , H01L21/823468 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529 , H01L27/11568 , H01L27/11573
摘要： Semiconductor devices are provided. The semiconductor devices may include a plurality of gate structures disposed on a semiconductor substrate, each of the gate structures including a floating gate, an inter-gate dielectric layer, and a control gate. The semiconductor devices may also include liners on opposing sidewalls of adjacent ones of the gate structures. The liners may define a gap. A first width of the gap may be less than a second width of the gap.
摘要翻译：提供半导体器件。半导体器件可以包括设置在半导体衬底上的多个栅极结构，每个栅极结构包括浮置栅极，栅极间电介质层和控制栅极。半导体器件还可以包括在相邻栅极结构的相对侧壁上的衬垫。衬垫可以限定间隙。间隙的第一宽度可以小于间隙的第二宽度。

2. 发明申请

US20100295113A1 SEMICONDUCTOR DEVICES COMPRISING A PLURALITY OF GATE STRUCTURES 有权
标题翻译：包含大量门结构的半导体器件
公开(公告)号：US20100295113A1
公开(公告)日：2010-11-25
申请号：US12847351
申请日：2010-07-30
申请人： Dae-Woong Kang , Sung-Nam Chang , Jin-Joo Kim , Kyong-Joo Lee , Eun-Jung Lee
发明人： Dae-Woong Kang , Sung-Nam Chang , Jin-Joo Kim , Kyong-Joo Lee , Eun-Jung Lee
IPC分类号： H01L29/788
CPC分类号： H01L21/76 , H01L21/764 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： Semiconductor devices including a plurality of gate structures disposed on a semiconductor substrate are provided. Each of the gate structures includes a tunnel dielectric layer, a floating gate, an inter-gate dielectric layer, a control gate, and a mask layer. Liners cover opposing sidewalls of adjacent floating gates. Spacers are disposed on the liners, the spacers protruding from opposing sidewalls of adjacent ones of the gate structures, and a top of each of the spacers is disposed below a top of a corresponding one of the gate structures. The liners define sidewalls of respective air gaps and the spacers define tops of the respective air gaps.
摘要翻译：提供包括设置在半导体衬底上的多个栅极结构的半导体器件。栅极结构中的每一个包括隧道介电层，浮置栅极，栅极间介电层，控制栅极和掩模层。衬套覆盖相邻浮动门的相对侧壁。间隔件设置在衬垫上，间隔件从相邻栅极结构的相对侧壁突出，并且每个间隔件的顶部设置在相应的一个栅极结构的顶部的下方。衬垫限定相应空气间隙的侧壁，间隔件限定相应气隙的顶部。

3. 发明授权

US08436410B2 Semiconductor devices comprising a plurality of gate structures 有权
标题翻译：包括多个栅极结构的半导体器件
公开(公告)号：US08436410B2
公开(公告)日：2013-05-07
申请号：US13050335
申请日：2011-03-17
申请人： Dae-Woong Kang , Sung-Nam Chang , Jin-Joo Kim , Kyong-Joo Lee , Eun-Jung Lee
发明人： Dae-Woong Kang , Sung-Nam Chang , Jin-Joo Kim , Kyong-Joo Lee , Eun-Jung Lee
IPC分类号： H01L29/788
CPC分类号： H01L21/764 , H01L21/823456 , H01L21/823468 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529 , H01L27/11568 , H01L27/11573
摘要： Semiconductor devices are provided. The semiconductor devices may include a plurality of gate structures disposed on a semiconductor substrate, each of the gate structures including a floating gate, an inter-gate dielectric layer, and a control gate. The semiconductor devices may also include liners on opposing sidewalls of adjacent ones of the gate structures. The liners may define a gap. A first width of the gap may be less than a second width of the gap.
摘要翻译：提供半导体器件。半导体器件可以包括设置在半导体衬底上的多个栅极结构，每个栅极结构包括浮置栅极，栅极间介电层和控制栅极。半导体器件还可以包括在相邻栅极结构的相对侧壁上的衬垫。衬垫可以限定间隙。间隙的第一宽度可以小于间隙的第二宽度。

4. 发明授权

US08362542B2 Semiconductor devices comprising a plurality of gate structures 有权
标题翻译：包括多个栅极结构的半导体器件
公开(公告)号：US08362542B2
公开(公告)日：2013-01-29
申请号：US12847351
申请日：2010-07-30
申请人： Dae-Woong Kang , Sung-Nam Chang , Jin-Joo Kim , Kyong-Joo Lee , Eun-Jung Lee
发明人： Dae-Woong Kang , Sung-Nam Chang , Jin-Joo Kim , Kyong-Joo Lee , Eun-Jung Lee
IPC分类号： H01L29/788
CPC分类号： H01L21/76 , H01L21/764 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： Semiconductor devices including a plurality of gate structures disposed on a semiconductor substrate are provided. Each of the gate structures includes a tunnel dielectric layer, a floating gate, an inter-gate dielectric layer, a control gate, and a mask layer. Liners cover opposing sidewalls of adjacent floating gates. Spacers are disposed on the liners, the spacers protruding from opposing sidewalls of adjacent ones of the gate structures, and a top of each of the spacers is disposed below a top of a corresponding one of the gate structures. The liners define sidewalls of respective air gaps and the spacers define tops of the respective air gaps.
摘要翻译：提供包括设置在半导体衬底上的多个栅极结构的半导体器件。栅极结构中的每一个包括隧道介电层，浮置栅极，栅极间介电层，控制栅极和掩模层。衬套覆盖相邻浮动门的相对侧壁。间隔件设置在衬垫上，间隔件从相邻栅极结构的相对侧壁突出，并且每个间隔件的顶部设置在相应的一个栅极结构的顶部的下方。衬垫限定相应空气间隙的侧壁，间隔件限定相应气隙的顶部。

5. 发明授权

US07508048B2 Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby 有权
标题翻译：制造具有多栅极绝缘层的半导体器件和由此制造的半导体器件的方法
公开(公告)号：US07508048B2
公开(公告)日：2009-03-24
申请号：US10758802
申请日：2004-01-15
申请人： Dae-Woong Kang , Hong-Soo Kim , Jung-Dal Choi , Kyu-Charn Park , Seong-Soon Cho , Yong-Sik Yim , Sung-Nam Chang
发明人： Dae-Woong Kang , Hong-Soo Kim , Jung-Dal Choi , Kyu-Charn Park , Seong-Soon Cho , Yong-Sik Yim , Sung-Nam Chang
IPC分类号： H01L29/00
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11526 , H01L27/11543
摘要： Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby are provided. The method includes forming a pad insulation layer and an initial high voltage gate insulation layer on a first region and a second region of a semiconductor substrate respectively. The initial high voltage gate insulation layer is formed to be thicker than the pad insulation layer. A first isolation layer that penetrates the pad insulation layer and is buried in the semiconductor substrate is formed to define a first active region in the first region, and a second isolation layer that penetrates the initial high voltage gate insulation layer and is buried in the semiconductor substrate is formed to define a second active region in the second region. The pad insulation layer is then removed to expose the first active region. A low voltage gate insulation layer is formed on the exposed first active region. Accordingly, it can minimize a depth of recessed regions (dent regions) to be formed at edge regions of the first isolation layer during removal of the pad insulation layer, and it can prevent dent regions from being formed at edge regions of the second isolation layer.
摘要翻译：提供了制造具有多栅极绝缘层的半导体器件和由此制造的半导体器件的方法。该方法包括分别在半导体衬底的第一区域和第二区域上形成衬垫绝缘层和初始高电压栅极绝缘层。初始高压栅绝缘层形成为比焊垫绝缘层厚。形成穿过焊盘绝缘层并被埋在半导体衬底中的第一隔离层，以限定第一区域中的第一有源区和穿过初始高电压栅极绝缘层并被埋在半导体中的第二隔离层形成衬底以限定第二区域中的第二有源区。然后去除焊盘绝缘层以露出第一有源区。在暴露的第一有源区上形成低压栅极绝缘层。因此，能够最大限度地减少在去除焊盘绝缘层期间在第一隔离层的边缘区域形成的凹陷区域（凹陷区域）的深度，并且可以防止凹陷区域形成在第二隔离层的边缘区域。

6. 发明申请

US20050139953A1 Non-volatile memory devices including fuse covered field regions and methods of forming the same 有权
标题翻译：包括保险丝覆盖的场区域的非易失性存储器件及其形成方法
公开(公告)号：US20050139953A1
公开(公告)日：2005-06-30
申请号：US11020925
申请日：2004-12-22
申请人： Jong-Sun Sel , Sung-Nam Chang , Dae-Woong Kang , Bong-Tae Park
发明人： Jong-Sun Sel , Sung-Nam Chang , Dae-Woong Kang , Bong-Tae Park
IPC分类号： H01L21/82 , H01L21/8247 , H01L23/525 , H01L27/115 , H01L29/00
CPC分类号： H01L27/11521 , H01L23/5258 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A non-volatile device includes a semiconductor substrate having a fuse window region. At least one fuse crosses the fuse window region. Field regions are arranged outside of the fuse window region and arranged under end portions of the at least one fuse. An isolation layer is configured to isolate the field regions. A fuse insulating layer is interposed between the at least one fuse and the field regions.
摘要翻译：非易失性器件包括具有熔丝窗口区域的半导体衬底。至少有一个保险丝穿过保险丝窗口区域。场区域布置在保险丝窗口区域的外部并且布置在至少一个保险丝的端部下方。隔离层被配置为隔离场区域。保险丝绝缘层介于至少一个保险丝和场区之间。

7. 发明授权

US07132728B2 Non-volatile memory devices including fuse covered field regions 有权
标题翻译：非易失性存储器件包括保险丝覆盖的场区域
公开(公告)号：US07132728B2
公开(公告)日：2006-11-07
申请号：US11020925
申请日：2004-12-22
申请人： Jong-Sun Sel , Sung-Nam Chang , Dae-Woong Kang , Bong-Tae Park
发明人： Jong-Sun Sel , Sung-Nam Chang , Dae-Woong Kang , Bong-Tae Park
IPC分类号： H01L29/00
CPC分类号： H01L27/11521 , H01L23/5258 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A non-volatile device includes a semiconductor substrate having a fuse window region. At least one fuse crosses the fuse window region. Field regions are arranged outside of the fuse window region and arranged under end portions of the at least one fuse. An isolation layer is configured to isolate the field regions. A fuse insulating layer is interposed between the at least one fuse and the field regions.
摘要翻译：非易失性器件包括具有熔丝窗口区域的半导体衬底。至少有一个保险丝穿过保险丝窗口区域。场区域布置在保险丝窗口区域的外部并且布置在至少一个保险丝的端部下方。隔离层被配置为隔离场区域。保险丝绝缘层介于至少一个保险丝和场区之间。

8. 发明申请

US20070087496A1 NON-VOLATILE MEMORY DEVICES INCLUDING FUSE COVERED FIELD REGIONS 失效
标题翻译：非易失性存储器件，包括保险丝覆盖的领域
公开(公告)号：US20070087496A1
公开(公告)日：2007-04-19
申请号：US11538839
申请日：2006-10-05
申请人： Jong-Sun Sel , Sung-Nam Chang , Dae-Woong Kang , Bong-Tae Park
发明人： Jong-Sun Sel , Sung-Nam Chang , Dae-Woong Kang , Bong-Tae Park
IPC分类号： H01L21/8238
CPC分类号： H01L27/11521 , H01L23/5258 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A non-volatile device includes a semiconductor substrate having a fuse window region. At least one fuse crosses the fuse window region. Field regions are arranged outside of the fuse window region and arranged under end portions of the at least one fuse An isolation layer is configured to isolate the field regions. A fuse insulating layer is interposed between the at least one fuse and the field regions.
摘要翻译：非易失性器件包括具有熔丝窗口区域的半导体衬底。至少有一个保险丝穿过保险丝窗口区域。场区域布置在保险丝窗口区域的外部并且布置在至少一个熔丝的端部下方。隔离层被配置为隔离场区域。保险丝绝缘层介于至少一个保险丝和场区之间。

9. 发明授权

US07666717B2 Non-volatile memory devices including fuse covered field regions 失效
标题翻译：非易失性存储器件包括保险丝覆盖的场区域
公开(公告)号：US07666717B2
公开(公告)日：2010-02-23
申请号：US11538839
申请日：2006-10-05
申请人： Jong-Sun Sel , Sung-Nam Chang , Dae-Woong Kang , Bong-Tae Park
发明人： Jong-Sun Sel , Sung-Nam Chang , Dae-Woong Kang , Bong-Tae Park
IPC分类号： H01L21/82
CPC分类号： H01L27/11521 , H01L23/5258 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A non-volatile device includes a semiconductor substrate having a fuse window region. At least one fuse crosses the fuse window region. Field regions are arranged outside of the fuse window region and arranged under end portions of the at least one fuse. An isolation layer is configured to isolate the field regions. A fuse insulating layer is interposed between the at least one fuse and the field regions.
摘要翻译：非易失性器件包括具有熔丝窗口区域的半导体衬底。至少有一个保险丝穿过保险丝窗口区域。场区域布置在保险丝窗口区域的外部并且布置在至少一个保险丝的端部下方。隔离层被配置为隔离场区域。保险丝绝缘层介于至少一个保险丝和场区之间。

10. 发明授权

US07344944B2 Non-volatile memory device and fabricating method thereof 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07344944B2
公开(公告)日：2008-03-18
申请号：US11341073
申请日：2006-01-27
申请人： Kyu-Charn Park , Kwang-Shik Shin , Sung-Nam Chang
发明人： Kyu-Charn Park , Kwang-Shik Shin , Sung-Nam Chang
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11534 , H01L29/42328
摘要： A non-volatile memory device comprises a gate line that includes a gate dielectric layer, a bottom gate pattern, an inter-gate dielectric and a top gate pattern, which are sequentially stacked. The width of the inter-gate dielectric is narrower than that of the bottom gate pattern.
摘要翻译：非易失性存储器件包括栅极线，栅极线包括依次堆叠的栅极介电层，底部栅极图案，栅极间电介质和顶栅极图案。栅极间电介质的宽度比底栅图案的宽度窄。

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