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1. 发明授权

US08331166B2 Method and system for reading from memory cells in a memory device 有权
标题翻译：用于从存储器件中的存储单元读取的方法和系统
公开(公告)号：US08331166B2
公开(公告)日：2012-12-11
申请号：US13036030
申请日：2011-02-28
申请人： Cyrille Dray , Alexandre Ney
发明人： Cyrille Dray , Alexandre Ney
IPC分类号： G11C5/14
CPC分类号： G11C7/02 , G11C7/08 , G11C7/14 , G11C2207/002
摘要： A method and a system for reading from memory cells in a memory device are provided. In one embodiment, the memory device comprises a first plurality of data lines and a second plurality of data lines, at least one first multiplexer coupled to the first plurality of data lines and at least one low reference line, at least one second multiplexer coupled to the second plurality of data lines and at least one high reference line, at least one third multiplexer coupled to the at least one first multiplexer and the at least one second multiplexer, and a reference memory cell coupled to the at least one third multiplexer and at least one sense amplifier.
摘要翻译：提供了一种用于从存储器件中的存储单元读取的方法和系统。在一个实施例中，存储器设备包括第一多个数据线和第二多个数据线，耦合到第一多个数据线和至少一个低参考线的至少一个第一多路复用器，耦合到所述第二多个数据线和至少一个高参考线，耦合到所述至少一个第一多路复用器和所述至少一个第二多路复用器的至少一个第三多路复用器，以及耦合到所述至少一个第三多路复用器的参考存储器单元，至少一个读出放大器。

2. 发明授权

US08605479B2 Nonvolatile memory architecture 有权
标题翻译：非易失性存储器架构
公开(公告)号：US08605479B2
公开(公告)日：2013-12-10
申请号：US12911603
申请日：2010-10-25
申请人： Cyrille Dray , Alexandre Ney , Karl Hofmann
发明人： Cyrille Dray , Alexandre Ney , Karl Hofmann
IPC分类号： G11C5/06
CPC分类号： G11C11/1659 , G11C8/08 , G11C13/0002 , G11C13/0028 , G11C13/003 , G11C17/12 , G11C2213/74 , G11C2213/79
摘要： Representative implementations of memory devices have transistors between memory cells of a memory device. Memory devices may be arranged in memory arrays. The use of transistors may include alternately providing electrical isolation or current paths between pairs or groups of memory cells in a memory array.
摘要翻译：存储器件的代表性实现在存储器件的存储器单元之间具有晶体管。存储器件可以被布置在存储器阵列中。晶体管的使用可以包括交替地在存储器阵列中的存储器单元的对或组之间提供电隔离或电流路径。

3. 发明申请

US20100265758A1 Method for implementing an SRAM memory information storage device 有权
标题翻译：用于实现SRAM存储器信息存储设备的方法
公开(公告)号：US20100265758A1
公开(公告)日：2010-10-21
申请号：US12829675
申请日：2010-07-02
申请人： Cyrille Dray , Francois Jacquet , Sébastien Barasinski
发明人： Cyrille Dray , Francois Jacquet , Sébastien Barasinski
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.
摘要翻译：提供了一种用于SRAM存储器信息存储的设备和相应的实现方法。该设备由电源电压供电并且包括组合在基列中的基本单元的阵列，以及至少一个反射镜单元的至少一个反射镜列，其容易模拟基极柱中的单元的行为。该装置还包括在立柱中的最大限制单元的反射镜列中的仿真装置，用于改变反射镜列的反射镜电源电压的装置和用于复制仿真基色列中的反射镜电源电压的装置。

4. 发明申请

US20070189066A1 Magnetic Random Access Memory Array Having Bit/Word Lines for Shared Write Select and Read Operations 有权
标题翻译：具有用于共享写入选择和读取操作的位/字线的磁性随机存取存储器阵列
公开(公告)号：US20070189066A1
公开(公告)日：2007-08-16
申请号：US11738987
申请日：2007-04-23
申请人： Cyrille Dray , Christophe Frey , Jean Lasseuguette , Sebastien Barasinski , Richard Fournel
发明人： Cyrille Dray , Christophe Frey , Jean Lasseuguette , Sebastien Barasinski , Richard Fournel
IPC分类号： G11C11/14
CPC分类号： G11C11/15
摘要： A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row. A second write signal is applied to one bit line to actuate the second selection circuit/transistor for the column corresponding to that one bit line and cause a write current to flow through the second source-drain path of the actuated second selection circuit/transistor and the corresponding write bit line to write data into at least one memory element in that column.
摘要翻译：随机存取存储器阵列包括排列成行和列的随机存取存储器元件。每行的元素具有字线和写数字线，并且每列的元素具有位线和写位线。用于每行的第一选择电路/晶体管具有耦合在写入数字线中的第一源极 - 漏极通路和耦合到字线的栅极端子。用于每列的第二选择电路/晶体管具有在写位线中耦合的第二源 - 漏路径和耦合到位线的栅极端。第一写入信号被施加到一个字线以激活对应于该一条字线的行的第一选择电路/晶体管，并且使得写入电流流过被激活的第一选择电路/晶体管的第一源极 - 漏极路径，并且相应的写数字行将数据写入该行中的某些存储器元素。第二写入信号被施加到一个位线以启动与该一个位线相对应的列的第二选择电路/晶体管，并且使得写入电流流过被致动的第二选择电路/晶体管的第二源极 - 漏极通路，并且相应的写位线将数据写入该列中的至少一个存储器元件。

5. 发明授权

US06940119B2 Non-volatile programmable and electrically erasable memory with a single layer of gate material 有权
标题翻译：具有单层栅极材料的非易失性可编程和电可擦除存储器
公开(公告)号：US06940119B2
公开(公告)日：2005-09-06
申请号：US10383153
申请日：2003-03-06
申请人： Cyrille Dray , Phillipe Gendrier , Richard Fournel
发明人： Cyrille Dray , Phillipe Gendrier , Richard Fournel
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11558 , H01L29/66825 , H01L29/7883
摘要： The semiconducting memory device comprises a non-volatile programmable and electrically erasable memory cell with a single layer of grid material and comprising a floating grid transistor and a control grid, within an active semiconducting area formed in a region of the substrate and delimited by an isolation region. The layer of grid material EG, FL P2 in which the floating grid FG is made extends integrall above the active area ZA without overlapping part of the isolation region STI, and the transistor is electrically isolated from the control grid CG by PN junctions that will be reverse biased.
摘要翻译：半导体存储器件包括具有单层栅格材料的非易失性可编程和电可擦除存储器单元，并且包括浮动栅格晶体管和控制栅格，该栅极晶体管和控制栅极位于形成在衬底的区域中且由隔离区限定的有源半导体区域内地区。形成浮栅FG的栅格材料EG，FLP2层在有源区ZA之上扩展而不与隔离区STI重叠，并且晶体管通过PN结与控制栅格CG电绝缘，PN结反向偏置。

6. 发明授权

US06639838B2 Non-volatile memory architecture and integrated circuit comprising a corresponding memory 有权
标题翻译：非易失性存储器架构和包括相应存储器的集成电路
公开(公告)号：US06639838B2
公开(公告)日：2003-10-28
申请号：US10139621
申请日：2002-05-06
申请人： Richard Fournel , Sigrid Thomas , Cyrille Dray
发明人： Richard Fournel , Sigrid Thomas , Cyrille Dray
IPC分类号： G11C1606
CPC分类号： G11C16/0416
摘要： A non-volatile memory architecture with a word-based organization includes one selection transistor per word. This selection transistor is used for the selection of the word by the source of the memory cells. In this way, the selection may be done directly by the ouput signals from the address decoders using low voltage. The switching of a high voltage to the gates and the drains of the memory cells is done independently of this selection. This enables the required number of high voltage switches to be reduced.
摘要翻译：具有基于单词的组织的非易失性存储器架构包括每个字的一个选择晶体管。该选择晶体管用于由存储器单元的源选择单词。以这种方式，可以通过使用低电压的地址解码器的输出信号直接进行选择。独立于该选择，高电压切换到存储器单元的栅极和漏极。这使得能够减少所需数量的高压开关。

7. 发明授权

US06639427B2 High-voltage switching device and application to a non-volatile memory 有权
公开(公告)号：US06639427B2
公开(公告)日：2003-10-28
申请号：US09996071
申请日：2001-11-28
申请人： Cyrille Dray , Sigrid Thomas
发明人： Cyrille Dray , Sigrid Thomas
IPC分类号： H03K190185
CPC分类号： H03K19/00315 , G11C5/145 , G11C8/08 , G11C16/0441 , G11C16/30
摘要： A high voltage switching device includes a switching circuit for switching a high voltage to an output line and for providing a control signal. The high voltage switching device also includes a switching transistor connected to the switching circuit for switching a low voltage to the output line based upon the control signal. The output signal is controlled by a control circuit that sets up a control loop between the drop in the gate voltage level of the switching transistor and the voltage level of the output line that is controlled by the switching circuit.

8. 发明授权

US09478273B2 Low resistance bitline and sourceline apparatus for improving read and write operations of a nonvolatile memory 有权
标题翻译：用于改善非易失性存储器的读和写操作的低电阻位线和源极线设备
公开(公告)号：US09478273B2
公开(公告)日：2016-10-25
申请号：US14129506
申请日：2013-10-31
申请人： Cyrille Dray , Blake C. Lin , Fatih Hamzaoglu , Liqiong Wei , Yih Wang
发明人： Cyrille Dray , Blake C. Lin , Fatih Hamzaoglu , Liqiong Wei , Yih Wang
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G06F3/0604 , G06F3/0659 , G06F3/067 , G11C11/161 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1697
摘要： Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.
摘要翻译：描述了一种用于提高读写余量的装置。该装置包括：源线; 第一个位线一列电阻存储器单元，该列的每个电阻存储器单元在一端耦合到源极线并且在另一端耦合到第一位线; 以及与所述第一位线并联的第二位线，所述第二位线用于解耦所述电阻存储器单元的位线上的读取和写入操作。还描述了一种装置，其包括：源线; 有位一列电阻存储器单元，列中的每个电阻存储器单元在一端耦合到源极线并且在另一端耦合到位线; 以及耦合到位线和源极线的源极线写入驱动器，其中源极线写入驱动器沿着电阻存储器单元的列分布。

9. 发明申请

US20140340977A1 LOW POWER TRANSIENT VOLTAGE COLLAPSE APPARATUS AND METHOD FOR A MEMORY CELL 有权
标题翻译：低功耗瞬态电压放大器和存储器单元的方法
公开(公告)号：US20140340977A1
公开(公告)日：2014-11-20
申请号：US13976403
申请日：2013-05-16
申请人： Eric A. Karl , Yong-Gee Ng , Cyrille Dray
发明人： Eric A. Karl , Yong-Gee Ng , Cyrille Dray
IPC分类号： G11C5/14 , G11C11/419
CPC分类号： G11C11/419 , G11C5/147 , G11C11/413 , G11C11/414 , G11C11/417
摘要： Described is an apparatus for memory write assist which consumes low power during write assist operation. The apparatus comprises: a power supply node; a device operable to adjust voltage on the power supply node; and a feedback unit coupled to the power supply node, the feedback unit to control the device in response to a voltage level of the voltage on the power supply node.
摘要翻译：描述了一种在写入辅助操作期间消耗低功率的存储器写入辅助装置。该装置包括：电源节点; 可操作以调节所述电源节点上的电压的装置; 以及耦合到所述电源节点的反馈单元，所述反馈单元响应于所述电源节点上的电压的电压电平来控制所述装置。

10. 发明授权

US07751229B2 SRAM memory device with improved write operation and method thereof 有权
标题翻译：具有改进的写操作的SRAM存储器件及其方法
公开(公告)号：US07751229B2
公开(公告)日：2010-07-06
申请号：US11617336
申请日：2006-12-28
申请人： Cyrille Dray , Francois Jacquet , Sébastien Barasinski
发明人： Cyrille Dray , Francois Jacquet , Sébastien Barasinski
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage (VDDMMOCK) for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.
摘要翻译：提供了一种用于SRAM存储器信息存储的设备和相应的实现方法。该设备由电源电压供电并且包括组合在基列中的基本单元的阵列，以及至少一个反射镜单元的至少一个反射镜列，其容易模拟基极柱中的单元的行为。该装置还包括在立柱中的最大限制单元的反射镜中的仿真装置，用于改变反射镜列的反射镜电源电压（VDDMMOCK）的装置，以及用于将模拟的反射镜电源电压复制的装置基列。

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