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    • 1. 发明授权
    • Off-concentric polishing system design
    • 非同心抛光系统设计
    • US06432823B1
    • 2002-08-13
    • US09433681
    • 1999-11-04
    • Cuc K. HuynhPaul A. ManfrediThomas J. MartinDouglas P. NadeauYutong Wu
    • Cuc K. HuynhPaul A. ManfrediThomas J. MartinDouglas P. NadeauYutong Wu
    • H01L21302
    • B24B37/042B24B27/0076
    • An apparatus and method of planarizing objects, particularly electronic components. The off-concentric polishing system of the present invention comprises at least two polishing platens positioned adjacent each other such that the polishing portions of the platens are substantially co-planar. At least one wafer carrier is moveably mounted over the at least two platens such that a wafer may be polished by more than one platen substantially simultaneously. The platen configurations may be in a linear or non-linear configuration such that the wafer being polished is no longer centrally disposed over a single platen but is off-concentrically positioned over multiple platens. The off-concentric positioning of the wafer provides enhanced slurry distribution and endpoint detection. The present invention reduces time and cost in manufacturing electronic components by engaging several polishing conditions simultaneously without the need for sequential polishing.
    • 平面化物体,特别是电子部件的装置和方法。 本发明的非同心抛光系统包括至少两个彼此相邻定位的抛光台,使得压板的抛光部分基本上是共面的。 至少一个晶片载体可移动地安装在所述至少两个压板上,使得晶片可以被多于一个压板基本上同时抛光。 压板构造可以是线性或非线性构造,使得被抛光的晶片不再居中地设置在单个压板上,而是在多个压板上偏心地定位。 晶片的非同心定位提供了增强的浆料分布和端点检测。 本发明通过同时接合多个抛光条件来减少制造电子部件的时间和成本,而不需要顺序抛光。
    • 4. 发明授权
    • Selectively removable filler layer for BiCMOS process
    • 用于BiCMOS工艺的选择性可移除填料层
    • US06576507B1
    • 2003-06-10
    • US09712510
    • 2000-11-14
    • Kenneth A. BandyStuart D. CheneyGary L. MiloYutong Wu
    • Kenneth A. BandyStuart D. CheneyGary L. MiloYutong Wu
    • H01L218249
    • H01L21/8249
    • The present invention is intended for use on BiCMOS technology where the BJTs are formed after the FETs. A thin FET protection layer 26 is deposited on the raised and recessed regions 28 of the semiconductor substrate 10. A selectively removable filler layer 30 is then deposited on the FET protection layer 26 with a thickness to over-fill the recessed regions 28 of the gates 24 of the FETs. The selectively removable filler layer 30 is then planarized until the FET protection layer 26 on top of the gates 24 is exposed. The recessed regions 28 between the gates 24 are left substantially filled with selectively removable filler layer 30. The selectively removable filler layer 30 in the region where the BJT is formed is patterned and an opening 32 is made to allow for the depositing of layers of different materials 34, 36, 38, 40, 42, 44 used in the construction of the BJT. The layer of different materials 34, 36, 38, 40, 42, 44 are processed by methods known in the art to form polysilicon emitter 46 of the BJT. Due to selectively removable filler layer 30 creating a substantially planar surface in the recessed regions 28 of the FETs, little to none of the layers of different materials 34, 36, 38, 40, 42, 44 that are used in the construction of the BJT are deposited within the recessed regions 28. Thus, removal of the layers of different materials 34, 36, 38, 40 (40′), 42, 44 from the FET region is simplified. After removal of the layers of different materials 34, 36, 38, 40 (40′), 42, 44 from the FET region, the selectively removable filler layer 30 is removed selectively to the FET protection layer 26. The FET protection layer 26 is then removed. The recessed regions 28 between the gates 24 of the FETs are free from residual films.
    • 本发明旨在用于在FET之后形成BJT的BiCMOS技术。 薄的FET保护层26沉积在半导体衬底10的凸起和凹陷区域28上。然后,可选择地移除的填充层30沉积在FET保护层26上,其厚度足以使栅极的凹陷区域28过度填充 24个FET。 然后可选择性地移除的填充层30被平坦化,直到露出栅极24顶部的FET保护层26为止。 门24之间的凹陷区域28基本上被可选择地移除的填充层30填充。形成BJT的区域中的可选择性地移除的填充层30被图案化并且形成开口32以允许沉积不同的层 用于建造BJT的材料34,36,38,40,42,44。 通过本领域已知的方法来处理不同材料层34,36,38,40,42,44的层以形成BJT的多晶硅发射器46。 由于选择性地可移除的填充层30在FET的凹陷区域28中产生基本平坦的表面,所以在BJT的构造中使用的不同材料34,36,38,40,42,44的层几乎不下降 沉积在凹陷区域28内。因此,从FET区域去除不同材料层34,36,38,40(40'),42,44的层被简化。 在从FET区域去除不同材料34,36,38,40(40'),42,44的层之后,可选择地移除的填充层30被选择性地去除到FET保护层26.FET保护层26是 然后删除。 FET的栅极24之间的凹陷区域28没有残留的膜。