专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08959136B1 Matrix operations in an integrated circuit device 有权
标题翻译：集成电路器件中的矩阵运算
公开(公告)号：US08959136B1
公开(公告)日：2015-02-17
申请号：US13466805
申请日：2012-05-08
申请人： Colman C. Cheung , Steven Perry , Volker Mauer , Mark Jervis
发明人： Colman C. Cheung , Steven Perry , Volker Mauer , Mark Jervis
IPC分类号： G06F17/16
CPC分类号： G06F17/16 , G06F17/12
摘要： Efficient matrix operations circuitry is based on combining a matrix decomposition and a forward substitution operations to share the same processing overhead. A dual multiplier circuit selectively applies complex multiplication operations to a first and second input vectors for computing a conjugate dot product vector or a non-conjugate dot product vector. The conjugate dot product vector corresponds to the matrix decomposition operation for triangulating an input matrix to generate an element of a triangulated matrix. The non-conjugate dot product vector corresponds to a forward substitution operation for determining an element of a forward substitution vector from the triangulated matrix.
摘要翻译：有效的矩阵运算电路基于组合矩阵分解和前向替换操作以共享相同的处理开销。双乘法器电路选择性地将复乘法运算应用于第一和第二输入向量，用于计算共轭点积矢量或非共轭点乘积矢量。共轭点乘积向量对应于用于三角测量输入矩阵以生成三角矩阵的元素的矩阵分解操作。非共轭点积矢量对应于用于确定来自三角测量矩阵的正向替换矢量的元素的正向替换操作。

2. 发明授权

US08543634B1 Specialized processing block for programmable integrated circuit device 有权
标题翻译：可编程集成电路器件专用处理块
公开(公告)号：US08543634B1
公开(公告)日：2013-09-24
申请号：US13435133
申请日：2012-03-30
申请人： Lei Xu , Volker Mauer , Steven Perry
发明人： Lei Xu , Volker Mauer , Steven Perry
IPC分类号： G06F15/00
CPC分类号： G06F7/552 , G06F2207/5523
摘要： A specialized processing block such as a DSP block may be enhanced by including direct connections that allow the block output to be directly connected to either the multiplier inputs or the adder inputs of another such block. A programmable integrated circuit device may includes a plurality of such specialized processing blocks. The specialized processing block includes a multiplier having two multiplicand inputs and a product output, an adder having as one adder input the product output of the multiplier, and having a second adder input and an adder output, a direct-connect output of the adder output to a first other one of the specialized processing block, and a direct-connect input from a second other one of the specialized processing block. The direct-connect input connects a direct-connect output of that second other one of the specialized processing block to a first one of the multiplicand inputs.
摘要翻译：可以通过包括允许块输出直接连接到另一个这样的块的乘法器输入或加法器输入的直接连接来增强诸如DSP块的专门处理块。可编程集成电路设备可以包括多个这样的专用处理块。专用处理块包括具有两个被乘数输入和乘积输出的乘法器，具有一个加法器的加法器输入乘法器的乘积输出，并具有第二加法器输入和加法器输出，加法器输出的直接连接输出到专用处理块中的第一另一个，以及来自专门处理块中的另一个的直接连接输入。直接连接输入将专用处理块中另外另一个的直接连接输出连接到被乘数输入中的第一个。

3. 发明授权

US07076751B1 Chip debugging using incremental recompilation 失效
公开(公告)号：US07076751B1
公开(公告)日：2006-07-11
申请号：US10351017
申请日：2003-01-24
申请人： Gregor Nixon , Mark Jervis , Zhengjun Pan , Gihan De Silva , Steven Perry
发明人： Gregor Nixon , Mark Jervis , Zhengjun Pan , Gihan De Silva , Steven Perry
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5054 , G06F17/5077
摘要： While debugging, a user chooses an incremental recompile. Internal signals of interest are selected and output pins are optionally reserved. An incremental recompile of the compiled design includes compiling a routing from each internal signal to an output pin. The technology-mapped netlist and placing and routing information corresponding to an original compiled design are saved into a database during full compilation. During debugging, an incremental compiler retrieves this information to build the original routing netlist. The database building, logic synthesis and technology mapping stages may be skipped. New connections are added, fitted to the device, and then the final routing netlist is output into a programming output file (POF) in a form suitable for programming the PLD. The user views the internal signals at the output pins chosen. The user may iterate through this process many times in order to debug the PLD. The debugging assignments may be deleted.

4. 发明授权

US07530046B1 Chip debugging using incremental recompilation 有权
标题翻译：芯片调试使用增量重新编译
公开(公告)号：US07530046B1
公开(公告)日：2009-05-05
申请号：US11437285
申请日：2006-05-18
申请人： Gregor Nixon , Mark Jervis , Zhengjun Pan , Gihan De Silva , Steven Perry
发明人： Gregor Nixon , Mark Jervis , Zhengjun Pan , Gihan De Silva , Steven Perry
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5077
摘要： While debugging, a user chooses an incremental recompile. Internal signals of interest are selected and output pins are optionally reserved. An incremental recompile of the compiled design includes compiling a routing from each internal signal to an output pin. The technology-mapped netlist and placing and routing information corresponding to an original compiled design are saved into a database during full compilation. During debugging, an incremental compiler retrieves this information to build the original routing netlist. The database building, logic synthesis and technology mapping stages may be skipped. New connections are added, fitted to the device, and then the final routing netlist is output into a programming output file (POF) in a form suitable for programming the PLD. The user views the internal signals at the output pins chosen. The user may iterate through this process many times in order to debug the PLD. The debugging assignments may be deleted.
摘要翻译：在调试时，用户选择增量重新编译。选择感兴趣的内部信号，并选择保留输出引脚。编译设计的增量重新编译包括从每个内部信号编译到输出引脚的路由。与原始编译设计对应的技术映射网表和放置和路由信息在完整编译期间保存到数据库中。在调试期间，增量编译器检索此信息以构建原始路由网表。可能会跳过数据库构建，逻辑综合和技术映射阶段。添加新的连接，安装到设备，然后最终路由网表以适合于编程PLD的形式输出到编程输出文件（POF）中。用户查看所选输出引脚上的内部信号。为了调试PLD，用户可以多次迭代此过程。调试分配可能会被删除。

5. 发明授权

US09176912B2 Processor to message-based network interface using speculative techniques 有权
标题翻译：处理器以基于消息的网络接口采用投机技术
公开(公告)号：US09176912B2
公开(公告)日：2015-11-03
申请号：US13369727
申请日：2012-02-09
申请人： Steven Perry , Gareth Duncan
发明人： Steven Perry , Gareth Duncan
IPC分类号： G06F13/38 , H04L12/861
CPC分类号： G06F13/385 , G06F2213/3808 , H04L49/90
摘要： Methods and systems are provided for a message network interface unit (a message interface unit), coupled to a processor, that is used for allowing the processor to send messages to a hardware unit. Methods and systems are also provided for a message interface unit, coupled to a processor, that is used for allowing a processor to receive messages from a hardware unit. The message network interface unit described herein may allow for the implementation data-intensive, real time applications, which require a substantially low message response latency and a substantially high message throughput.
摘要翻译：提供了一种方法和系统，用于耦合到处理器的消息网络接口单元（消息接口单元），其用于允许处理器向硬件单元发送消息。还提供了一种方法和系统，用于耦合到处理器的消息接口单元，其用于允许处理器从硬件单元接收消息。本文描述的消息网络接口单元可以允许执行数据密集型实时应用，其需要基本上低的消息响应延迟和基本上高的消息吞吐量。

6. 发明授权

US08615543B1 Saturation and rounding in multiply-accumulate blocks 有权
标题翻译：多重积累块中的饱和度和舍入
公开(公告)号：US08615543B1
公开(公告)日：2013-12-24
申请号：US13166119
申请日：2011-06-22
申请人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
发明人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
IPC分类号： G06F7/38
CPC分类号： G06F7/49921 , G06F7/49947 , G06F7/523 , G06F7/5443
摘要： Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuitrs implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.
摘要翻译：饱和度和舍入能力在MAC块中实现，以提供乘法器的舍入和饱和输出以及使用DSP实现的加减累加电路。这些功能支持任何合适的价值表示形式，包括x.15格式。乘法器和加减累积电路内的电路实现了本发明的舍入和饱和特征。

7. 发明授权

US08402400B1 Method and apparatus for implementing a processor interface block with an electronic design automation tool 有权
标题翻译：一种用电子设计自动化工具实现处理器接口块的方法和装置
公开(公告)号：US08402400B1
公开(公告)日：2013-03-19
申请号：US12932140
申请日：2011-02-18
申请人： Steven Perry
发明人： Steven Perry
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/68
摘要： An electric design automation (EDA) tool for generating a design of a system on a field programmable gate array (FPGA) includes a library that includes a processor interface block selectable by a designer to represent a component in the design that is accessible to a processor. The EDA tool also includes a processor interface circuitry generation unit to automatically generate circuitry in the design to support the processor interface block without input from the designer.
摘要翻译：用于在现场可编程门阵列（FPGA）上生成系统设计的电气设计自动化（EDA）工具包括一个库，其包括由设计者可选择的处理器接口块，以表示处理器可访问的设计中的组件。 EDA工具还包括处理器接口电路生成单元，用于在设计中自动生成电路以支持处理器接口块，而无需设计者的输入。

8. 发明授权

US07467176B2 Saturation and rounding in multiply-accumulate blocks 有权
标题翻译：多重积累块中的饱和度和舍入
公开(公告)号：US07467176B2
公开(公告)日：2008-12-16
申请号：US10783829
申请日：2004-02-20
申请人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
发明人： Leon Zheng , Martin Langhammer , Steven Perry , Paul Metzgen , Nitin Prasad , William Hwang
IPC分类号： G06F7/38
CPC分类号： G06F7/49921 , G06F7/49947 , G06F7/523 , G06F7/5443
摘要： Saturation and rounding capabilities are implemented in multiply-accumulate (MAC) blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuits implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.
摘要翻译：饱和度和舍入能力在乘法累加（MAC）块中实现，以提供乘法器的舍入和饱和输出以及使用DSP实现的加减累加电路。这些功能支持任何合适的价值表示形式，包括x.15格式。乘法器和加减累积电路内的电路实现了本发明的舍入和饱和特征。

9. 发明授权

US07290237B2 Method for programming a mask-programmable logic device and device so programmed 有权
标题翻译：用于编程掩码可编程逻辑器件和如此编程的器件的方法
公开(公告)号：US07290237B2
公开(公告)日：2007-10-30
申请号：US10875256
申请日：2004-06-23
申请人： Steven Perry , Gregor Nixon , Larry Kong , Alasdair Scott , Andrew Hall , Lingli Wang , Chris Dettmar , Jonathan Park , Richard Price
发明人： Steven Perry , Gregor Nixon , Larry Kong , Alasdair Scott , Andrew Hall , Lingli Wang , Chris Dettmar , Jonathan Park , Richard Price
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5054
摘要： A user logic design for a mask-programmable logic device (“MPLD”) may be designed on a comparable or compatible user-programmable logic device (“UPLD”) and migrated to the MPLD, or may be designed directly on an MPLD. If the design is designed on a UPLD, the constraints of the target MPLD—i.e., differences between the devices—are taken into account so that the migration will be successful. If the design is designed directly on an MPLD, constraints of a comparable compatible UPLD are taken into account if the user indicates that the design will be migrated to the UPLD for testing. This means that when a logic design is intended to be migrated back-and-forth between a UPLD and an MPLD, only the intersection of features can be used. To facilitate migration, fixed mappings between pairs of devices may be created.
摘要翻译：可以在可比较或兼容的用户可编程逻辑器件（“UPLD”）上设计用于掩模可编程逻辑器件（“MPLD”）的用户逻辑设计并迁移到MPLD，或者可以直接设计在MPLD上。如果设计是在UPLD上设计的，则会考虑目标MPLD的约束，即设备之间的差异，以便迁移将成功。如果设计直接在MPLD上设计，则如果用户指示设计将迁移到UPLD进行测试，则会考虑可比较的兼容UPLD的约束。这意味着当逻辑设计旨在在UPLD和MPLD之间进行迁移时，只能使用特征交集。为了便于迁移，可以创建成对的设备之间的固定映射。

10. 发明授权

US07216330B1 Method and apparatus for extending the capabilities of tools used for designing systems on programmable logic devices by registering a user specified procedure 有权
标题翻译：用于通过注册用户指定的程序来扩展用于在可编程逻辑器件上设计系统的工具的能力的方法和装置
公开(公告)号：US07216330B1
公开(公告)日：2007-05-08
申请号：US10413081
申请日：2003-04-14
申请人： Steven Perry , Gregor Nixon , Alasdair Scott , Philippe Marti
发明人： Steven Perry , Gregor Nixon , Alasdair Scott , Philippe Marti
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method for designing a system on a PLD is disclosed according to a first embodiment of the present invention. A logic design is optimized. Logic circuits from the logic design are mapped to resources on the PLD. At least some of the resources are fitted onto locations on the PLD by utilizing a user-specified procedure.
摘要翻译：根据本发明的第一实施例公开了一种在PLD上设计系统的方法。优化了逻辑设计。来自逻辑设计的逻辑电路映射到PLD上的资源。至少一些资源通过使用用户指定的过程被安装到PLD上的位置上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式