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1. 发明授权

US08959136B1 Matrix operations in an integrated circuit device 有权
标题翻译：集成电路器件中的矩阵运算
公开(公告)号：US08959136B1
公开(公告)日：2015-02-17
申请号：US13466805
申请日：2012-05-08
申请人： Colman C. Cheung , Steven Perry , Volker Mauer , Mark Jervis
发明人： Colman C. Cheung , Steven Perry , Volker Mauer , Mark Jervis
IPC分类号： G06F17/16
CPC分类号： G06F17/16 , G06F17/12
摘要： Efficient matrix operations circuitry is based on combining a matrix decomposition and a forward substitution operations to share the same processing overhead. A dual multiplier circuit selectively applies complex multiplication operations to a first and second input vectors for computing a conjugate dot product vector or a non-conjugate dot product vector. The conjugate dot product vector corresponds to the matrix decomposition operation for triangulating an input matrix to generate an element of a triangulated matrix. The non-conjugate dot product vector corresponds to a forward substitution operation for determining an element of a forward substitution vector from the triangulated matrix.
摘要翻译：有效的矩阵运算电路基于组合矩阵分解和前向替换操作以共享相同的处理开销。双乘法器电路选择性地将复乘法运算应用于第一和第二输入向量，用于计算共轭点积矢量或非共轭点乘积矢量。共轭点乘积向量对应于用于三角测量输入矩阵以生成三角矩阵的元素的矩阵分解操作。非共轭点积矢量对应于用于确定来自三角测量矩阵的正向替换矢量的元素的正向替换操作。

2. 发明授权

US08942248B1 Shared control logic for multiple queues 有权
标题翻译：多个队列的共享控制逻辑
公开(公告)号：US08942248B1
公开(公告)日：2015-01-27
申请号：US12762987
申请日：2010-04-19
申请人： Colman C. Cheung
发明人： Colman C. Cheung
IPC分类号： H04L12/54 , H04L7/00 , G11C7/22
CPC分类号： H04L7/0041 , G06F5/065 , G11C7/22 , H04J3/062 , H04L47/6245 , H04L49/901
摘要： Methods, integrated circuits, and computer programs for managing a communication path carrying multiple channels are presented. Each channel includes a first-in first-out (FIFO) queue. In one method, the time difference between the start of a cycle for receiving data in a particular channel and a start of a cycle for transmitting data in the same particular channel is identified. Further, the method includes an operation for buffering arriving data in the communication path. The arriving data is buffered for an amount of time equal to the identified time difference, and the result is delayed data. FIFO registers are loaded from memory, which includes loading FIFO control and status data for a single FIFO queue, where the single FIFO queue is associated with the current channel of the produced delayed data at any time. Additionally, method includes an operation for processing contemporaneously read and write requests for the single FIFO queue using the loaded FIFO registers.
摘要翻译：提出了用于管理承载多个通道的通信路径的方法，集成电路和计算机程序。每个通道包括先进先出（FIFO）队列。在一种方法中，识别用于在特定信道中接收数据的周期的开始与用于在相同特定信道中发送数据的周期的开始之间的时间差。此外，该方法包括用于缓冲通信路径中的到达数据的操作。到达的数据被缓冲一段等于识别的时间差的时间，结果是延迟的数据。 FIFO寄存器从存储器加载，其中包括加载FIFO控制和单个FIFO队列的状态数据，其中单个FIFO队列随时与所生成的延迟数据的当前通道相关联。此外，方法包括一个操作，用于使用加载的FIFO寄存器来处理对单个FIFO队列的同时读和写请求。

3. 发明授权

US08533245B1 Multipliers with a reduced number of memory blocks 有权
标题翻译：乘数减少的内存块数
公开(公告)号：US08533245B1
公开(公告)日：2013-09-10
申请号：US12716280
申请日：2010-03-03
申请人： Colman C. Cheung
发明人： Colman C. Cheung
IPC分类号： G06F7/00 , G06F15/00
CPC分类号： G06F1/03 , G06F7/523
摘要： Techniques for implementing multipliers using memory blocks in an integrated circuit (IC) are provided. The disclosed techniques may reduce the number of memory blocks required to implement various multiplication operations. A plurality of generated products is normalized. The normalized products are scaled to generate a plurality of scaled products. Scaled products with the least root mean square (RMS) error are identified. The scaled products with the least RMS error are then stored in a plurality of memory blocks in an IC. The scaled products may have a reduced number of bits compared to the plurality of generated products that have not been normalized and scaled.
摘要翻译：提供了使用集成电路（IC）中的存储器块实现乘法器的技术。所公开的技术可以减少实现各种乘法运算所需的存储器块的数量。多个生成的产品被归一化。归一化的产品被缩放以产生多个缩放的产品。识别具有最小均方根（RMS）误差的缩放产品。然后将具有最小RMS误差的缩放产品存储在IC中的多个存储器块中。与尚未被归一化和缩放的多个生成的产品相比，缩放的产品可以具有减少的位数。

4. 发明授权

US07743272B1 Methods and apparatus for generating precise timing information using progressive block averaging 有权
标题翻译：使用渐进块平均来产生精确定时信息的方法和装置
公开(公告)号：US07743272B1
公开(公告)日：2010-06-22
申请号：US11707834
申请日：2007-02-16
申请人： Colman C. Cheung
发明人： Colman C. Cheung
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： Precise timing information produced by a block average module may be provided to signal processing circuitry. A sample period value generator may produce samples of the input data period values. A progressive block averaging computation may be applied to the generated input data period value samples. The output of the progressive block averaging computation may be used as the precise input sample rate information. The precise input sample rate information may in turn drive a signal processing application. The precision of the clock information may be increased with an increase in startup overhead.
摘要翻译：由块平均模块产生的精确定时信息可以被提供给信号处理电路。采样周期值发生器可以产生输入数据周期值的采样。逐行块平均计算可以应用于所生成的输入数据周期值样本。逐行块平均计算的输出可以用作精确的输入采样率信息。精确的输入采样率信息可以依次驱动信号处理应用。随着启动开销的增加，时钟信息的精度可能会增加。

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