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    • 8. 发明授权
    • Chip debugging using incremental recompilation and register insertion
    • 使用增量重新编译和寄存器插入进行芯片调试
    • US07206967B1
    • 2007-04-17
    • US10774731
    • 2004-02-09
    • Philippe MartiMark JervisGregor Nixon
    • Philippe MartiMark JervisGregor Nixon
    • G06F11/00
    • G01R31/318364
    • While debugging, a user chooses an incremental recompile. Internal signals of interest and output pins are selected, and a number of additional registers are chosen to insert in the path of each internal signal. A clock is selected for the registers. An incremental recompile of the compiled design compiles a routing from each internal signal to an output pin via the added registers. The database building and logic synthesis stages are skipped. The post-fitting logical netlist and routing netlist are retrieved. The new registers are created and the internal signal is connected to the output pin atom in the logical netlist. The fitter places and routes the connections to create a new routing netlist and then the new routing netlist is output into a programming output file (POF) in a form suitable for programming the PLD. The original routing netlist is undisturbed. The user views the internal signals at the output pins chosen. The user may iterate through this process many times in order to debug the PLD. The debugging assignments may be deleted.
    • 在调试时,用户选择增量重新编译。 选择感兴趣的内部信号和输出引脚,并且选择多个附加寄存器来插入每个内部信号的路径。 为寄存器选择一个时钟。 编译设计的增量重新编译通过添加的寄存器编译从每个内部信号到输出引脚的路由。 数据库构建和逻辑综合阶段被跳过。 检索后拟合逻辑网表和路由网表。 创建新的寄存器,并将内部信号连接到逻辑网表中的输出引脚原子。 装配者放置和路由连接以创建新的路由网表,然后将新的路由网表以适于编程PLD的形式输出到编程输出文件(POF)中。 原始路由网表不受干扰。 用户查看所选输出引脚上的内部信号。 为了调试PLD,用户可以多次迭代此过程。 调试分配可能会被删除。