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1. 发明授权

US6070262A Reconfigurable I/O DRAM 失效
标题翻译：可重配置I / O DRAM
公开(公告)号：US6070262A
公开(公告)日：2000-05-30
申请号：US833367
申请日：1997-04-04
申请人： Mark W. Kellogg , Timothy J. Dell , Erik L. Hedberg , Claude L. Bertin
发明人： Mark W. Kellogg , Timothy J. Dell , Erik L. Hedberg , Claude L. Bertin
IPC分类号： G06F11/10 , G06F12/00 , G11C7/10 , G11C29/00
CPC分类号： G11C7/1057 , G06F11/1044 , G11C7/1006 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C7/1084
摘要： A Dynamic Random Access Memory (DRAM) configurable by eight (.times.8) or by nine (.times.9). The DRAM has nine Data Input/Outputs (I/Os). The memory array is divided into two or more sub-arrays, with sub-array cells arranged in addressable rows and columns. When the DRAM is configured .times.8, one I/O is held in its high impedance state; one ninth of the DRAM's data path (between the array and the ninth I/O) is ignored; and, the entire array address space is available for data storage through eight I/Os. When the DRAM is configured .times.9, all nine I/Os are active; the DRAM I/O path is reconfigured with part of the array providing the ninth bit through the ninth I/O; and the array address space reduced by one-eighth. All nine bits may be from a common sub-array. Alternatively, sub-arrays may be paired so that when the DRAM is configured .times.9, eight bits are accessed in seven-eighths of one sub-array, with the ninth bit being accessed in one eighth of the other sub-array of the pair.
摘要翻译：动态随机存取存储器（DRAM）可由八（x8）或九（x9）配置。 DRAM具有9个数据输入/输出（I / O）。存储器阵列被分成两个或更多个子阵列，子阵列单元被布置成可寻址的行和列。当DRAM被配置为x8时，一个I / O保持在其高阻抗状态; DRAM的数据路径（阵列和第九个I / O之间）的九分之一被忽略; 并且整个阵列地址空间可用于通过八个I / O进行数据存储。当DRAM配置为x9时，所有9个I / O都有效; DRAM I / O路径被配置为通过第九个I / O提供第九位的阵列的一部分; 并且阵列地址空间减少了八分之一。所有9位可能来自公共子阵列。或者，子阵列可以配对，使得当DRAM被配置为x9时，在一个子阵列的七分之八中访问八个比特，其中第九比特在该对的另一个子阵列的八分之一中被访问。

2. 发明授权

US06178517B1 High bandwidth DRAM with low operating power modes 失效
标题翻译：具有低工作功率模式的高带宽DRAM
公开(公告)号：US06178517B1
公开(公告)日：2001-01-23
申请号：US09121933
申请日：1998-07-24
申请人： Claude L. Bertin , Timothy J. Dell , Erik L. Hedberg , Mark W. Kellogg
发明人： Claude L. Bertin , Timothy J. Dell , Erik L. Hedberg , Mark W. Kellogg
IPC分类号： G06F1200
CPC分类号： G06F13/1684 , Y02D10/14
摘要： A high bandwidth DRAM is provided with two separate bus networks connecting the DRAM to a processor. One bus network is a high speed (e.g., 500 MHZ) 8:1 or 16:1 multiplexed I/O bus and the second is a slower (e.g., 64-bit) bus. The high-speed bus is used for example for graphic intensive applications which require fast access to large numbers of bits in the DRAM memory array. This of course results in higher power requirements. Since, not all applications require such large amounts of data to be transferred between the DRAM and the processor, the slower bus is provided for these less demanding applications such as word processors, spreadsheets, and the like. The slower bus requires less power to operate and therefore results in a power saving mode which, among other things, facilitates longer battery life.
摘要翻译：高带宽DRAM具有将DRAM连接到处理器的两个单独的总线网络。一个总线网络是高速（例如，500MHz）8：1或16：1多路复用I / O总线，第二个是较慢（例如，64位）总线。例如，高速总线用于需要快速访问DRAM存储器阵列中大量位的图形密集型应用。这当然会导致更高的功率需求。由于并非所有应用都需要在DRAM和处理器之间传输大量数据，所以为这些不太要求苛刻的应用程序提供较慢的总线，例如文字处理器，电子表格等。较慢的总线需要更少的功率来进行操作，因此导致省电模式，其中尤其有助于延长电池寿命。

3. 发明授权

US5896404A Programmable burst length DRAM 失效
标题翻译：可编程突发长度DRAM
公开(公告)号：US5896404A
公开(公告)日：1999-04-20
申请号：US833371
申请日：1997-04-04
申请人： Mark W. Kellogg , Timothy J. Dell , Erik L. Hedberg , Claude L. Bertin
发明人： Mark W. Kellogg , Timothy J. Dell , Erik L. Hedberg , Claude L. Bertin
IPC分类号： G06F12/16 , G06F11/10 , G11C7/10 , G11C11/401 , G11C29/42 , G11C29/00
CPC分类号： G06F11/1008 , G11C7/1018 , G06F11/1052
摘要： A Dynamic Random Access Memory (DRAM) with a burst length programmable as eight (8) or nine (9) bytes. The DRAM array is divided into two or more sub-arrays, with sub-array cells arranged in addressable rows and columns. When the DRAM is programmed in Normal mode, the burst length is 8 and the entire array address space is available for data storage. When the DRAM is programmed for error checking (ECC mode), the burst length is nine and the array is reconfigured with part of the array providing the ninth byte. The DRAM's address space is reduced by one-eighth in ECC mode. Preferably, all nine locations are in the same page, with each page being divided into eight equal portions. In Normal mode all eight equal portions are data storage; and, in ECC mode, seven-eighths of the page is data storage, the remaining one eighth being assigned to check bit storage.
摘要翻译：具有可编程为八（8）或九（9）字节的突发长度的动态随机存取存储器（DRAM）。 DRAM阵列分为两个或更多个子阵列，子阵列单元以可寻址的行和列排列。当DRAM在正常模式下编程时，突发长度为8，整个阵列地址空间可用于数据存储。当DRAM被编程用于错误检查（ECC模式）时，突发长度为9，并且阵列被配置为提供第九个字节的阵列的一部分。在ECC模式下，DRAM的地址空间减少了八分之一。优选地，所有九个位置在同一页面中，每个页面被分成八个相等的部分。在正常模式下，所有八个相等的部分都是数据存储; 并且在ECC模式中，页面的七分之一是数据存储，剩下的八分之一被分配给校验位存储。

4. 发明授权

US06567950B1 Dynamically replacing a failed chip 失效
标题翻译：动态更换故障芯片
公开(公告)号：US06567950B1
公开(公告)日：2003-05-20
申请号：US09302917
申请日：1999-04-30
申请人： Claude L. Bertin , Timothy J. Dell , Erik L. Hedberg
发明人： Claude L. Bertin , Timothy J. Dell , Erik L. Hedberg
IPC分类号： G11C2900
CPC分类号： G11C29/70 , G11C29/838
摘要： An improved chip sparing system and method of operation are provided in which a failed chip is detected even if there are multiple errors on a single chip and one or more spare chips are provided within the system; and in which spare chips or space chip I/Os are dynamically inserted into the system upon detection of a failed chip or chip I/O without the necessity of shutting down and rebooting the system or even without the necessity of re-initializing the memory.
摘要翻译：提供了一种改进的芯片保存系统和操作方法，其中即使在单个芯片上存在多个错误并且在系统内提供一个或多个备用芯片，也检测到故障芯片; 并且在检测到故障的芯片或芯片I / O时，备用芯片或空芯片I / O被动态地插入到系统中，而不需要关闭和重新启动系统，或者甚至不需要重新初始化存储器。

5. 发明授权

US6065093A High bandwidth narrow I/O memory device with command stacking 失效
标题翻译：带带命令的高带宽窄I / O存储器
公开(公告)号：US6065093A
公开(公告)日：2000-05-16
申请号：US79572
申请日：1998-05-15
申请人： Timothy J. Dell , Erik L. Hedberg , Mark W. Kellogg
发明人： Timothy J. Dell , Erik L. Hedberg , Mark W. Kellogg
IPC分类号： G11C11/407 , G11C7/10 , G11C7/22 , G11C11/401 , G06F13/00
CPC分类号： G11C7/1072 , G11C7/22
摘要： A memory device is provided which stacks commands and internally executes each command at the appropriate time, thereby ensuring contiguous data I/O. The memory device is capable of initiating memory accesses either immediately or "stacking" the command along with a "clock count". The clock count defines the number of clock cycles that must occur prior to execution of the command by the memory device. The memory device initiates memory accesses either immediately, or delayed by the number of clocks defined by the clock count for that command. The memory device operates as a slave to the memory controller and therefore has no ability to execute instructions at a time other than that defined by the memory controller.
摘要翻译：提供一种存储器件，其堆叠命令并在适当的时间内部执行每个命令，从而确保连续的数据I / O。存储器件能够立即启动存储器访问或者“堆叠”命令以及“时钟计数”。时钟计数定义在存储器件执行命令之前必须发生的时钟周期数。存储器设备立即启动存储器访问，或延迟由该命令的时钟计数定义的时钟数。存储器件作为存储器控制器的从设备操作，因此在与由存储器控制器定义的时间以外的时间不具有执行指令的能力。

6. 发明授权

US06327664B1 Power management on a memory card having a signal processing element 失效
标题翻译：对具有信号处理元件的存储卡进行电源管理
公开(公告)号：US06327664B1
公开(公告)日：2001-12-04
申请号：US09302916
申请日：1999-04-30
申请人： Timothy J. Dell , Bruce G. Hazelzet , Mark W. Kellogg , Christopher P. Miller
发明人： Timothy J. Dell , Bruce G. Hazelzet , Mark W. Kellogg , Christopher P. Miller
IPC分类号： G06F132
CPC分类号： G06F1/3275 , G06F1/3203 , Y02D10/13 , Y02D10/14
摘要： An improved memory module and its use in a computer system is provided. The module includes a DSP first and second individually addressable banks of memory chips. The first bank is configured to function principally under the control of the signal processing element and the second bank is configured to function principally under the control of a system memory controller, although all the portions of each of the memory banks is addressable by both the signal processing element and the system memory controller. Both banks of memory chips can be placed in at least one higher power state and at least one lower power state by either the system memory controller or the DSP. The activity of each bank is sensed while in the higher power state, and the condition of each of the banks is sensed with respect to any activity during operation of the memory bank at the higher power state. The power state of each bank can be changed by either the signal processing element or the system memory controller responsive to preselected conditions of each bank. Each memory bank is returned to a predetermined known condition when changing from a lower power state to a higher power state. This is especially important when the memory bank assigned to the system controller is placed in another state by the DSP.
摘要翻译：提供了一种改进的存储器模块及其在计算机系统中的应用。该模块包括DSP第一和第二可单独寻址的存储器芯片组。第一组被配置为主要在信号处理元件的控制下起作用，并且第二存储体被配置为主要在系统存储器控制器的控制下起作用，尽管每个存储体的所有部分都可以由信号处理元件和系统存储器控制器。两个存储芯片组可以通过系统存储器控制器或DSP被置于至少一个较高功率状态和至少一个较低功率状态。在较高功率状态下感测每个存储体的活动，并且相对于在较高功率状态的存储体的操作期间的任何活动来感测每个存储体的状况。响应于每个银行的预选条件，可以通过信号处理元件或系统存储器控制器改变每个存储体的电源状态。当从较低功率状态改变到较高功率状态时，每个存储体返回到预定的已知状态。当分配给系统控制器的存储体被DSP置于另一状态时，这尤其重要。

7. 发明授权

US07539800B2 System, method and storage medium for providing segment level sparing 有权
标题翻译：系统，方法和存储介质，用于提供段级备份
公开(公告)号：US07539800B2
公开(公告)日：2009-05-26
申请号：US10903188
申请日：2004-07-30
申请人： Timothy J. Dell , Frank D. Ferraiolo , Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
发明人： Timothy J. Dell , Frank D. Ferraiolo , Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
IPC分类号： G06F13/00 , G06F11/00
CPC分类号： G06F11/201 , G06F11/104
摘要： A memory subsystem that includes segment level sparing. The memory subsystem includes a cascaded interconnect system with segment level sparing. The cascaded interconnect system includes two or more memory assemblies and a memory bus. The memory bus includes multiple segments and the memory assemblies are interconnected via the memory bus.
摘要翻译：一个内存子系统，包括段级备份。存储器子系统包括具有段级保护的级联互连系统。级联互连系统包括两个或多个存储器组件和存储器总线。存储器总线包括多个段，并且存储器组件经由存储器总线互连。

8. 发明授权

US06467018B1 Method and apparatus for addressing individual banks of DRAMs on a memory card 有权
标题翻译：用于寻址存储卡上DRAM的各个存储体的方法和装置
公开(公告)号：US06467018B1
公开(公告)日：2002-10-15
申请号：US09225536
申请日：1999-01-04
申请人： Timothy J. Dell , Mark W. Kellogg
发明人： Timothy J. Dell , Mark W. Kellogg
IPC分类号： G06F1200
CPC分类号： G06F13/1647
摘要： An improved memory card and its use in a computer system is provided. The computer system has a system bus which provides requests from a CPU to a memory controller, which then provides signals to the memory card or module or a memory bus. The memory card is provided with first and second banks of DRAMs, a memory card bus and a DSP. Logic circuitry including a memory card data bus controller provides communication of the DSP with the banks of DRAM chips. Logic circuitry is also provided which can selectively connect the DSP to either the first or second bank of DRAMs and selectively connect the memory bus with the other bank of DRAMs or with both banks of DRAMs. Hence when the CPU is accessing one bank of DRAMS the DSP can access the other bank of DRAMs thus allowing the DSP to function utilizing the bank of DRAMs not being accessed by the memory bus to service the CPU or some I/O device.
摘要翻译：提供了一种改进的存储卡及其在计算机系统中的应用。计算机系统具有系统总线，其提供从CPU到存储器控制器的请求，然后存储器控制器向存储卡或模块或存储器总线提供信号。存储卡设置有第一和第二组DRAM，存储卡总线和DSP。包括存储卡数据总线控制器的逻辑电路提供DSP与DRAM芯片组的通信。还提供了逻辑电路，其可以选择性地将DSP连接到第一或第二组DRAM并且选择性地将存储器总线与另一组DRAM或两组DRAM连接。因此，当CPU正在访问一组DRAMS时，DSP可以访问另一组DRAM，从而允许DSP利用由存储器总线访问的DRAM组来对CPU或一些I / O设备进行服务。

9. 发明授权

US06349390B1 On-board scrubbing of soft errors memory module 有权
标题翻译：车载擦洗软错误内存模块
公开(公告)号：US06349390B1
公开(公告)日：2002-02-19
申请号：US09224990
申请日：1999-01-04
申请人： Timothy J. Dell , Bruce G. Hazelzet , Mark W. Kellogg
发明人： Timothy J. Dell , Bruce G. Hazelzet , Mark W. Kellogg
IPC分类号： G06F1110
CPC分类号： G06F11/106
摘要： A memory module for attachment to a computer system having a memory bus and a method of using the memory module for error correction by scrubbing soft errors on-board the module is provided. The module includes a printed circuit card with memory storage chips on the card to store data bits and associated ECC check bits. Tabs are provided on the circuit card to couple the card to the memory bus of the computer system. Logic circuitry selectively operatively connects and disconnects the memory chip and the memory bus. A signal processor is connected in circuit relationship with the memory chips. The logic circuitry selectively permits the signal processor to read the stored data bits and associated check bits from the memory chips, recalculate the check bits from the read stored data bits, compare the recalculated check bits with the stored check bits, correct all at least one bit errors in the store data bits and stored associated check bits and re-store the correct data bits and associated check bits in the memory chips. When the memory chips and the memory bus are disconnected, single bit soft errors occurring during storage of the data bits and check bits are corrected periodically before the data is read from the memory chips to the data bus on a read operation.
摘要翻译：提供了一种用于附接到具有存储器总线的计算机系统的存储器模块，以及通过擦除模块上的软错误来使用存储器模块进行纠错的方法。该模块包括在卡上具有存储器存储芯片的印刷电路卡，以存储数据位和相关联的ECC校验位。在电路卡上提供标签以将该卡耦合到计算机系统的存储器总线。逻辑电路选择性地操作地连接和断开存储器芯片和存储器总线。信号处理器与存储器芯片以电路关系连接。逻辑电路选择性地允许信号处理器从存储器芯片读取存储的数据位和相关的校验位，从读取的存储的数据位重新计算校验位，将重新计算的校验位与存储的校验位进行比较，校正所有至少一个存储数据位和存储的相关检查位中的位错误并且将存储器芯片中的正确数据位和相关联的校验位重新存储。当存储器芯片和存储器总线断开时，在存储数据位和校验位期间发生的单位软错误在数据从读存储器芯片读取到数据总线之前被周期性地校正。

10. 发明授权

US06347367B1 Data bus structure for use with multiple memory storage and driver receiver technologies and a method of operating such structures 失效
标题翻译：用于多存储器存储和驱动器接收器技术的数据总线结构以及操作这种结构的方法
公开(公告)号：US06347367B1
公开(公告)日：2002-02-12
申请号：US09240647
申请日：1999-01-29
申请人： Timothy J. Dell , Steven A. Grundon , Mark W. Kellogg
发明人： Timothy J. Dell , Steven A. Grundon , Mark W. Kellogg
IPC分类号： G06F1200
CPC分类号： G06F13/4239
摘要： The disclosed invention relates generally to electronic data storage systems that access data storage memory modules via a data bus comprised of multiple data query lines and, more particularly, to an electronic data storage system provided with a data bus that can be selectively provided with terminations thereby permitting the data storage memory to use either modules that require that the data query lines be open-ended, i.e., without terminations or modules that require that the data bus be terminated and to a method for operating such a system. The present invention is particularly directed to a single memory system that can accommodate either 3.3V DIMMs or DDR DIMMs. This is especially accomplished by providing the processor circuit, used in memory storage systems, with both (3.3V) receiver/driver circuits and double rate (DDR) receiver/driver circuits, with an identification circuit for identifying the type of DIMMs in the memory system coupled thereto, a selection circuit for selecting the receiver/driver circuits required to access the identified DIMMs, and switch for adding or removing terminations to the data query lines, interconnecting the selected receiver driver circuits to identified DIMMS. Thus the invention provides a memory system that can access either 3.3V DIMMs or DDR DIMMs and automatically provide the proper terminations on the data bus used to access the DIMMs.
摘要翻译：所公开的发明一般涉及经由包括多条数据查询线的数据总线访问数据存储存储器模块的电子数据存储系统，更具体地说，涉及一种具有数据总线的电子数据存储系统，该数据总线可选择性地提供终端允许数据存储存储器使用要求数据查询行是开放式的模块，即，不需要终止数据总线的终端或模块以及用于操作这样的系统的方法。本发明特别涉及可容纳3.3V DIMM或DDR DIMM的单个存储器系统。这通过在存储器存储系统中使用处理器电路（3.3V）接收器/驱动器电路和双速率（DDR）接收器/驱动器电路）来实现，其中识别电路用于识别存储器中的DIMM的类型耦合到其上的系统，用于选择访问所识别的DIMM所需的接收机/驱动器电路的选择电路，以及用于向数据查询线路添加或移除终端的切换，将所选择的接收机驱动器电路互连到所识别的DIMMS。因此，本发明提供了一种存储系统，其可以访问3.3V DIMM或DDR DIMM，并且在用于访问DIMM的数据总线上自动提供适当的终端。

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