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    • 3. 发明授权
      US08185786B2 Error recovery within processing stages of an integrated circuit 有权
    • Error recovery within processing stages of an integrated circuit
    • 集成电路处理阶段内的错误恢复
    • US08185786B2
    • 2012-05-22
    • US12923911
    • 2010-10-13
    • Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge
    • Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge
    • G06F11/00
    • G06F11/1695 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
    • An integrated circuit includes a plurality of processing stages each including processing logic, a non-delayed signal-capture element, a delayed signal-capture element and a comparator. The non-delayed signal-capture element captures an output from the processing logic at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element also captures a value from the processing logic. An error detection circuit and error correction circuit detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator. The comparator compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
    • 集成电路包括多个处理级，每个处理级包括处理逻辑，非延迟信号捕获元件，延迟信号捕获元件和比较器。 非延迟信号捕获元件在非延迟捕获时间捕获来自处理逻辑的输出。 在稍后的延迟捕获时间，延迟信号捕获元件还捕获来自处理逻辑的值。 误差检测电路和误差校正电路检测并校正延迟值中的随机误差，并向比较器提供经错误检测的延迟值。 比较器比较错误检查的延迟值和非延迟值，如果它们不相等，则表示非延迟值被捕获太早，应由错误检查的延迟值替换。 非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播 在重新启动时钟之前通过后续的处理逻辑。 调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US07337356B2 Systematic and random error detection and recovery within processing stages of an integrated circuit 有权
    • Systematic and random error detection and recovery within processing stages of an integrated circuit
    • 在集成电路的处理阶段内的系统和随机的错误检测和恢复
    • US07337356B2
    • 2008-02-26
    • US10896997
    • 2004-07-23
    • Trevor Nigel Mudge , Todd Michael Austin , David Theodore Blaauw , Krisztian Flautner
    • Trevor Nigel Mudge , Todd Michael Austin , David Theodore Blaauw , Krisztian Flautner
    • G06F11/00
    • G06F11/1695 , G06F9/3861 , G06F9/3869 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
    • An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
    • 集成电路包括多个处理级，每个处理级包括处理逻辑1014，非延迟信号捕获元件1016，延迟信号捕获元件1018和比较器1024。 非延迟信号捕获元件1016在非延迟捕获时间捕获来自处理逻辑1014的输出。 在稍后延迟的捕获时间，延迟信号捕获元件1018还从处理逻辑1014捕获一个值。 误差检测电路1026和误差校正电路1028检测并校正延迟值中的随机误差，并将错误检测的延迟值提供给比较器1024。 比较器1024比较错误检查的延迟值和非延迟值，如果它们不相等，则表示非延迟值被捕获得太早，应该被错误检查的延迟值替换。 非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播 在重新启动时钟之前通过后续的处理逻辑。 调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US4924467A System for checking duplicate logic using complementary residue codes to achieve high error coverage with a minimum of interface signals 失效
    • System for checking duplicate logic using complementary residue codes to achieve high error coverage with a minimum of interface signals
    • 使用互补残留代码检查重复逻辑的系统，以最少的接口信号实现高错误覆盖
    • US4924467A
    • 1990-05-08
    • US235425
    • 1988-08-24
    • Peter B. Criswell
    • Peter B. Criswell
    • G06F11/10 , G06F11/16
    • G06F11/1608 , G06F11/104
    • A system for detecting and isolating fault conditions occurring within a digital electronic system. The digital electronic system includes a first digital logic array for generating digital outputs in response to a set of digital signal inputs applied to it. The digital logic array is replicated and the second array is configured to receive the same inputs as the first. The first and second arrays are made to operate in synchrony so as to normally produce identical outputs in the absence of fault conditions occurring either in the first or second array or in the inputs applied to them. The digital outputs from the first array are applied to first and second residue code generators having different modulii. Likewise, the outputs from the second arry are applied to third and fourth residue code generators which are identical in make-up to the first and second residue code generators. The residue codes developed by the first and third generators are applied to a first comparator while the codes developed by the second and fourth generators are applied to a second comparator. The comparator outputs are applied through combinatorial logic so as to provide an output signal indicative of a fault condition when either the first or second comparator produces an output indicative of inequality between respective residue codes.
    • 一种用于检测和隔离数字电子系统内出现的故障状况的系统。 数字电子系统包括用于响应于应用于其的一组数字信号输入而产生数字输出的第一数字逻辑阵列。 数字逻辑阵列被复制，第二阵列被配置为接收与第一阵列相同的输入。 使第一和第二阵列同步操作，以便在没有发生在第一或第二阵列中或在施加到它们的输入中的故障条件下通常产生相同的输出。 来自第一阵列的数字输出被应用于具有不同模块的第一和第二残差码发生器。 类似地，来自第二arry的输出被应用于第三和第四残差码发生器，它们与第一和第二残留码发生器相同。 由第一和第三发生器开发的残留代码被应用于第一比较器，而由第二和第四发生器开发的代码被施加到第二比较器。 比较器输出通过组合逻辑施加，以便当第一或第二比较器产生指示各残留代码之间的不等式的输出时，提供指示故障状况的输出信号。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 9. 发明授权
      US3980874A Binary to modulo M translation 失效
    • Binary to modulo M translation
    • 二进制到模M翻译
    • US3980874A
    • 1976-09-14
    • US576002
    • 1975-05-09
    • Chandrakant R. Vora
    • Chandrakant R. Vora
    • G06F7/72 , G06F11/10 , H03M7/18 , G06F7/385 , H03K13/24
    • G06F11/104 , H03M7/18
    • Modulo M translation is performed on a large binary number of n bits by grouping the binary number in contiguous sets of approximately K bits each, storing the modulo M residues for each K bit set in an individually associated pre-stored ROM, reading the modulo M residues for a particular K bit segment of a binary number out of the ROMs, and performing modulo M addition on the read-out residues. Thus, modulo M translation of a positive number is accomplished in n/k modulo M additions and a table look-up, with the look-up table being stored in n/k ROMs. A subsequent modulo M subtraction is performed if the binary number is negative.
    • 通过将二进制数分组在大约K个比特的连续集合中，对大量二进制数n位执行模M翻译，将每个K位设置的模M残差存储在单独关联的预存ROM中，读取模M 对于ROM中的二进制数的特定K位段的残差，以及对读出的残差执行模M加法。 因此，正数的模M转换在n / k模M加法和表查找中完成，其中查找表存储在n / k个ROM中。 如果二进制数为负，则执行后续的模M减法。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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