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1. 发明授权

US6070262A Reconfigurable I/O DRAM 失效
标题翻译：可重配置I / O DRAM
公开(公告)号：US6070262A
公开(公告)日：2000-05-30
申请号：US833367
申请日：1997-04-04
申请人： Mark W. Kellogg , Timothy J. Dell , Erik L. Hedberg , Claude L. Bertin
发明人： Mark W. Kellogg , Timothy J. Dell , Erik L. Hedberg , Claude L. Bertin
IPC分类号： G06F11/10 , G06F12/00 , G11C7/10 , G11C29/00
CPC分类号： G11C7/1057 , G06F11/1044 , G11C7/1006 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C7/1084
摘要： A Dynamic Random Access Memory (DRAM) configurable by eight (.times.8) or by nine (.times.9). The DRAM has nine Data Input/Outputs (I/Os). The memory array is divided into two or more sub-arrays, with sub-array cells arranged in addressable rows and columns. When the DRAM is configured .times.8, one I/O is held in its high impedance state; one ninth of the DRAM's data path (between the array and the ninth I/O) is ignored; and, the entire array address space is available for data storage through eight I/Os. When the DRAM is configured .times.9, all nine I/Os are active; the DRAM I/O path is reconfigured with part of the array providing the ninth bit through the ninth I/O; and the array address space reduced by one-eighth. All nine bits may be from a common sub-array. Alternatively, sub-arrays may be paired so that when the DRAM is configured .times.9, eight bits are accessed in seven-eighths of one sub-array, with the ninth bit being accessed in one eighth of the other sub-array of the pair.
摘要翻译：动态随机存取存储器（DRAM）可由八（x8）或九（x9）配置。 DRAM具有9个数据输入/输出（I / O）。存储器阵列被分成两个或更多个子阵列，子阵列单元被布置成可寻址的行和列。当DRAM被配置为x8时，一个I / O保持在其高阻抗状态; DRAM的数据路径（阵列和第九个I / O之间）的九分之一被忽略; 并且整个阵列地址空间可用于通过八个I / O进行数据存储。当DRAM配置为x9时，所有9个I / O都有效; DRAM I / O路径被配置为通过第九个I / O提供第九位的阵列的一部分; 并且阵列地址空间减少了八分之一。所有9位可能来自公共子阵列。或者，子阵列可以配对，使得当DRAM被配置为x9时，在一个子阵列的七分之八中访问八个比特，其中第九比特在该对的另一个子阵列的八分之一中被访问。

2. 发明授权

US06178517B1 High bandwidth DRAM with low operating power modes 失效
标题翻译：具有低工作功率模式的高带宽DRAM
公开(公告)号：US06178517B1
公开(公告)日：2001-01-23
申请号：US09121933
申请日：1998-07-24
申请人： Claude L. Bertin , Timothy J. Dell , Erik L. Hedberg , Mark W. Kellogg
发明人： Claude L. Bertin , Timothy J. Dell , Erik L. Hedberg , Mark W. Kellogg
IPC分类号： G06F1200
CPC分类号： G06F13/1684 , Y02D10/14
摘要： A high bandwidth DRAM is provided with two separate bus networks connecting the DRAM to a processor. One bus network is a high speed (e.g., 500 MHZ) 8:1 or 16:1 multiplexed I/O bus and the second is a slower (e.g., 64-bit) bus. The high-speed bus is used for example for graphic intensive applications which require fast access to large numbers of bits in the DRAM memory array. This of course results in higher power requirements. Since, not all applications require such large amounts of data to be transferred between the DRAM and the processor, the slower bus is provided for these less demanding applications such as word processors, spreadsheets, and the like. The slower bus requires less power to operate and therefore results in a power saving mode which, among other things, facilitates longer battery life.
摘要翻译：高带宽DRAM具有将DRAM连接到处理器的两个单独的总线网络。一个总线网络是高速（例如，500MHz）8：1或16：1多路复用I / O总线，第二个是较慢（例如，64位）总线。例如，高速总线用于需要快速访问DRAM存储器阵列中大量位的图形密集型应用。这当然会导致更高的功率需求。由于并非所有应用都需要在DRAM和处理器之间传输大量数据，所以为这些不太要求苛刻的应用程序提供较慢的总线，例如文字处理器，电子表格等。较慢的总线需要更少的功率来进行操作，因此导致省电模式，其中尤其有助于延长电池寿命。

3. 发明授权

US5896404A Programmable burst length DRAM 失效
标题翻译：可编程突发长度DRAM
公开(公告)号：US5896404A
公开(公告)日：1999-04-20
申请号：US833371
申请日：1997-04-04
申请人： Mark W. Kellogg , Timothy J. Dell , Erik L. Hedberg , Claude L. Bertin
发明人： Mark W. Kellogg , Timothy J. Dell , Erik L. Hedberg , Claude L. Bertin
IPC分类号： G06F12/16 , G06F11/10 , G11C7/10 , G11C11/401 , G11C29/42 , G11C29/00
CPC分类号： G06F11/1008 , G11C7/1018 , G06F11/1052
摘要： A Dynamic Random Access Memory (DRAM) with a burst length programmable as eight (8) or nine (9) bytes. The DRAM array is divided into two or more sub-arrays, with sub-array cells arranged in addressable rows and columns. When the DRAM is programmed in Normal mode, the burst length is 8 and the entire array address space is available for data storage. When the DRAM is programmed for error checking (ECC mode), the burst length is nine and the array is reconfigured with part of the array providing the ninth byte. The DRAM's address space is reduced by one-eighth in ECC mode. Preferably, all nine locations are in the same page, with each page being divided into eight equal portions. In Normal mode all eight equal portions are data storage; and, in ECC mode, seven-eighths of the page is data storage, the remaining one eighth being assigned to check bit storage.
摘要翻译：具有可编程为八（8）或九（9）字节的突发长度的动态随机存取存储器（DRAM）。 DRAM阵列分为两个或更多个子阵列，子阵列单元以可寻址的行和列排列。当DRAM在正常模式下编程时，突发长度为8，整个阵列地址空间可用于数据存储。当DRAM被编程用于错误检查（ECC模式）时，突发长度为9，并且阵列被配置为提供第九个字节的阵列的一部分。在ECC模式下，DRAM的地址空间减少了八分之一。优选地，所有九个位置在同一页面中，每个页面被分成八个相等的部分。在正常模式下，所有八个相等的部分都是数据存储; 并且在ECC模式中，页面的七分之一是数据存储，剩下的八分之一被分配给校验位存储。

4. 发明授权

US6065093A High bandwidth narrow I/O memory device with command stacking 失效
标题翻译：带带命令的高带宽窄I / O存储器
公开(公告)号：US6065093A
公开(公告)日：2000-05-16
申请号：US79572
申请日：1998-05-15
申请人： Timothy J. Dell , Erik L. Hedberg , Mark W. Kellogg
发明人： Timothy J. Dell , Erik L. Hedberg , Mark W. Kellogg
IPC分类号： G11C11/407 , G11C7/10 , G11C7/22 , G11C11/401 , G06F13/00
CPC分类号： G11C7/1072 , G11C7/22
摘要： A memory device is provided which stacks commands and internally executes each command at the appropriate time, thereby ensuring contiguous data I/O. The memory device is capable of initiating memory accesses either immediately or "stacking" the command along with a "clock count". The clock count defines the number of clock cycles that must occur prior to execution of the command by the memory device. The memory device initiates memory accesses either immediately, or delayed by the number of clocks defined by the clock count for that command. The memory device operates as a slave to the memory controller and therefore has no ability to execute instructions at a time other than that defined by the memory controller.
摘要翻译：提供一种存储器件，其堆叠命令并在适当的时间内部执行每个命令，从而确保连续的数据I / O。存储器件能够立即启动存储器访问或者“堆叠”命令以及“时钟计数”。时钟计数定义在存储器件执行命令之前必须发生的时钟周期数。存储器设备立即启动存储器访问，或延迟由该命令的时钟计数定义的时钟数。存储器件作为存储器控制器的从设备操作，因此在与由存储器控制器定义的时间以外的时间不具有执行指令的能力。

5. 发明授权

US5969997A Narrow data width DRAM with low latency page-hit operations 失效
标题翻译：狭窄的数据宽度DRAM，具有低延迟页命中操作
公开(公告)号：US5969997A
公开(公告)日：1999-10-19
申请号：US942825
申请日：1997-10-02
申请人： Michael P. Clinton , Marc R. Faucher , Erik L. Hedberg , Mark W. Kellogg , Wilbur D. Pricer
发明人： Michael P. Clinton , Marc R. Faucher , Erik L. Hedberg , Mark W. Kellogg , Wilbur D. Pricer
IPC分类号： G11C11/41 , G11C11/401 , G11C11/407 , G11C11/409 , G11C15/00
CPC分类号： G11C11/409 , G11C11/407
摘要： A high speed Random Access Memory (RAM) array device includes several logical banks, each of which can be uniquely addressed. Each of these logical banks contains a unique memory array segment and associated page register, the latter serving as a temporary storage location during high-speed page hit operations. To reduce latency during an initial page hit, further array optimization is realized by segmenting each logical bank into two segments with one, smaller segment, comprising a faster random access memory (FRAM) for storing initial data in a data stream. A high speed page register connects the FRAM directly to a multiplexer/demultiplexer connected to the device I/O ports bypassing an internal bus protocol such that the initial data can be transferred between the FRAM and the I/O ports faster thereby improving page-hit latency. Hence, segmenting the logical banks to include only a small high speed segment results in a performance gain approaching what could be achieved by implementing the entire memory device with a high speed FRAM, but at much lower cost.
摘要翻译：高速随机存取存储器（RAM）阵列器件包括几个逻辑存储体，每个逻辑存储体可以被唯一地寻址。这些逻辑组中的每一个包含唯一的存储器阵列段和相关联的页寄存器，后者在高速页命中操作期间用作临时存储位置。为了在初始页面命中期间减少延迟，通过将每个逻辑存储体分割成具有一个较小段的两个段来实现进一步的阵列优化，其包括用于在数据流中存储初始数据的更快的随机存取存储器（FRAM）。高速页寄存器将FRAM直接连接到绕过内部总线协议的设备I / O端口连接的多路复用器/解复用器，从而可以更快地在FRAM和I / O端口之间传输初始数据，从而提高页命中率潜伏。因此，将逻辑存储体分割为仅包含小的高速段导致通过以高速FRAM实现整个存储器件而可以以低得多的成本实现可达到的性能增益。

6. 发明授权

US07132841B1 Carrier for test, burn-in, and first level packaging 失效
标题翻译：用于测试，老化和一级包装的载体
公开(公告)号：US07132841B1
公开(公告)日：2006-11-07
申请号：US09588617
申请日：2000-06-06
申请人： Claude L. Bertin , Wayne F. Ellis , Mark W. Kellogg , William R. Tonti , Jerzy M. Zalesinski , James M. Leas , Wayne J. Howell
发明人： Claude L. Bertin , Wayne F. Ellis , Mark W. Kellogg , William R. Tonti , Jerzy M. Zalesinski , James M. Leas , Wayne J. Howell
IPC分类号： G01R31/26 , G01R31/28
CPC分类号： G01R31/2867 , G11C5/04 , G11C29/06 , G11C29/1201 , G11C29/48 , G11C29/56016 , G11C29/785 , G11C2029/2602 , G11C2029/5602 , H01L22/22 , H01L22/32 , H01L2924/0002 , H01L2924/00
摘要： A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier. The carrier is formed of a flex material. It can also be formed of printed circuit board material. A window in the flex permits invoking redundancy on each chip after burn-in is complete, significantly improving yield as compared with present schemes that do not permit repair after burn-in.
摘要翻译：在载体上提供多个半导体器件用于测试或烧录。然后将载体切割以提供单个芯片上载波部件或多芯片载波部件。载体用作每个芯片的第一级封装。因此，载体用于测试和烧录和包装的双重目的。可以在每个芯片或载体上提供诸如内置自检引擎的引线减少机构，并且连接到载体的触点用于测试和老化步骤。切割后的最终包装包括至少一个已知的良好的模具，并且可以包括载体上的芯片阵列，例如SIMM或DIMM。最终的包装也可以是一堆芯片，每个芯片都安装在单独的载体上。堆叠的载体通过沿着堆叠的侧面安装的基板彼此连接，该基板沿着每个载体的边缘电连接到焊盘一排。载体由柔性材料形成。它也可以由印刷电路板材料形成。柔性窗口允许在烧坏完成后在每个芯片上调用冗余度，与不允许在老化后修复的现有方案相比，显着提高产量。

7. 发明授权

US07394268B2 Carrier for test, burn-in, and first level packaging 失效
标题翻译：用于测试，老化和一级包装的载体
公开(公告)号：US07394268B2
公开(公告)日：2008-07-01
申请号：US11531140
申请日：2006-09-12
申请人： Claude L. Bertin , Wayne F. Ellis , Mark W. Kellogg , William R. Tonti , Jerzy M. Zalesinski , James M. Leas , Wayne J. Howell
发明人： Claude L. Bertin , Wayne F. Ellis , Mark W. Kellogg , William R. Tonti , Jerzy M. Zalesinski , James M. Leas , Wayne J. Howell
IPC分类号： G01R31/02
CPC分类号： G01R31/2867 , G11C5/04 , G11C29/06 , G11C29/1201 , G11C29/48 , G11C29/56016 , G11C29/785 , G11C2029/2602 , G11C2029/5602 , H01L22/22 , H01L22/32 , H01L2924/0002 , H01L2924/00
摘要： A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier.
摘要翻译：在载体上提供多个半导体器件用于测试或烧录。然后将载体切割以提供单个芯片上载波部件或多芯片载波部件。载体用作每个芯片的第一级封装。因此，载体用于测试和烧录和包装的双重目的。可以在每个芯片或载体上提供诸如内置自检引擎的引线减少机构，并且连接到载体的触点用于测试和老化步骤。切割后的最终包装包括至少一个已知的良好的模具，并且可以包括载体上的芯片阵列，例如SIMM或DIMM。最终的包装也可以是一堆芯片，每个芯片都安装在单独的载体上。堆叠的载体通过沿着堆叠的侧面安装的基板彼此连接，该基板沿着每个载体的边缘电连接到焊盘一排。

8. 发明授权

US06327664B1 Power management on a memory card having a signal processing element 失效
标题翻译：对具有信号处理元件的存储卡进行电源管理
公开(公告)号：US06327664B1
公开(公告)日：2001-12-04
申请号：US09302916
申请日：1999-04-30
申请人： Timothy J. Dell , Bruce G. Hazelzet , Mark W. Kellogg , Christopher P. Miller
发明人： Timothy J. Dell , Bruce G. Hazelzet , Mark W. Kellogg , Christopher P. Miller
IPC分类号： G06F132
CPC分类号： G06F1/3275 , G06F1/3203 , Y02D10/13 , Y02D10/14
摘要： An improved memory module and its use in a computer system is provided. The module includes a DSP first and second individually addressable banks of memory chips. The first bank is configured to function principally under the control of the signal processing element and the second bank is configured to function principally under the control of a system memory controller, although all the portions of each of the memory banks is addressable by both the signal processing element and the system memory controller. Both banks of memory chips can be placed in at least one higher power state and at least one lower power state by either the system memory controller or the DSP. The activity of each bank is sensed while in the higher power state, and the condition of each of the banks is sensed with respect to any activity during operation of the memory bank at the higher power state. The power state of each bank can be changed by either the signal processing element or the system memory controller responsive to preselected conditions of each bank. Each memory bank is returned to a predetermined known condition when changing from a lower power state to a higher power state. This is especially important when the memory bank assigned to the system controller is placed in another state by the DSP.
摘要翻译：提供了一种改进的存储器模块及其在计算机系统中的应用。该模块包括DSP第一和第二可单独寻址的存储器芯片组。第一组被配置为主要在信号处理元件的控制下起作用，并且第二存储体被配置为主要在系统存储器控制器的控制下起作用，尽管每个存储体的所有部分都可以由信号处理元件和系统存储器控制器。两个存储芯片组可以通过系统存储器控制器或DSP被置于至少一个较高功率状态和至少一个较低功率状态。在较高功率状态下感测每个存储体的活动，并且相对于在较高功率状态的存储体的操作期间的任何活动来感测每个存储体的状况。响应于每个银行的预选条件，可以通过信号处理元件或系统存储器控制器改变每个存储体的电源状态。当从较低功率状态改变到较高功率状态时，每个存储体返回到预定的已知状态。当分配给系统控制器的存储体被DSP置于另一状态时，这尤其重要。

9. 发明授权

US06385685B1 Memory card utilizing two wire bus 失效
公开(公告)号：US06385685B1
公开(公告)日：2002-05-07
申请号：US09833871
申请日：2001-04-12
申请人： Timothy J. Dell , Bruce G. Hazelzet , Mark W. Kellogg , Clarence R. Ogilvie , Paul C. Stabler
发明人： Timothy J. Dell , Bruce G. Hazelzet , Mark W. Kellogg , Clarence R. Ogilvie , Paul C. Stabler
IPC分类号： G06F1338
CPC分类号： G11C5/066
摘要： A serial bus and connection to a device on a computer system through a system memory controller is provided on a memory card having a DSP and a memory bus controller to allow the DSP on the memory card to gain access to the system device without using the system memory bus. The serial bus is a two wire serial bus connecting the device to the DSP through the system memory controller. If more than one memory card is present with DSPs or more than one device is contending for access, the system memory controller or arbitrate the access of each memory card or contending device. In such case the serial bus will signal the system memory controller when it wants access to the particular device, and the system memory controller will act as arbitrator to grant or not grant access to the particular memory card or device requesting access. If access is granted the bus memory controller outputs the required control or command word on the serial bus followed by the address and the required data. This serial information is received by the system memory controller which packets it, and, upon completion, outputs the information rapidly on a parallel bus, e.g. a PCI bus to the device which needs the information.

10. 发明授权

US07539800B2 System, method and storage medium for providing segment level sparing 有权
标题翻译：系统，方法和存储介质，用于提供段级备份
公开(公告)号：US07539800B2
公开(公告)日：2009-05-26
申请号：US10903188
申请日：2004-07-30
申请人： Timothy J. Dell , Frank D. Ferraiolo , Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
发明人： Timothy J. Dell , Frank D. Ferraiolo , Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
IPC分类号： G06F13/00 , G06F11/00
CPC分类号： G06F11/201 , G06F11/104
摘要： A memory subsystem that includes segment level sparing. The memory subsystem includes a cascaded interconnect system with segment level sparing. The cascaded interconnect system includes two or more memory assemblies and a memory bus. The memory bus includes multiple segments and the memory assemblies are interconnected via the memory bus.
摘要翻译：一个内存子系统，包括段级备份。存储器子系统包括具有段级保护的级联互连系统。级联互连系统包括两个或多个存储器组件和存储器总线。存储器总线包括多个段，并且存储器组件经由存储器总线互连。

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