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1. 发明授权

US06881996B2 Metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer 有权
标题翻译：金属绝缘体金属（MIM）电容器结构在铜CMOS电路中使用焊盘保护层
公开(公告)号：US06881996B2
公开(公告)日：2005-04-19
申请号：US10935376
申请日：2004-09-07
申请人： Chun-Hon Chen , Ssu-Pin Ma , Ta-Hsun Yeh , Yen-Shih Ho , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou
发明人： Chun-Hon Chen , Ssu-Pin Ma , Ta-Hsun Yeh , Yen-Shih Ho , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou
IPC分类号： H01L21/02 , H01L21/8238 , H01L21/8242 , H01L23/522 , H01L27/08 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L28/60 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor structure and method of fabrication for CMOS circuits having copper interconnections are described. The method provides metal capacitors with high figure of merit Q (Xc/R) and which does not require additional masks and metal layers. The method forms a copper capacitor bottom metal (CBM) electrode while concurrently forming the pad contacts and level of copper interconnections by the damascene process. An insulating (Si3N4) metal protect layer is formed on the copper and a capacitor interelectrode dielectric layer is formed. A metal protecting buffer is used to protect the thin interelectrode layer, and openings are etched to pad contacts and interconnecting lines. A TiN/AlCu/TiN metal layer is deposited and patterned to form the capacitor top metal (CTM) electrodes, the next level of interconnections, and to provide a pad protect layer on the copper pad contacts. The thick TiN/AlCu/TiN CTM electrode reduces the capacitor series resistance and improves the capacitor figure of merit Q, while the pad protect layer protects the copper from corrosion.
摘要翻译：描述了具有铜互连的CMOS电路的金属绝缘体金属（MIM）电容器结构和制造方法。该方法提供具有高品质因数Q（X / C / R）的金属电容器，并且不需要额外的掩模和金属层。该方法形成铜电容器底部金属（CBM）电极，同时通过镶嵌工艺形成焊盘触点和铜互连水平。在铜上形成绝缘（Si 3 N 4 N 4）金属保护层，形成电容器电极间电介质层。使用金属保护缓冲器来保护薄的电极间层，并且蚀刻开口以焊接触点和互连线。沉积并图案化TiN / AlCu / TiN金属层以形成电容器顶部金属（CTM）电极，下一级互连，并在铜焊盘触点上提供焊盘保护层。厚TiN / AlCu / TiN CTM电极降低了电容器串联电阻，提高了电容器的品质因数Q，而焊盘保护层保护铜免受腐蚀。

2. 发明授权

US06472721B2 Dual damascene interconnect structures that include radio frequency capacitors and inductors 有权
标题翻译：双镶嵌互连结构，包括射频电容器和电感器
公开(公告)号：US06472721B2
公开(公告)日：2002-10-29
申请号：US09963749
申请日：2001-09-27
申请人： Ssu-Pin Ma , Chun-Hon Chen , Ta-Hsun Yeh , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou , Yen-Shih Ho
发明人： Ssu-Pin Ma , Chun-Hon Chen , Ta-Hsun Yeh , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou , Yen-Shih Ho
IPC分类号： H01L2943
CPC分类号： H01L28/40 , H01L21/3212 , H01L21/76838 , H01L28/56 , H01L28/60 , H01L28/90
摘要： In many mixed-signal or radio frequency Rf applications, inductors and capacitors are needed at the same time. For a high performance inductor devices, a thick metal layer is needed to increase performance, usually requiring an extra masking process. The present invention describes both a structure and method of fabricating both copper metal-insulator-metal (MIM) capacitors and thick metal inductors, simultaneously, with only one mask, for high frequency mixed-signal or Rf, CMOS applications, in a damascene and dual damascene trench/via process. High performance device structures formed by this invention include: parallel plate capacitor bottom metal (CBM) electrodes and capacitor top metal (CTM) electrodes, metal-insulator-metal (MIM) capacitors, thick inductor metal wiring, interconnects and contact vias.
摘要翻译：在许多混合信号或射频Rf应用中，同时需要电感器和电容器。对于高性能电感器件，需要厚金属层来提高性能，通常需要额外的掩模工艺。本发明同时描述了铜金属 - 绝缘体 - 金属（MIM）电容器和厚金属电感器的结构和方法，同时仅使用一个掩模用于大马士革中的高频混合信号或Rf，CMOS应用，双镶嵌沟/通孔工艺。本发明形成的高性能器件结构包括：平行电容器底部金属（CBM）电极和电容器顶部金属（CTM）电极，金属 - 绝缘体 - 金属（MIM）电容器，厚电感器金属布线，互连和接触通孔。

3. 发明授权

US06329234B1 Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow 有权
标题翻译：铜工艺兼容CMOS金属 - 绝缘体 - 金属电容器结构及其工艺流程
公开(公告)号：US06329234B1
公开(公告)日：2001-12-11
申请号：US09624026
申请日：2000-07-24
申请人： Ssu-Pin Ma , Chun-Hon Chen , Ta-Hsun Yeh , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou , Yen-Shih Ho
发明人： Ssu-Pin Ma , Chun-Hon Chen , Ta-Hsun Yeh , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou , Yen-Shih Ho
IPC分类号： H01L218238
CPC分类号： H01L28/40 , H01L21/3212 , H01L21/76838 , H01L28/56 , H01L28/60 , H01L28/90
摘要： In many mixed-signal or radio frequency Rf applications, inductors and capacitors are needed at the same time. For a high performance inductor devices, a thick metal layer is needed to increase performance, usually requiring an extra masking process. The present invention describes both a structure and method of fabricating both copper metal-insulator-metal (MIM) capacitors and thick metal inductors, simultaneously, with only one mask, for high frequency mixed-signal or Rf, CMOS applications, in a damascene and dual damascene trench/via process. High performance device structures formed by this invention include: parallel plate capacitor bottom metal (CBM) electrodes and capacitor top metal (CTM) electrodes, metal-insulator-metal (MIM) capacitors, thick inductor metal wiring, interconnects and contact vias.
摘要翻译：在许多混合信号或射频Rf应用中，同时需要电感器和电容器。对于高性能电感器件，需要厚金属层来提高性能，通常需要额外的掩模工艺。本发明同时描述了铜金属 - 绝缘体 - 金属（MIM）电容器和厚金属电感器的结构和方法，同时仅使用一个掩模用于大马士革中的高频混合信号或Rf，CMOS应用，双镶嵌沟/通孔工艺。本发明形成的高性能器件结构包括：平行电容器底部金属（CBM）电极和电容器顶部金属（CTM）电极，金属 - 绝缘体 - 金属（MIM）电容器，厚电感器金属布线，互连和接触通孔。

4. 发明申请

US20050029566A1 Method for making a new metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer 有权
标题翻译：使用焊盘保护层在铜CMOS电路中制造新的金属 - 绝缘体 - 金属（MIM）电容器结构的方法
公开(公告)号：US20050029566A1
公开(公告)日：2005-02-10
申请号：US10935376
申请日：2004-09-07
申请人： Chun-Hon Chen , Ssu-Pin Ma , Ta-Hsun Yeh , Yen-Shih Ho , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou
发明人： Chun-Hon Chen , Ssu-Pin Ma , Ta-Hsun Yeh , Yen-Shih Ho , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou
IPC分类号： H01L21/02 , H01L21/8238 , H01L21/8242 , H01L23/522 , H01L27/08 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L28/60 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor structure and method of fabrication for CMOS circuits having copper interconnections are described. The method provides metal capacitors with high figure of merit Q (Xc/R) and which does not require additional masks and metal layers. The method forms a copper capacitor bottom metal (CBM) electrode while concurrently forming the pad contacts and level of copper interconnections by the damascene process. An insulating (Si3N4) metal protect layer is formed on the copper and a capacitor interelectrode dielectric layer is formed. A metal protecting buffer is used to protect the thin interelectrode layer, and openings are etched to pad contacts and interconnecting lines. A TiN/AlCu/TiN metal layer is deposited and patterned to form the capacitor top metal (CTM) electrodes, the next level of interconnections, and to provide a pad protect layer on the copper pad contacts. The thick TiN/AlCu/TiN CTM electrode reduces the capacitor series resistance and improves the capacitor figure of merit Q, while the pad protect layer protects the copper from corrosion.
摘要翻译：描述了具有铜互连的CMOS电路的金属绝缘体金属（MIM）电容器结构和制造方法。该方法提供具有高品质因数Q（Xc / R）的金属电容器，并且不需要额外的掩模和金属层。该方法形成铜电容器底部金属（CBM）电极，同时通过镶嵌工艺形成焊盘触点和铜互连水平。在铜上形成绝缘（Si3N4）金属保护层，形成电容器电极间电介质层。使用金属保护缓冲器来保护薄的电极间层，并且蚀刻开口以焊接触点和互连线。沉积并图案化TiN / AlCu / TiN金属层以形成电容器顶部金属（CTM）电极，下一级互连，并在铜焊盘触点上提供焊盘保护层。厚TiN / AlCu / TiN CTM电极降低了电容器串联电阻，提高了电容器的品质因数Q，而焊盘保护层保护铜免受腐蚀。

5. 发明授权

US06812088B1 Method for making a new metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer 失效
标题翻译：使用焊盘保护层在铜CMOS电路中制造新的金属 - 绝缘体 - 金属（MIM）电容器结构的方法
公开(公告)号：US06812088B1
公开(公告)日：2004-11-02
申请号：US10167856
申请日：2002-06-11
申请人： Chun-Hon Chen , Ssu-Pin Ma , Ta-Hsun Yeh , Yen-Shih Ho , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou
发明人： Chun-Hon Chen , Ssu-Pin Ma , Ta-Hsun Yeh , Yen-Shih Ho , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： This MIM structure provides metal capacitors with high figure of merit Q (Xc/R) and does not require additional masks and metal layers. A copper capacitor bottom metal (CBM) electrode is formed, while concurrently forming the pad contacts and level of copper interconnections by the damascene process. An insulating (Si3N4) metal protect layer is formed on the copper and a capacitor interelectrode dielectric layer is formed. A metal protecting buffer protects the thin interelectrode layer, and openings are etched to pad contacts and interconnecting lines. A TiN/AlCu/TiN metal layer is deposited and patterned to form the capacitor top metal (CTM) electrodes, the next level of interconnections, and to provide a pad protect layer on the copper pad contacts. The thick TiN/AlCu/TiN CTM electrode reduces the capacitor series resistance and improves the capacitor figure of merit Q, while the pad protect layer protects the copper from corrosion.
摘要翻译：该MIM结构提供具有高品质因数Q（Xc / R）的金属电容器，并且不需要额外的掩模和金属层。形成铜电容器底部金属（CBM）电极，同时通过镶嵌工艺同时形成焊盘触点和铜互连水平。在铜上形成绝缘（Si3N4）金属保护层，形成电容器电极间电介质层。金属保护缓冲器保护薄的电极间层，并且蚀刻开口以焊接触点和互连线。沉积并图案化TiN / AlCu / TiN金属层以形成电容器顶部金属（CTM）电极，下一级互连，并在铜焊盘触点上提供焊盘保护层。厚TiN / AlCu / TiN CTM电极降低了电容器串联电阻，提高了电容器的品质因数Q，而焊盘保护层保护铜免受腐蚀。

6. 发明授权

US06667217B1 Method of fabricating a damascene copper inductor structure using a sub-0.18 um CMOS process 有权
标题翻译：使用亚0.18μmCMOS工艺制造镶嵌铜电感器结构的方法
公开(公告)号：US06667217B1
公开(公告)日：2003-12-23
申请号：US09795115
申请日：2001-03-01
申请人： Heng-Ming Hsu , Jau-Yuann Chung , Yen-Shih Ho , Chun-Hon Chen , Kuo-Reay Peng , Ta-Hsun Yeh , Kong-Beng Thei , Ssu-Pin Ma
发明人： Heng-Ming Hsu , Jau-Yuann Chung , Yen-Shih Ho , Chun-Hon Chen , Kuo-Reay Peng , Ta-Hsun Yeh , Kong-Beng Thei , Ssu-Pin Ma
IPC分类号： H01L2120
CPC分类号： H01L28/10 , H01F17/0006 , H01F41/042 , H01L23/5227 , H01L27/08 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A process for integrating the fabrication of a thick, copper inductor structure, with the fabrication of narrow channel length CMOS devices, has been developed. The integrated process features the use of only one additional photolithographic masking step, used to form the opening in an IMD layer, that will accommodate the subsequent inductor structure. After forming damascene type openings in the same IMD layer, in the CMOS region, copper is deposited and then defined, to result in a thick, copper inductor structure, in the opening in the IMD layer, in a first region of a semiconductor substrate, as well as to result in copper interconnect structures, in the damascene type openings located in a second region of the semiconductor structure, used for the narrow channel length CMOS devices. The use of a thick, copper inductor structure, equal to the thickness of the IMD layer, results in increased inductance, or an increased quality factor, when compared to counterparts formed with thinner metal inductors.
摘要翻译：已经开发了将厚铜电感器结构的制造与窄沟道长度CMOS器件的制造相结合的工艺。集成过程的特征在于仅使用一个额外的光刻掩模步骤，用于在IMD层中形成开口，其将适应随后的电感器结构。在相同的IMD层中形成镶嵌型开口之后，在CMOS区域中，沉积铜，然后限定铜，以在半导体衬底的第一区域中的IMD层的开口中产生厚的铜电感器结构，以及在半导体结构的第二区域中的镶嵌型开口中产生用于窄沟道长度CMOS器件的铜互连结构。与使用较薄的金属电感器形成的对应物相比，使用等于IMD层的厚度的厚铜电感器结构导致增加的电感或增加的品质因数。

7. 发明授权

US06444517B1 High Q inductor with Cu damascene via/trench etching simultaneous module 有权
标题翻译：高Q电感与Cu镶嵌通孔/沟槽蚀刻同时模块
公开(公告)号：US06444517B1
公开(公告)日：2002-09-03
申请号：US10055091
申请日：2002-01-23
申请人： Heng-Ming Hsu , Shyh-Chyi Wong , Chaochieh Tsai , Ssu-Pin Ma , Chao-Cheng Chen , Liang-Kun Huang
发明人： Heng-Ming Hsu , Shyh-Chyi Wong , Chaochieh Tsai , Ssu-Pin Ma , Chao-Cheng Chen , Liang-Kun Huang
IPC分类号： H01L218244
CPC分类号： H01L28/10 , H01F17/0006 , H01F41/041 , H01L21/76838 , H01L27/08
摘要： A new method is provided for the creation of an inductive over the surface of a semiconductor substrate. A first layer of metal is created in a layer of dielectric, a second layer of metal is created overlying the first layer of metal. The first layer of metal combined with the second layer of metal form an inductor of increased height, reducing the resistivity of the inductor, increasing the Q value of the inductor. The new method of creating an inductor can be combined with creating contact points that connect to contact points in the active region of the surface of a semiconductor substrate.
摘要翻译：提供了一种用于在半导体衬底的表面上产生电感的新方法。在电介质层中产生第一金属层，产生覆盖在第一金属层上的第二金属层。第一层金属与第二层金属组合形成一个增加高度的电感器，降低了电感的电阻率，增加了电感的Q值。创建电感器的新方法可以与产生连接到半导体衬底的表面的有源区域中的接触点的接触点组合。

8. 发明授权

US07038294B2 Planar spiral inductor structure with patterned microelectronic structure integral thereto 有权
公开(公告)号：US07038294B2
公开(公告)日：2006-05-02
申请号：US09821521
申请日：2001-03-29
申请人： Ssu-Pin Ma , Yen-Shih Ho
发明人： Ssu-Pin Ma , Yen-Shih Ho
IPC分类号： H01L29/00
CPC分类号： H01L24/05 , H01L23/5227 , H01L23/645 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05556 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48463 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/48844 , H01L2224/48847 , H01L2224/49171 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01027 , H01L2924/01029 , H01L2924/01067 , H01L2924/01079 , H01L2924/01083 , H01L2924/05042 , H01L2924/14 , H01L2924/15787 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/30105 , H01L2924/30107 , Y10S257/909 , H01L2224/48824 , H01L2924/00 , H01L2224/48744
摘要： Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a spirally patterned conductor layer which terminates in a microelectronic structure within the center of the spirally patterned conductor layer. The spirally patterned conductor layer forms a planar spiral inductor, and the microelectronic structure formed within the center of the spirally patterned conductor layer further comprises a series of electrically interconnected sub-patterns. The method contemplates a microelectronic fabrication fabricated in accord with the method. The microelectronic fabrication is fabricated with optimal performance while occupying minimal microelectronic substrate area.

9. 发明授权

US08737545B2 Receiver chain gain selection 有权
标题翻译：接收机链增益选择
公开(公告)号：US08737545B2
公开(公告)日：2014-05-27
申请号：US13326248
申请日：2011-12-14
申请人： Sujai Chari , Ssu-Pin Ma
发明人： Sujai Chari , Ssu-Pin Ma
IPC分类号： H04L27/08
CPC分类号： H03G3/3068 , H04B2001/1054
摘要： Apparatuses, methods and systems of selecting a gain setting of a receiver chain are disclosed. One method includes bypassing a filter portion of the receiver chain and sampling a bypass receive signal while the filter portion of the receiver chain is bypassed. If the sampled bypass receive signal is determined to be saturated greater than a threshold, then selecting a gain setting of the receive chain as a function of the saturation. Further, the filter portion of the receive chain is included while sampling a receive signal with the selected gain setting.
摘要翻译：公开了选择接收机链的增益设置的设备，方法和系统。一种方法包括绕过接收器链的滤波器部分并对旁路接收信号进行采样，同时接收器链的滤波器部分被旁路。如果采样旁路接收信号被确定为饱和大于阈值，则选择接收链的增益设置作为饱和度的函数。此外，包括接收链的滤波器部分，同时采用所选择的增益设置对接收信号进行采样。

10. 发明申请

US20050242892A1 Method and apparatus for producing an oscillating signal 有权
标题翻译：用于产生振荡信号的方法和装置
公开(公告)号：US20050242892A1
公开(公告)日：2005-11-03
申请号：US11117321
申请日：2005-04-29
申请人： Ssu-Pin Ma , Shao-Hua Chen
发明人： Ssu-Pin Ma , Shao-Hua Chen
IPC分类号： H03K3/00 , H03K3/012 , H03K3/013 , H03K3/0231 , H03K3/26
CPC分类号： H03K3/013 , H03K3/012 , H03K3/0231
摘要： A method for producing an oscillating signal comprises: generating an oscillating signal by discharging after charging to a high trigger level and charging after discharging to a low trigger level; and turbo-charging at the initial of a change-over from charging to discharging while resuming a normal charging/discharging thereafter, and vice versa. The present invention makes use of the turbo-charging/discharging for a linear compensation, such that the produced oscillating signal has the features of concurrently eliminating phase noises and jitters as well as maintaining the modulation linearity.
摘要翻译：一种用于产生振荡信号的方法包括：通过在充电之后放电到高触发电平并且在放电到低触发电平之后进行充电来产生振荡信号; 并且在从充电到放电的转换的初始阶段进行涡轮增压，同时在此之后恢复正常的充电/放电，反之亦然。本发明利用用于线性补偿的涡轮增压/放电，使得所产生的振荡信号具有同时消除相位噪声和抖动以及维持调制线性的特征。

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