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1. 发明授权

US06444517B1 High Q inductor with Cu damascene via/trench etching simultaneous module 有权
标题翻译：高Q电感与Cu镶嵌通孔/沟槽蚀刻同时模块
公开(公告)号：US06444517B1
公开(公告)日：2002-09-03
申请号：US10055091
申请日：2002-01-23
申请人： Heng-Ming Hsu , Shyh-Chyi Wong , Chaochieh Tsai , Ssu-Pin Ma , Chao-Cheng Chen , Liang-Kun Huang
发明人： Heng-Ming Hsu , Shyh-Chyi Wong , Chaochieh Tsai , Ssu-Pin Ma , Chao-Cheng Chen , Liang-Kun Huang
IPC分类号： H01L218244
CPC分类号： H01L28/10 , H01F17/0006 , H01F41/041 , H01L21/76838 , H01L27/08
摘要： A new method is provided for the creation of an inductive over the surface of a semiconductor substrate. A first layer of metal is created in a layer of dielectric, a second layer of metal is created overlying the first layer of metal. The first layer of metal combined with the second layer of metal form an inductor of increased height, reducing the resistivity of the inductor, increasing the Q value of the inductor. The new method of creating an inductor can be combined with creating contact points that connect to contact points in the active region of the surface of a semiconductor substrate.
摘要翻译：提供了一种用于在半导体衬底的表面上产生电感的新方法。在电介质层中产生第一金属层，产生覆盖在第一金属层上的第二金属层。第一层金属与第二层金属组合形成一个增加高度的电感器，降低了电感的电阻率，增加了电感的Q值。创建电感器的新方法可以与产生连接到半导体衬底的表面的有源区域中的接触点的接触点组合。

2. 发明授权

US06555477B1 Method for preventing Cu CMP corrosion 有权
标题翻译：防止Cu CMP腐蚀的方法
公开(公告)号：US06555477B1
公开(公告)日：2003-04-29
申请号：US10152939
申请日：2002-05-22
申请人： Chen-Fa Lu , Chin-Hsiung Ho , Mei-Ling Chen , Liang-Kun Huang
发明人： Chen-Fa Lu , Chin-Hsiung Ho , Mei-Ling Chen , Liang-Kun Huang
IPC分类号： H01L21302
CPC分类号： H01L21/7684 , H01L21/02071 , H01L21/3212
摘要： A method for preventing or reducing corrosion of copper containing semiconductor features during chemical mechanical polishing (CMP) including providing a semiconductor wafer polishing surface including a copper layer overlying a copper filled anisotropically etched feature; polishing the semiconductor wafer polishing surface according to a first CMP process to remove at least a portion the copper layer to reveal a portion of an underlying barrier/adhesion layer; polishing the semiconductor wafer polishing surface according to a second CMP process including applying a neutralizing solution; polishing the semiconductor wafer polishing surface according to a third CMP process including applying a copper corrosion inhibitor solution; and, polishing the semiconductor wafer polishing surface according to at least a fourth CMP process to remove a remaining portion of the underlying barrier/adhesion layer.
摘要翻译：一种用于在化学机械抛光（CMP）期间防止或减少含铜半导体特征的腐蚀的方法，包括提供半导体晶片抛光表面，所述半导体晶片抛光表面包括覆盖铜填充的各向异性蚀刻特征的铜层; 根据第一CMP工艺抛光半导体晶片抛光表面以去除铜层的至少一部分以露出下面的阻挡/粘附层的一部分; 根据包括施加中和溶液的第二CMP工艺抛光半导体晶片抛光表面; 根据包括施加铜腐蚀抑制剂溶液的第三CMP工艺抛光半导体晶片抛光表面; 以及根据至少第四CMP工艺对所述半导体晶片抛光表面进行抛光以去除所述下面的阻挡/粘合层的剩余部分。

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